CN113223965B - Method for compensating internal gate potential loss of negative capacitor transistor - Google Patents
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66568—Lateral single gate silicon transistors
- H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
- H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
- H01L29/66598—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET forming drain [D] and lightly doped drain [LDD] simultaneously, e.g. using implantation through the wings a T-shaped layer, or through a specially shaped layer
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- H—ELECTRICITY
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- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
- H01L29/0843—Source or drain regions of field-effect devices
- H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/6684—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a ferroelectric gate insulator
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
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- H—ELECTRICITY
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/78391—Field effect transistors with field effect produced by an insulated gate the gate comprising a layer which is used for its ferroelectric properties
Abstract
The invention discloses a method for compensating the internal gate potential loss of a negative capacitor transistor close to a drain electrode side under high drain electrode voltage. The specific implementation method comprises the following steps: after the metal gate TiN material deposition process of the N-type negative capacitance transistor is completed, a certain concentration of P-type ions are additionally implanted into the channel region close to the drain terminal (drain) locally, so that the doping concentration of the P-type ions in the local region at the interface of the drain and the channel is improved, and the prior process technology and steps are kept unchanged. The method is characterized in that the method has good compatibility with the prior nNCFET process, and the manufacturing process does not obviously increase the process difficulty and complexity. The invention can relieve the phenomenon of negative differential resistance caused by the reduction of the output current of the negative capacitor transistor along with the rise of the drain voltage, and keeps the excellent performance of the nNCFET.
Description
Technical Field
The invention belongs to the field of novel semiconductor integrated information devices, and relates to a method for compensating gate potential loss in a negative capacitor transistor.
Background
The modern information society has higher and higher requirements on the performance of integrated circuit chips, and the channel size of a metal-oxide-semiconductor field effect transistor (MOSFET) which forms a basic unit of a chip system is forced to be continuously reduced, so that the chips obtain higher integration level. As the feature size of the device enters the nanometer scale, the power consumption density of the chip is also increasing continuously with the increase of the integration level. Therefore, excessive power consumption density in the chip inevitably consumes more energy, and a great challenge is brought to the continuous power supply of the wearable device and the battery of the internet of things device, which becomes a barrier for further development of the chip technology.
Theoretical analysis has shown that the main reason for the increasing power consumption density on an integrated chip is due to the boltzmann thermodynamic limitation, and the Subthreshold Swing (SS) of a conventional transistor has a theoretical limit of 60mV/decade at room temperature, which indicates that at least 60mV of gate voltage is required for a 10-fold increase in current, resulting in the threshold voltage not being able to be scaled down continuously, and as a result the supply voltage is limited by the threshold voltage and not being able to be further reduced as expected. Since the power consumption of the device is closely related to the power supply voltage, further reduction of the power consumption of the chip becomes a troublesome problem.
To overcome the above-mentioned energy consumption bottleneck, negative capacitance transistors (NCFETs) with steep subthreshold swing (SS below 60mV/decade at room temperature) are one of the most promising alternatives. The negative capacitor transistor has the characteristics of high switching current ratio, strong switching activity, low static power consumption and strong driving capability, and is attracted by international attention due to the compatibility of the manufacturing process and the traditional CMOS technology.
However, the common N-type NCFET (NCFET) has an inherent performance defect that, under a condition of a lower gate bias voltage, the inner gate potential of the channel near the drain (i.e. the potential at the interface between the ferroelectric layer and the gate oxide layer, as shown in fig. 1) of the NCFET decreases when the drain voltage increases, so that the output current is easily reduced along with the increase of the drain voltage, and a Negative Differential Resistance (NDR) phenomenon, which is an index phenomenon of the NCFET, occurs, and this causes a delay and a time delay in the application of digital circuits, thereby hindering the application of logic circuits of the device.
Disclosure of Invention
Aiming at the problem of internal gate potential loss of the nNCFET under high drain bias voltage, the invention provides a method for compensating the internal gate potential reduction of the nNCFET close to the drain side so as to improve the output channel current under the high drain voltage. The method does not change the manufacturing process steps of the original nNCFET, realizes the improvement of the overall performance of the nNCFET device only by the tiny adjustment of local process technology, can make up the inherent performance defects of the existing nNCFET, and promotes the nNCFET to have better application prospect in circuits.
The technical scheme adopted by the invention for solving the technical problem is as follows:
the invention adds a channel injection step of P-type ions in the manufacturing process of an N-type negative capacitance transistor, and particularly injects P-type ions with certain concentration into a channel region close to a drain end after finishing a metal grid TiN material deposition process of the N-type negative capacitance transistor and before carrying out a lightly doped drain ion injection process so as to improve the local doping concentration of the P-type doping ions at the junction of a drain and a channel.
Preferably, the length of the implanted P-type ion region is not more than 25% of the total gate length, and the concentration of implanted P-type ions is higher than the doping concentration of the substrate by an order of magnitude.
Preferably, the doping surface of the P-type ion implanted region follows a gaussian distribution, and gradually decreases the doping concentration outward in a 90-degree sector from the highest doping concentration near the junction of the upper surface of the channel and the drain end as the center until the outermost layer is doped close to the substrate.
Preferably, the P-type ion implantation depth does not exceed the LDD junction depth.
The invention has the beneficial effects that: according to the invention, the P-type ions with a certain concentration are additionally injected into the channel region close to the drain end of the nNCFET, so that the local doping concentration of the channel at the junction of the drain and the channel is improved, the interface electric field of the gate and the substrate is improved, the effect of compensating the gate potential loss in the position close to the drain caused by the increase of the drain voltage of the nNCFET is achieved, the channel current is further improved, and the inherent performance of the nNCFET is maintained. The method has good compatibility with the traditional nNCFET process, and the difficulty and complexity of the process are not obviously increased in the manufacturing process. The invention can solve the problem that the output channel current of the negative capacitor transistor is reduced along with the increase of the drain voltage, overcomes the inherent negative differential resistance phenomenon of the negative capacitor transistor, and keeps the overall performance advantage of the negative capacitor transistor.
Drawings
FIG. 1 is a schematic diagram of an N-type negative capacitance transistor (nNCFET);
fig. 2 schematic diagram of additional p-type ion implantation in ncfets.
Detailed Description
According to the invention, a certain concentration of P-type ions are additionally injected into the channel region of the N-type negative capacitance transistor (nNCFET) in the inversion mode, which is close to the drain terminal (drain), so that the doping concentration of the P-type ions close to the junction of the drain and the channel is increased, and the purpose of increasing the gate potential of the nNCFET close to the inner side of the drain terminal is achieved. The invention particularly relates to a method for compensating the inner gate potential of an nNCFET close to the inner side of a drain end under high drain voltage and improving the output channel current, wherein for an nNCFET under lower gate voltage bias, the inner gate potential close to the inner side of a drain is reduced due to the increase of the drain voltage, and the output channel current is reduced.
In the process of the conventional nNCFET manufacturing process, the traditional nNCFET mainly comprises the following process steps:
(1) Preparing an undoped silicon or silicon-on-insulator (SOI) substrate;
(2) High dielectric constant dielectric HfO 2 Depositing a gate oxide layer;
(3) Depositing a metal gate TiN material;
(4) Performing Lightly Doped Drain (LDD) ion implantation;
(5) Forming a transistor isolation layer and carrying out source-drain epitaxial growth;
(6) Depositing photoresist and etching process;
(7) Completing the rapid thermal annealing at 1050 ℃;
(8) A laser annealing process at 1398 ℃ for 1.0 ms;
(9) Finally, electrode contact nickel silicification is carried out.
The invention adds a channel ion implantation step. The detailed process and sequence of the specific implementation method are as follows: after the deposition process of the metal gate TiN material of the nNCFET is finished, a certain concentration of P-type ions are additionally implanted into the channel region close to the drain end, so that the doping concentration of the P-type ions at the boundary of the drain and the channel is improved, and the rest of the prior manufacturing process technology is kept unchanged. The method is characterized in that the method has good compatibility with the prior nNCFET process technology, and the whole realization scheme and the manufacturing steps do not obviously increase the difficulty and the complexity of the prior process.
Details of the doping implant are as follows: after the deposition of metal gate TiN material of nNCFET is completed and before the Lightly Doped Drain (LDD) ion implantation process is carried out, the length of the channel region near the drain end (drain) does not exceed the total gate length L g 25 percent, additionally implanting P-type ions with a certain concentration, wherein the concentration of the implanted ions is about one order of magnitude higher than that of the substrate doping concentration, namely, the substrate doping concentration is set as N sub Then the average doping concentration of this region is about 10N sub And the doping surface follows Gaussian distribution, and the highest doping concentration near the joint of the upper surface of the channel and the drain end is taken as the center, and the doping concentration is gradually reduced outwards in a sector of 90 degrees until the outermost layer is doped close to the substrate. The whole implantation depth H of the additional doping ions n Not exceeding the junction depth H of the LDD j I.e. ensure H n ≤H j The additional doped region is shown in fig. 2, and LDD ion implantation is performed after doping is completed. The sidewall processing steps in the figure are after the LDD ion implantation process, in order to effectively mask the lightly doped LDD structure in the subsequent heavily doped drain ion implantation.
The main principle of the invention is as follows: the increase in drain voltage causes a decrease in the amount of internal gate charge, resulting in a decrease in the voltage across the ferroelectric layer of the ncfet, causing a decrease in the internal gate voltage below the ferroelectric layer, which in turn causes an internal gate potential near the drain
Lower than the potential at the electrode close to the source
Resulting in so-called internal surface potential losses and consequently in a reduction of the channel output current strength, which affects the performance of the ncfet. According to the invention, a certain concentration of P-type ions are additionally injected into a channel region of the channel close to the drain end (drain), so that the ion doping concentration at the junction of the drain and the channel is improved, the distance between a drain-channel depletion region and a grid is reduced, the interface electric field between the grid and a substrate is improved, and the aim of compensating the nNCFET caused by the increase of the drain voltage is achievedThe internal gate surface potential loss near the drain reduces the channel current defect and improves the performance of the ncfet.
It will be appreciated by those of ordinary skill in the art that the above implementation steps and schemes are only for illustration and explanation of the present invention, and are not meant to be a limitation of the present invention, and that variations and modifications of the above implementation steps and schemes are within the scope of the present invention.
Claims (2)
1. A method of compensating for gate potential loss in a negative capacitor transistor, comprising:
in the manufacturing process of the N-type negative capacitance transistor, a channel injection step of P-type ions is added, specifically, after the deposition process of a metal gate TiN material of the N-type negative capacitance transistor is completed and before the lightly doped drain ion injection process is carried out, P-type ions with certain concentration are additionally injected into a channel region close to a drain end so as to improve the local doping concentration of the P-type doping ions at the junction of a drain and a channel;
the length of the P-type ion implantation area is not more than 25% of the total grid length, and the concentration of the P-type ion implantation is higher than the doping concentration of the substrate by one order of magnitude; the doping surface of the implanted P-type ion region follows Gaussian distribution, and the doping concentration is gradually reduced outwards in a sector of 90 degrees by taking the highest doping concentration close to the joint of the upper surface of the channel and the drain end as the center until the outermost layer is doped close to the substrate.
2. A method of compensating for gate potential loss in a negative capacitor transistor as claimed in claim 1, wherein: the P-type ion implantation depth does not exceed the junction depth of the LDD.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1411076A (en) * | 2001-10-04 | 2003-04-16 | 富士通株式会社 | Semiconductor device and mfg. method thereof |
| US20040110324A1 (en) * | 2002-12-09 | 2004-06-10 | Tsu-Jae King | Method of forming a negative differential resistance device |
| CN106711224A (en) * | 2015-11-16 | 2017-05-24 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| CN111463284A (en) * | 2020-04-10 | 2020-07-28 | 上海华力集成电路制造有限公司 | N-type FET and method of manufacturing the same |
| WO2020191792A1 (en) * | 2019-03-26 | 2020-10-01 | 湘潭大学 | Gate-last ferroelectric gate field effect transistor and preparation method therefor |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1411076A (en) * | 2001-10-04 | 2003-04-16 | 富士通株式会社 | Semiconductor device and mfg. method thereof |
| US20040110324A1 (en) * | 2002-12-09 | 2004-06-10 | Tsu-Jae King | Method of forming a negative differential resistance device |
| CN106711224A (en) * | 2015-11-16 | 2017-05-24 | 台湾积体电路制造股份有限公司 | Semiconductor device |
| WO2020191792A1 (en) * | 2019-03-26 | 2020-10-01 | 湘潭大学 | Gate-last ferroelectric gate field effect transistor and preparation method therefor |
| CN111463284A (en) * | 2020-04-10 | 2020-07-28 | 上海华力集成电路制造有限公司 | N-type FET and method of manufacturing the same |
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