CN111863937B - N-type TFET device with buried layer structure and preparation method thereof - Google Patents

N-type TFET device with buried layer structure and preparation method thereof Download PDF

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CN111863937B
CN111863937B CN202010537107.5A CN202010537107A CN111863937B CN 111863937 B CN111863937 B CN 111863937B CN 202010537107 A CN202010537107 A CN 202010537107A CN 111863937 B CN111863937 B CN 111863937B
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region
channel
drain
buried layer
heavily doped
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CN111863937A (en
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王斌
陈睿
罗昭
蔺孝堃
陈瑶
胡辉勇
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Xidian University
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Xidian University
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate

Abstract

The invention discloses an n-type TFET device with a buried layer structure and a preparation method thereof, wherein the n-type TFET device comprises: a substrate; the surface of the substrate is provided with a source region, a drain region and a channel region; the source region and the drain region are respectively positioned at two ends of the channel region; a buried layer is arranged below the channel region, the buried layer starts at the junction of the channel region and the source region, and the length of the buried layer is smaller than that of the channel region; a grid structure is arranged above the channel region; the grid structure comprises a grid electrode and a grid dielectric layer positioned between the grid electrode and the channel region; and the source region and the drain region are respectively and correspondingly provided with a source electrode and a drain electrode. The n-type TFET device provided by the invention reduces the requirement on the work function of the gate metal, so that the threshold voltage of the device is reduced, and the GIDL effect is inhibited; meanwhile, due to the introduction of the substrate tunneling junction, the tunneling area of the device is increased, the on-state current is improved, and the performance of the device is improved.

Description

N-type TFET device with buried layer structure and preparation method thereof
Technical Field
The invention belongs to the technical field of semiconductor integrated circuits, and particularly relates to an n-type TFET device with a buried layer structure and a preparation method thereof.
Background
With the continuous reduction of the size of CMOS transistors and the continuous increase of chip integration density, power consumption becomes a key issue for limiting the development of integrated circuits. The sub-threshold swing characterizes the speed of the device in switching from an off state to an on state, and the larger the sub-threshold swing is, the shorter the time the device is in the sub-threshold state is, and the lower the power consumption of the device is. However, due to the restriction of the carrier injection mechanism, the minimum limit that the subthreshold swing of the MOSFET can reach at room temperature is 60mV/dec, so that the conventional micro-nano electronic device becomes difficult to meet the requirement of the low power consumption design of the modern advanced integrated circuit. Therefore, tunneling Field Effect Transistors (TFETs) with low sub-threshold swings have received widespread attention in recent years from various research institutions.
Different from the working mechanism of the traditional field effect transistor, the TFET device realizes the starting of the device by utilizing a band-to-band tunneling (BTBT) mechanism of a channel and a source/drain region based on a Pin structure. Therefore, the TFET device has small subthreshold swing, small off-state current and good short channel effect. However, in the on state of the conventional TFET, the tunneling channel between the channel and the source/drain region is only a very thin strong inversion layer controlled by the gate at the surface of the channel, the tunneling area is very small, and the tunneling is a typical "point" tunneling, and the low on-state current and the high threshold voltage of the device are main factors limiting the development of the TFET device.
In order to increase the on-state current of the TFET device, the prior art proposes an N-type TFET (PNN-TFET) having a P + N + structure. The device realizes effective depletion of a channel region by using large-work-function metal (such as Au, pt and the like) introduced on a gate electrode under zero bias; when the device is in the on-state, significant tunneling occurs throughout the region at the P + N + junction formed by the source and channel regions due to the heavy doping of the channel, and thus the device has the characteristics of a "line" tunneling device and operates in the flat-band or accumulation mode rather than the inversion mode of a conventional TFET.
However, to ensure that the channel under zero bias can be fully depleted, PNN-TFET requires that the channel thickness be thin enough so that the device on-state current is still much smaller than that of MOSFET devices; in addition, the increase in work function difference causes the threshold voltage of the device to increase and introduces severe gate induced leakage current (GIDL effect) in the off state.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides an n-type TFET device having a buried layer structure and a method for fabricating the same. The technical problem to be solved by the invention is realized by the following technical scheme:
an n-type TFET device having a buried layer structure, comprising:
a substrate;
the surface of the substrate is provided with a source region, a drain region and a channel region; the source region and the drain region are respectively positioned at two ends of the channel region;
the channel region comprises a channel heavily doped region and a channel lightly doped region; a buried layer is arranged below the channel heavily doped region, starts at the junction of the channel region and the source region, and has the same length as the channel heavily doped region;
a grid structure is arranged above the channel region; the gate structure comprises a gate electrode and a gate dielectric layer positioned between the gate electrode and the channel region;
and a source electrode and a drain electrode are correspondingly arranged on the source region and the drain region respectively.
In one embodiment of the present invention, the source electrode, the drain electrode, and the gate electrode are made of the same metal, and the metal is a low work function metal.
In one embodiment of the present invention, the buried layer is at a distance L from the drain region gap And L is gap Greater than 50nm.
In one embodiment of the invention, the buried layer is a heavily doped region, and the doping concentration is higher than that of the channel region; and the buried layer and the channel region are doped in a special shape to form a substrate PN junction.
In one embodiment of the present invention, the drain region includes a drain ohmic region and an LDD region, and the LDD region is adjacent to the channel lightly doped region, and the drain ohmic region is far away from the channel lightly doped region; wherein, the first and the second end of the pipe are connected with each other,
the source electrode is positioned above the source region, and the drain electrode is positioned above the drain region ohmic region.
In one embodiment of the invention, the source region is uniformly heavily doped; heavily doping the drain region ohmic region; the LDD region has a doping concentration lower than that of the drain ohmic region,
and the LDD region and the channel lightly doped region have the same doping concentration to form an LDR region.
In one embodiment of the present invention, the drain region and the channel region are n-type doped; the substrate, the buried layer and the source region are doped in a p-type mode.
In one embodiment of the invention, the thickness of the channel region is smaller than the width of the space charge region of the substrate PN junction in the channel region, so as to ensure effective pinch-off of the channel without external grid voltage.
Another embodiment of the present invention provides a method for manufacturing an n-type TFET device having a buried structure, including the steps of:
obtaining p with a certain doping concentration - A substrate;
at said p - Forming heavily doped p on substrate ++ A buried layer;
n with a certain doping concentration is grown on the whole surface of the substrate - The thickness of the epitaxial layer is thinned and adjusted so that the thickness of the epitaxial layer is the same as that of a preset channel region;
at said n - Forming n on the epitaxial layer + A channel heavily doped region; wherein, said n + A channel heavily doped region is positioned in the p ++ A buried layer;
at said n + Forming heavily doped p on one side of heavily doped channel region ++ A source region;
at said n + N is formed on the other side of the heavily doped channel region ++ An ohmic region is drained, and an LDR region is naturally formed; wherein the LDR region is located at the n + Between the channel region and the ohmic region of the drain region and including the channel region adjacent to the n + N of heavily doped channel region - A lightly doped region of the channel and adjacent to the n ++ An LDD region of the drain ohmic region;
at said n + Heavily doped channel region and the n - Preparing a gate dielectric layer on the lightly doped channel region;
at said p ++ Source region, said n ++ And forming metal electrodes on the drain region ohmic region and the gate dielectric layer to finish the manufacture of the device.
The invention has the beneficial effects that:
1. according to the n-type TFET device, the heavily doped buried layer is introduced below the channel, and the depletion region of the substrate PN junction between the heavily doped buried layer and the channel region is utilized, so that the channel is pinched off in an off state, the requirement on the work function of gate metal is reduced, the threshold voltage of the device is reduced, and the GIDL effect is inhibited;
2. the n-type TFET device provided by the invention introduces two tunneling surfaces which are respectively: the tunneling area of the device is greatly increased, the on-state current is increased, and the performance of the device is improved;
3. the n-type TFET device provided by the invention inhibits the 'point' tunneling from the buried layer to the drain electrode in the off state by introducing the LDR region, further weakens the GIDL effect and reduces the off-state current of the device;
4. the n-type TFET device provided by the invention can increase the tunneling area of the substrate by increasing the length of the buried layer, thereby increasing the on-state current of the device and reducing the swing amplitude of the subthreshold value;
5. the source electrode, the drain electrode and the gate electrode of the n-type TFET device can be realized by using the same work function metal, and the process complexity is reduced.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
Fig. 1 is a schematic structural diagram of an n-type TFET device having a buried layer structure according to an embodiment of the present invention;
fig. 2 is a graph comparing transfer characteristics of an n-type TFET device having a buried layer structure according to an embodiment of the present invention with a conventional PNN-TFET;
fig. 3 shows an n-type TFET device with a buried layer structure at V according to an embodiment of the present invention DS ＝1V，L gap The graph of the variation of the transfer characteristic of the device along with the length of the buried layer when the thickness is 50 nm;
fig. 4 is a schematic diagram of a method for manufacturing an n-type TFET device having a buried layer structure according to an embodiment of the present invention;
fig. 5a to 5h are schematic diagrams illustrating a process flow of manufacturing an n-type TFET device having a buried layer structure according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example one
Fig. 1 is a schematic structural diagram of an n-type TFET device having a buried layer structure according to an embodiment of the present invention, where the n-type TFET device includes:
a substrate 10;
a source region 20, a drain region 30 and a channel region 40 are arranged on the surface of the substrate 10; wherein the source region 20 and the drain region 30 are respectively located at two ends of the channel region 40;
a buried layer 11 is arranged below the channel region 40, the buried layer 11 starts from the junction of the channel region 40 and the source region 20, and the length of the buried layer 11 is smaller than that of the channel region 40;
a gate structure 60 is arranged above the channel region 40; the gate structure 60 includes a gate electrode 62 and a gate dielectric layer 61 between the gate electrode 62 and the channel region 40;
a source electrode 21 and a drain electrode 33 are provided on the source region 20 and the drain region 30, respectively.
In this embodiment, the substrate material may be a semiconductor material such as Ge or Si, and lightly doped. The substrate 10 used in this embodiment has a doping concentration of 1 × 10 17 cm -3 A p-type Ge substrate. Further, a thin layer on the surface of the substrate may be sequentially divided into a source region, a channel region and a drain region. A gate structure is arranged right above the channel region. The channel region and the drain region are doped in an n-type mode, and the source region is doped in a p-type mode.
Further, the buried layer 11 is introduced under the channel region 40, requiring heavy doping to deplete the channel, starting at the junction between the channel region and the source region and ending at a point in the channel region, and having a distance L from the drain region gap ，L gap Typically greater than 50nm. In this embodiment, L gap Take 50nm.
In this embodiment, the buried layer 11 is heavily doped p-type, with a doping concentration higher than that of the channel region 40, and is doped with the channel region 40 in a special shape to form a substrate PN junction. Specifically, the buried layer of the present embodiment has a doping concentration of 1 × 10 20 cm -3 The thickness of the buried layer is 10nm.
In the n-type TFET device provided by the embodiment, the heavily doped buried layer is introduced below the channel, the heavily doped buried layer and the channel are doped in a special shape to form the substrate PN junction, and the depletion region of the substrate PN junction is utilized to clamp the channel in an off state, so that the requirement on the work function of the gate metal is reduced, the threshold voltage of the device is reduced, the device performance is improved, and the GIDL effect is inhibited.
In addition, in the present embodiment, the same metal is used for the source electrode 23, the drain electrode 33, and the gate electrode 51, and the metal is a low work function metal.
The embodiment reduces the requirement on the work function of the gate metal by introducing the heavily doped buried layer, so that the source electrode, the drain electrode and the gate electrode can use the same low work function metal, and the process complexity is reduced. Specifically, the present embodiment may employ a metallic Al group as the electrode metal.
Further, with continued reference to fig. 1, the channel region 40 includes a heavily doped channel region 41 and a lightly doped channel region 42, wherein,
the heavily doped channel region 41 is a channel region covered by a buried layer below, the lightly doped channel region 42 is a channel region not covered by a buried layer,
in the present embodiment, the doping concentration of the channel lightly doped region 42 is lighter than that of the channel heavily doped region 41. Specifically, the doping concentration of the lightly doped region of the channel is 5 × 10 18 cm -3 The doping concentration of the heavily doped channel region is 1 multiplied by 10 19 cm -3 。
In this embodiment, the channel region 40 is doped n-type, and the thickness of the channel region 40 must be smaller than the space charge region width of the substrate PN junction in the channel to ensure effective pinch-off of the channel in the absence of an applied bias. Specifically, when the thickness of the channel is 10-30nm, the substrate PN junction can effectively pinch off the channel, and the channel thickness is preferably 10nm in this embodiment.
Further, with continued reference to fig. 1, the Drain region 30 includes a Drain ohmic region 31 and an LDD (lightly Doped Drain) region 32, the LDD region 32 is adjacent to the channel lightly Doped region 42, and the Drain ohmic region 31 is far away from the channel lightly Doped region 42; wherein the content of the first and second substances,
the source electrode 21 is located above the source region 20, and the drain electrode 33 is located above the drain ohmic region 31.
Specifically, the source region 20 is uniformly heavily doped; the drain region ohmic region 31 is heavily doped; the LDD region 32 has a doping concentration lower than that of the drain ohmic region 31, wherein,
the LDD region 32 and the channel lightly doped region 42 have the same doping concentration to form a LDR region (lightly doped region) 50.
Specifically, in this embodiment, a side of the drain region away from the channel lightly doped region is heavily doped, which is called a drain region ohmic region, for forming an ohmic contact. The part adjacent to the lightly doped region of the channel has a slightly lower doping concentration than the part farther away from the channel. In this embodiment, the doping concentration of the source region is 1 × 10 20 cm -3 The doping concentration of the drain region ohmic region is 1 × 10 20 cm -3 The doping concentration of LDD region is 5 × 10 18 cm -3 。
The n-type TFET device provided by this embodiment has several differences compared with the conventional PNN-TFET device: 1) The conventional PNN-TFET device utilizes the work function of a grid electrode to realize the depletion of a current carrier in a channel region so as to turn off the device, but the embodiment introduces a heavy doping buried layer below a channel, the heavy doping buried layer and the channel are doped in a special shape to form a PN junction, and the depletion region of the substrate junction is utilized to realize the pinch-off of the channel in the off state; 2) The conventional PNN-TFET device only has one tunneling surface between a source region and a channel region, but in the embodiment, besides the tunneling surface between the source region and the channel region, one tunneling surface is additionally arranged between a buried layer and the channel region, and the tunneling area of a substrate can be increased by increasing the length of the buried layer; 3) The gate of the conventional PNN-TFET device uses a high work function metal, the source and the drain use a low work function metal, and the source, the gate and the drain of the embodiment all use a low work function metal; the embodiment introduces an LDR region to suppress the "point" tunneling from the channel to the drain due to the introduction of the heavily doped buried layer, further weaken the GIDL effect, and reduce the off-state current of the device. Compared with the conventional PNN-TFET device, the n-type TFET device provided by the embodiment has better performance.
Referring to fig. 2, fig. 2 is a comparison graph of transfer characteristics of an n-type TFET device having a buried layer structure and a conventional PNN-TFET device when the channel thickness and the channel doping are the same, where the gate metal of the conventional PNN-TFET device is Au, the source metal and the drain metal are Al, and the drain voltage is 1V. As can be seen from fig. 2, the off-state current of the n-type TFET device with the buried layer structure provided in this embodiment is reduced by 4 orders of magnitude compared with the conventional PNN-TFET device, and the on-state current of the n-type TFET device is increased by 2 orders of magnitude compared with the on-state current of the conventional PNN-TFET device, which reaches 3.4 × 10 -4 A/μm(V GS = 1V), which indicates that the n-type TFET device with the buried layer structure provided in the present embodiment has a more excellent current switching ratio; meanwhile, as can be seen from fig. 2, the conventional PNN-TFET device has a significant GIDL effect, which is avoided by the present invention.
In addition, on the premise of the same channel thickness and concentration, the threshold voltage of the n-type TFET device with the buried layer structure provided by the embodiment is 0.13V which is far smaller than that of the conventional PNN-TFET device by adopting a linear epitaxial method. These all show that the n-type TFET device with the buried layer structure has better performance than the conventional PNN-TFET device.
In addition, the n-type TFET device with the buried layer structure provided by the embodiment can also increase the buried layer length L BP The tunneling area of the substrate is increased, so that the on-state current of the device is increased, the sub-threshold swing is reduced, and the performance of the device is improved.
Referring to fig. 3, fig. 3 shows an n-type TFET device with a buried layer structure in V according to an embodiment of the present invention DS ＝1V，L gap Time device of =50nmTransfer characteristic of the device with buried layer length L BP A graph of the variation relationship of (c). As can be seen from FIG. 3, when L is BP Increasing from 50nm to 650nm, the on-state current was from 3.6X 10 -4 The A/mum is increased to 2.1 multiplied by 10 -3 A/mum, the threshold voltage is reduced from 0.13V to 0.08V, the average subthreshold swing is reduced from 54mV/dec to 34mV/dec, and the performance of the device is obviously improved.
Example two
On the basis of the first embodiment, the present embodiment provides a method for manufacturing an n-type TFET device having a buried layer structure, please refer to fig. 4, where fig. 4 is a schematic diagram of a method for manufacturing an n-type TFET device having a buried layer structure according to an embodiment of the present invention, including:
s1: obtaining p with a certain doping concentration - A substrate.
In this embodiment, the substrate material is a lightly doped type, and may be a single crystal Ge substrate, a Si substrate, or other substrate materials.
S2: at said p - Forming heavily doped p on substrate ++ A buried layer.
Specifically, a single crystal Ge substrate may be selected and subjected to photolithography to form a buried ion implantation window; ion doping is carried out at the position corresponding to the buried layer to form a p-type buried layer; the buried layer and the substrate are doped in the same type, and the buried layer is heavily doped.
S3: n with a certain doping concentration is grown on the whole surface of the substrate - And thinning and adjusting the epitaxial layer to enable the thickness of the epitaxial layer to be the same as that of the preset channel region.
Specifically, on the substrate where the buried layer is formed in step S2, an n-type Ge epitaxial layer is epitaxially grown with the doping concentration set to that of the designed LDR region.
In this embodiment, the doping concentration of the Ge epitaxial layer is set to the concentration of the LDR region, so that the manufacturing efficiency can be improved. After the epitaxial layer is formed, the thickness of the epitaxial layer is further reduced and adjusted so that the thickness of the epitaxial layer is equal to the thickness of the designed channel.
S4: at said n - Formation of n on epitaxial layer + Channel weightA doped region; wherein, said n + A channel heavily doped region is positioned in the p ++ Above the buried layer.
Specifically, the Ge epitaxial layer is photoetched to form an ion implantation window at the position of a well-defined channel heavily doped region, and n is carried out at the corresponding position + Doping to obtain n + And the channel is a heavily doped region.
S5: at said n + Forming heavily doped p on one side of the heavily doped channel region ++ A source region.
Specifically, photoetching the Ge epitaxial layer to form an ion implantation window at a well-defined source region position; p-type heavy doping is carried out at the corresponding position to obtain p ++ A source region.
S6: at n + N is formed on the other side of the heavily doped channel region ++ An ohmic region is drained, and an LDR region is naturally formed; wherein the LDR region is located at n + Between the channel region and the drain region ohmic region and including near n + N of heavily doped channel region - Lightly doped region of channel and near n ++ And LDD region of the drain region ohmic region.
Specifically, photoetching the Ge epitaxial layer to form an ion implantation window at the well-determined drain region ohmic region; respectively carrying out n-type heavy doping at corresponding positions to obtain n ++ Drain ohmic region while being naturally n + And an LDR region is formed between the channel region and the drain region ohmic region. Further, the LDR region includes a region near n + N of heavily doped channel region - Lightly doped region of channel and near n ++ And LDD region of the drain region ohmic region.
S7: at n + Heavily doped channel region and n - And preparing a gate dielectric layer on the lightly doped channel region.
Specifically, the epitaxial layer is lithographed to expose n + Heavily doped channel region and n - And sputtering a layer of gate dielectric material on the area where the channel lightly doped region (namely the channel region) is positioned to form a gate dielectric layer. The gate dielectric layer material may be a high-K dielectric material, such as hafnium oxide.
S8: at p ++ Source region, n ++ Forming metal electrodes on the drain region ohmic region and the gate dielectric layerAnd (5) manufacturing a finished device.
Specifically, photoetching is carried out on the whole substrate, and metal contact hole regions which are well defined on a source region, a drain region ohmic region and a gate dielectric layer are exposed;
then, depositing a metal layer on the whole epitaxial layer;
and finally, photoetching the whole substrate again, and removing the metal outside the contact hole to obtain a source electrode, a gate electrode and a drain electrode, so as to finish the manufacture of the TFET device.
EXAMPLE III
The following describes the manufacturing method of the present invention in detail with specific reference to the device simulation parameters in the first embodiment.
Referring to fig. 5a to 5h, fig. 5a to 5h are schematic diagrams illustrating a process of fabricating an n-type TFET device having a buried layer structure according to an embodiment of the present invention, including:
step 1: selecting the doping concentration to be 1 × 10 17 cm -3 P of (a) - Type single crystal Ge is the starting material, which is used as the substrate 101, as shown in fig. 5 a.
Step 2: carrying out first photoetching to form a buried ion implantation window in a specific area of the substrate 101; performing selective ion implantation, and annealing to activate impurities to form a doping concentration of 1 × 10 on the single crystal Ge substrate 20 cm -3 P of thickness 10nm ++ A type buried layer 102 as shown in fig. 5 b.
And step 3: epitaxially growing a substrate with a buried layer formed in step 2 and having a doping concentration of 5 × 10 18 cm -3 N of (a) - Type Ge epilayer 103 as shown in fig. 5 c.
And 4, step 4: the epitaxial layer is thinned so that the thickness of the Ge epitaxial layer 103 is 10nm of the designed thickness of the channel region 104.
And 5: performing a second photolithography to expose the epitaxial layer of the heavily doped channel region on the Ge epitaxial layer 103, and performing ion implantation to form an ion doped region with a doping concentration of 1 × 10- 19 cm -3 N of (A) to (B) + The type channel is heavily doped region 104 as shown in fig. 5 d.
Step 6: performing a third photolithography at Ge exposing the epitaxial layer of the source region part on the epitaxial layer 103 and performing ion implantation to form a doping concentration of 1 × 10 in the Ge epitaxial layer 103 20 cm -3 P of (a) ++ Source region 105 as shown in fig. 5 e.
And 7: performing fourth photolithography to expose the epitaxial layer of the drain region 111 away from the channel region 109 on the Ge epitaxial layer 103, and performing ion implantation to form an ion-doped region with a doping concentration of 1 × 10- 20 cm -3 N of (A) to (B) ++ A drain ohmic region 106, wherein a region between the heavily doped channel region and the drain ohmic region is an LDR region 110, and the LDR region 110 comprises a region close to n + N of heavily doped channel region 104 - Channel lightly doped region 108 and near n ++ LDD regions 107 of drain ohmic region 106 as shown in fig. 5 f.
And 8: performing a fifth photolithography to expose n + Heavily doped channel region 104 and n - The channel lightly doped region 108 (i.e., the channel region 109) is located, and a layer of hafnium oxide is sputtered over the channel region 109 as a gate dielectric layer to form a gate oxide layer 112, as shown in fig. 5 g.
And step 9: a sixth photolithography is performed to expose the metal contact hole regions on the gate oxide 112, the source 105, and the drain ohmic region 106, and a layer of metal is deposited over the entire device surface.
Step 10: a seventh photolithography is performed to remove the metal except the contact hole, thereby forming a gate electrode 113, a source electrode 115, and a drain electrode 114, as shown in fig. 5 h.
And finishing the preparation of the n-channel TFET device with the buried layer structure.
In the method for manufacturing an n-type TFET device according to this embodiment, the related process may be appropriately adjusted according to actual conditions. However, regardless of the specific implementation manner, all structural, methodological or functional changes based on the device structure proposed by the present invention should be included in the protection scope of the present invention.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims (9)

1. An n-type TFET device having a buried layer structure, comprising:
a substrate (10);
a source region (20), a drain region (30) and a channel region (40) are arranged on the surface of the substrate (10); wherein the source region (20) and the drain region (30) are respectively located at two ends of the channel region (40);
the channel region (40) comprises a channel heavily doped region (41) and a channel lightly doped region (42); a buried layer (11) is arranged below the channel heavily doped region (41), and the buried layer (11) starts from the junction of the channel region (40) and the source region (20) and has the same length as the channel heavily doped region (41);
a gate structure (60) is arranged above the channel region (40); the gate structure (60) comprises a gate electrode (62) and a gate dielectric layer (61) between the gate electrode (62) and the channel region (40);
and a source electrode (21) and a drain electrode (33) are correspondingly arranged on the source region (20) and the drain region (30) respectively.
2. The n-type TFET device with the buried structure of claim 1, wherein the source electrode (21), the drain electrode (33), and the gate electrode (62) are of the same metal, and the metal is a low work function metal.
3. The n-type TFET device with buried layer structure of claim 1, wherein the buried layer (11) is at a distance L from the drain region (30) gap And L is gap Greater than 50nm.
4. The n-type TFET device with buried layer structure of claim 1, characterized in that the buried layer (11) is a heavily doped region and has a doping concentration higher than that of the channel region (40); and the buried layer (11) and the channel region (40) are doped in a special shape to form a substrate PN junction.
5. The n-type TFET device with a buried structure according to claim 1, wherein the drain region (30) comprises a drain ohmic region (31) and an LDD region (32), and the LDD region (32) is adjacent to the channel lightly doped region (42), the drain ohmic region (31) being distant from the channel lightly doped region (42); wherein the content of the first and second substances,
the source electrode (21) is located above the source region (20), and the drain electrode (33) is located above the drain ohmic region (31).
6. The n-type TFET device with buried layer structure of claim 1, characterized in that the source region (20) is uniformly heavily doped; the drain region ohmic region (31) is heavily doped; the doping concentration of the LDD region (32) is lower than that of the drain ohmic region (31), wherein,
the LDD region (32) and the channel lightly doped region (42) are doped at the same concentration to form an LDR region (50).
7. The n-type TFET device with buried structure of claim 1, wherein the drain region (30) and the channel region (40) are n-type doped; the substrate (10), the buried layer (11) and the source region (20) are doped p-type.
8. The n-type TFET device with a buried layer structure according to claim 4, wherein the thickness of the channel region (40) is smaller than the space charge region width of the substrate PN junction in the channel region (40) to ensure effective pinch-off of the channel in the absence of an applied gate voltage.
9. A preparation method of an n-type TFET device with a buried layer structure is characterized by comprising the following steps:
obtaining p with a certain doping concentration - A substrate;
at said p - Forming heavily doped p on a substrate ++ Buried layer；
Growing n with a certain doping concentration on the whole surface of the substrate - The epitaxial layer is thinned and adjusted, so that the thickness of the epitaxial layer is the same as that of a preset channel region;
at said n - Forming n on the epitaxial layer + A channel heavily doped region; wherein, said n + A channel heavily doped region is positioned in the p ++ A buried layer;
at said n + Forming heavily doped p on one side of heavily doped channel region ++ A source region;
at said n + N is formed on the other side of the heavily doped channel region ++ An ohmic region is drained, and an LDR region is naturally formed; wherein the LDR region is located at the n + Between the channel region and the drain ohmic region, and including a region near the n + N of heavily doped channel region - A lightly doped region of the channel and adjacent to the n ++ An LDD region of the drain ohmic region;
at said n + Heavily doped channel region and the n - Preparing a gate dielectric layer on the channel lightly doped region;
at said p ++ Source region of the n ++ And forming metal electrodes on the drain region ohmic region and the gate dielectric layer to finish the manufacture of the device.
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