CN113964190B - High-mobility p-type polysilicon gate LDMOS device and manufacturing method thereof - Google Patents
High-mobility p-type polysilicon gate LDMOS device and manufacturing method thereof Download PDFInfo
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- CN113964190B CN113964190B CN202010707870.8A CN202010707870A CN113964190B CN 113964190 B CN113964190 B CN 113964190B CN 202010707870 A CN202010707870 A CN 202010707870A CN 113964190 B CN113964190 B CN 113964190B
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 39
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 26
- 239000004065 semiconductor Substances 0.000 claims abstract description 86
- 239000000758 substrate Substances 0.000 claims abstract description 82
- 210000000746 body region Anatomy 0.000 claims abstract description 35
- 108091006146 Channels Proteins 0.000 claims description 53
- 108010075750 P-Type Calcium Channels Proteins 0.000 claims description 22
- 238000005468 ion implantation Methods 0.000 claims description 22
- 239000000463 material Substances 0.000 claims description 8
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000009792 diffusion process Methods 0.000 claims description 4
- 235000012239 silicon dioxide Nutrition 0.000 claims description 3
- 239000000377 silicon dioxide Substances 0.000 claims description 3
- 238000002347 injection Methods 0.000 abstract description 10
- 239000007924 injection Substances 0.000 abstract description 10
- 230000007547 defect Effects 0.000 abstract description 8
- 230000000694 effects Effects 0.000 abstract description 6
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- 238000010586 diagram Methods 0.000 description 4
- 238000009826 distribution Methods 0.000 description 4
- 238000013459 approach Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 2
- 238000002513 implantation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
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Abstract
The invention discloses a p-type polysilicon gate LDMOS device with high mobility and a manufacturing method thereof. The high-mobility p-type polysilicon gate LDMOS device comprises a semiconductor substrate and a grid electrode, wherein a body region contact region and a drift region are distributed in the semiconductor substrate, an active region and a drain region are respectively formed in the body region contact region and the drift region, a channel region is also distributed in the semiconductor substrate, a first doping region is also formed in the channel region, the semiconductor substrate, the grid electrode, the body region contact region and the channel region are of a first doping type, and the source region, the drain region, the drift region and the first doping region are of a second doping type. According to the high-mobility P-type polysilicon gate LDMOS device provided by the invention, the n-type lightly doped region is arranged in the P-type doped channel region, so that the influence of surface defects on electron mobility is reduced, the influence of hot carrier injection effect on the surface of semiconductor equipment and a gate oxide layer is reduced, and the quality factors of the saturation current and the hot carrier injection reliability of the device are further improved.
Description
Technical Field
The invention relates to an LDMOS device, in particular to a p-type polysilicon gate LDMOS device with high mobility and a manufacturing method thereof, and belongs to the technical field of semiconductors.
Background
The conventional N-type LDMOS device structure is shown in fig. 1, in which 100 is an N-type polysilicon gate, 200 is a gate oxide layer, 50 is a heavily doped N-type source region, 20 is a lightly doped N-type drift region, 40 is an N-type heavily doped drain region, 30 is a p-type heavily doped body contact region, 60 is a p-type channel region, and 10 is a p-type substrate.
The structure of fig. 1 above belongs to an enhancement mode device with a threshold voltage greater than zero. With the conventional device structure shown in fig. 1, the device is turned on and off by changing the voltage of the gate, the channel surface is inversely turned on when the gate voltage exceeds the threshold voltage, the device is turned on, the channel is depleted or accumulated when the gate voltage is less than the threshold voltage, and the device is turned off. For the enhanced device, under the conduction condition, a large amount of electrons exist in the inversion layer positioned on the surface of the channel, so that the inversion layer is easily influenced by surface defects, the electron mobility is reduced, the performance of the device is influenced, meanwhile, the surface channel is easily subjected to hot carrier injection effect, new defects are generated in the oxide layer, and the device is invalid
Disclosure of Invention
The invention mainly aims to provide a p-type polysilicon gate LDMOS device with high mobility and a manufacturing method thereof, which are used for overcoming the defects in the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a high-mobility p-type polysilicon gate LDMOS device, which comprises a semiconductor substrate and a grid electrode, wherein a body region contact region and a drift region are distributed in the semiconductor substrate, a source region and a drain region are respectively formed in the body region contact region and the drift region, the source region and the drain region are respectively matched with a source electrode and a drain electrode, a channel region is also distributed in the semiconductor substrate, the channel region is positioned below the grid electrode, a first doping region is also formed in a region, which is close to the surface of the semiconductor substrate, in the channel region, and the first doping region is also electrically contacted with or combined with the source region, wherein the semiconductor substrate, the grid electrode, the body region contact region and the channel region are of a first doping type, and the source region, the drain region, the drift region and the first doping region are of a second doping type;
when the channel region is inversion-formed into an electron layer after the gate voltage exceeds the threshold voltage, the inversion layer near the source region will first occur under the first doped region.
Further, the high mobility p-type polysilicon gate LDMOS device comprises a p-type semiconductor substrate and a p-type doped gate, wherein a p-type heavily doped body region contact region and an n-type lightly doped drift region are distributed in the p-type semiconductor substrate, an n-type heavily doped source region and an n-type heavily doped drain region are respectively formed in the p-type heavily doped body region contact region and the n-type lightly doped drift region, the n-type heavily doped source region and the n-type heavily doped drain region are respectively matched with a source electrode and a drain electrode, a p-type channel region is also distributed in the p-type semiconductor substrate, the p-type channel region is positioned below the p-type doped gate, an n-type lightly doped region is also formed in a region, close to the surface of the p-type semiconductor substrate, and the n-type lightly doped region is also electrically contacted or combined with the n-type heavily doped source region; when the p-doped gate voltage exceeds a threshold voltage, an inversion layer near the n-type heavily doped source region will first occur below the n-type lightly doped region when the p-type channel region is inversion-formed into an electron layer.
The embodiment of the invention also provides a manufacturing method of the high-mobility p-type polysilicon gate LDMOS device, which comprises the following steps:
providing a semiconductor substrate, and manufacturing a grid electrode on the semiconductor substrate;
a body region contact region, a drift region and a channel region are formed in the semiconductor substrate, a source region and a drain region are formed in the body region contact region and the drift region respectively, the source region and the drain region are matched with a source electrode and a drain electrode respectively, and the channel region is positioned below the grid electrode;
and forming a first doped region in the channel region, which is close to the surface of the semiconductor substrate, at least a partial region of the channel region is covered by the first doped region, and the first doped region is electrically contacted or combined with the source region.
Compared with the prior art, the invention has the advantages that: according to the P-type polysilicon gate LDMOS device with high mobility, the n-type lightly doped region is arranged in the P-type doped channel region, so that the doping distribution of the channel region is changed; when the device starts to be conducted, the inversion layer is positioned below the n-type lightly doped region, and gradually thickens and approaches the surface of the channel region along with the lifting of the grid voltage; when the device works, the inversion layer is positioned in the semiconductor substrate and far away from the surface, so that the influence of surface defects on electron mobility is reduced, the influence of hot carrier injection effect on the surface of the semiconductor device and the gate oxide layer is reduced, and the saturation current of the device and the quality factor of hot carrier injection reliability are improved.
Drawings
Fig. 1 is a schematic cross-sectional structure of an n-type LDMOS device structure of the prior art;
fig. 2 is a schematic diagram of a high mobility p-type polysilicon gate LDMOS device according to an exemplary embodiment of the present invention;
fig. 3 is a schematic diagram of another high mobility p-type polysilicon gate LDMOS device in accordance with an exemplary embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a manufacturing process flow structure of a p-type polysilicon gate LDMOS device with high mobility according to an exemplary embodiment of the present invention;
fig. 5 is a schematic diagram illustrating a process flow structure of a high mobility p-type polysilicon gate LDMOS device according to an exemplary embodiment of the present invention.
Detailed Description
In view of the shortcomings in the prior art, the inventor of the present invention has long studied and practiced in a large number of ways to propose the technical scheme of the present invention. The technical scheme, the implementation process, the principle and the like are further explained as follows.
In order to overcome the problems in the prior art, the embodiment of the invention provides a high mobility P-type polysilicon gate LDMOS device, which changes the doping distribution of a channel region by forming an n-type lightly doped region in the P-type doped channel region; when the device starts to be conducted, the inversion layer is positioned below the n-type lightly doped region, and gradually thickens and approaches the surface of the channel region along with the lifting of the grid voltage; when the device works, the inversion layer is positioned in the semiconductor substrate and far away from the surface, so that the influence of surface defects on electron mobility is reduced, the influence of hot carrier injection effect on the surface of the semiconductor device and the gate oxide layer is reduced, and the quality factors of the saturation current of the device and the hot carrier injection reliability are further improved.
Specifically, the embodiment of the invention provides a p-type polysilicon gate LDMOS device with high mobility, which comprises a semiconductor substrate and a grid electrode, wherein a body region contact region and a drift region are distributed in the semiconductor substrate, a source region and a drain region are respectively formed in the body region contact region and the drift region, the source region and the drain region are respectively matched with a source electrode and a drain electrode, a channel region is also distributed in the semiconductor substrate, the channel region is positioned below the grid electrode, a first doping region is also formed in a region, which is close to the surface of the semiconductor substrate, in the channel region, and is also in electrical contact with or electrically combined with the source region, wherein the semiconductor substrate, the grid electrode, the body region contact region and the channel region are of a first doping type, and the source region, the drain region, the drift region and the first doping region are of a second doping type;
when the channel region is inversion-formed into an electron layer after the gate voltage exceeds the threshold voltage, the inversion layer near the source region will first occur under the first doped region.
Further, a second doped region is further formed in the channel region or in a region, close to the surface of the semiconductor substrate, in the first doped region, the second doped region is of the first doped type, and the second doped region is further electrically contacted or electrically combined with the first doped region and the drift region.
Further, at least a partial region of the first doped region is masked by the second doped region.
Further, the doping concentration of the first doping region and the second doping region is 1×1011-6×10 12 cm 2 。
Furthermore, an oxide layer is formed on the surface of the semiconductor substrate, and the grid electrode is arranged above the oxide layer.
Further, the high mobility p-type polysilicon gate LDMOS device comprises a p-type semiconductor substrate and a p-type doped gate, wherein a p-type heavily doped body region contact region and an n-type lightly doped drift region are distributed in the p-type semiconductor substrate, an n-type heavily doped source region and an n-type heavily doped drain region are respectively formed in the p-type heavily doped body region contact region and the n-type lightly doped drift region, the n-type heavily doped source region and the n-type heavily doped drain region are respectively matched with a source electrode and a drain electrode, a p-type channel region is also distributed in the p-type semiconductor substrate, the p-type channel region is positioned below the p-type doped gate, an n-type lightly doped region is also formed in a region, close to the surface of the p-type semiconductor substrate, and the n-type lightly doped region is also electrically contacted or combined with the n-type heavily doped source region; when the p-doped gate voltage exceeds a threshold voltage, an inversion layer near the n-type heavily doped source region will first occur below the n-type lightly doped region when the p-type channel region is inversion-formed into an electron layer.
The embodiment of the invention also provides a manufacturing method of the high-mobility p-type polysilicon gate LDMOS device, which comprises the following steps:
providing a semiconductor substrate, and manufacturing a grid electrode on the semiconductor substrate;
a body region contact region, a drift region and a channel region are formed in the semiconductor substrate, a source region and a drain region are formed in the body region contact region and the drift region respectively, the source region and the drain region are matched with a source electrode and a drain electrode respectively, and the channel region is positioned below the grid electrode;
and forming a first doped region in the channel region, which is close to the surface of the semiconductor substrate, at least a partial region of the channel region is covered by the first doped region, and the first doped region is electrically contacted or combined with the source region.
Further, the manufacturing method also comprises the steps of; and forming a second doped region in the channel region near the surface of the semiconductor substrate or in the region of the first doped region near the surface of the semiconductor substrate, wherein at least a local region of the first doped region is covered by the second doped region, and the second doped region is electrically contacted or combined with the first doped region and the drift region.
Further, the manufacturing method specifically comprises the following steps of; the body region contact region and the drift region are formed by local processing of a semiconductor substrate in an ion implantation and thermal diffusion mode, the source region is formed by local processing of the body region contact region in an ion implantation mode, the drain region is formed by local processing of the drift region in an ion implantation mode, the first doped region is formed by local processing of the channel region in an ion implantation mode, and the second doped region is formed by local processing of the channel region or the first doped region in an ion implantation mode.
Further, the manufacturing method specifically comprises the following steps: and manufacturing an oxide layer on the surface of the semiconductor substrate, and then manufacturing a grid electrode on the oxide layer.
Further, the gate is made of polysilicon.
Further, the material of the oxide layer comprises silicon oxide, and the thickness of the oxide layer is 0.01-0.06nm.
The technical solution, implementation process and principle thereof, etc. will be further explained with reference to the drawings and specific embodiments, and it should be noted that the ion implantation process adopted in the embodiments of the present invention is known to those skilled in the art, and specific process parameter conditions thereof may be adjusted according to specific situations, and are not limited herein.
Referring to fig. 2, in an exemplary embodiment of the present invention, a high mobility p-type polysilicon gate LDMOS device includes a p-type semiconductor substrate 10 and a p-type doped gate 100, a p-type heavily doped body region contact region 30 and an n-type lightly doped drift region 20 are distributed in the p-type semiconductor substrate 10, n-type heavily doped source regions 50 and n-type heavily doped drain regions 40 are formed in the p-type heavily doped body region contact region 30 and the n-type lightly doped drift region 20 respectively, the n-type heavily doped source regions 50 and the n-type heavily doped drain regions 40 are respectively matched with a source and a drain, a p-type channel region 60 is also distributed in the p-type semiconductor substrate 10, the p-type channel region 60 is located under the p-type doped gate 100, an n-type lightly doped region 70 is also formed in a local region of the p-type channel region 60 near the surface of the p-type semiconductor substrate 10, and the n-type lightly doped region 70 is also electrically contacted with or electrically combined with the n-type heavily doped source region 50; when the p-doped gate 100 voltage exceeds the threshold voltage, the inversion of the p-channel region forms an electron layer, the inversion layer near the n-heavily doped source region 50 may occur first under the n-lightly doped region 70.
Specifically, the p-type semiconductor substrate 10 is further provided with a gate oxide layer 200, the p-type doped gate 100 is disposed on the gate oxide layer 200, wherein the material of the p-type doped gate 100 includes polysilicon, the material of the gate oxide layer 200 includes silicon dioxide, and the material of the p-type semiconductor substrate 10 may be silicon.
Referring to fig. 3, in an exemplary embodiment of the present invention, a high mobility p-type polysilicon gate LDMOS device is provided, which includes a p-type semiconductor substrate 10 and a p-type doped gate 100, wherein a p-type heavily doped body region contact region 30 and an n-type lightly doped drift region 20 are distributed in the p-type semiconductor substrate 10, n-type heavily doped source regions 50 and n-type heavily doped drain regions 40 are formed in the p-type heavily doped body region contact region 30 and the n-type lightly doped drift region 20 respectively, the n-type heavily doped source regions 50 and the n-type heavily doped drain regions 40 are respectively matched with a source and a drain, and a p-type channel region 60 is also distributed in the p-type semiconductor substrate 10, the p-type channel region 60 is located under the p-type doped gate 100, an n-type lightly doped region 70 and a p-type lightly doped region 80 are also formed in a local region near the surface of the p-type semiconductor substrate 10, at least the n-type lightly doped region 70 is masked by the p-type doped region 80, and the n-type heavily doped region 70 is electrically combined with the n-type lightly doped region 70 and the n-type lightly doped region 80 or the p-type lightly doped region 80;
when the p-doped gate 100 voltage exceeds the threshold voltage, the inversion of the p-channel region forms an electron layer, the inversion layer near the n-heavily doped source region 50 may occur first under the n-lightly doped region 70.
Specifically, the p-type semiconductor substrate 10 is further provided with a gate oxide layer 200, the p-type doped gate 100 is disposed on the gate oxide layer 200, wherein the material of the p-type doped gate 100 includes polysilicon, and the material of the gate oxide layer 200 includes silicon dioxide; wherein the doping concentration of the n-type lightly doped region 70 is 1×10 11 ～6*10 12 cm 2 The doping concentration of the p-type doped region 80 is 1 x 10 11 ～6*10 12 cm 2 。
Referring to fig. 4, a method for fabricating a p-type polysilicon gate LDMOS device with high mobility mainly includes the following steps:
providing a p-type semiconductor substrate 10, manufacturing a gate oxide layer 200 on the surface of the p-type semiconductor substrate 10, manufacturing a p-type doped gate 100 on the gate oxide layer, and etching the morphology of the gate;
forming a p-type heavily doped body region contact region 30, an n-type lightly doped drift region 20 and a p-type channel region 60 in the semiconductor substrate 10 by means of ion implantation and thermal diffusion, wherein the p-type channel region 60 is positioned below the p-type doped gate 100;
processing the p-type heavy doped body region contact region 30 and the n-type light doped drift region 20 by ion implantation to form an n-type heavy doped source region 50 and an n-type heavy doped drain region 40, wherein the n-type heavy doped source region 50 and the n-type heavy doped drain region 40 are respectively matched with a source electrode and a drain electrode;
at the source end, n-type impurities are implanted into the p-type channel region 60 at an inclined angle by using the layout of the source region in an ion implantation manner, so as to form an n-type lightly doped region 70 in a region close to the surface of the p-type semiconductor substrate 10, at least a local region of the p-type channel region 60 is covered by the n-type lightly doped region 70, and the n-type lightly doped region 70 is electrically contacted or electrically combined with the n-type heavily doped source region 50, so that the p-type polysilicon gate LDMOS device structure with high mobility is formed, as shown in fig. 2.
Referring to fig. 5, a method for fabricating a p-type polysilicon gate LDMOS device with high mobility mainly includes the following steps:
providing a p-type semiconductor substrate 10, and forming an n-type lightly doped region 70 in the semiconductor substrate 10 near the surface of the p-type semiconductor substrate 10 by ion implantation;
performing oblique angle p-type implantation on one side close to the n-type heavy doping source region through an ion implantation process to form a p-type doping region 80 in a local region of the n-type light doping region 70, and enabling the p-type doping region 80 to be in electrical contact with or electrically combined with the n-type light doping region 70, wherein at least part of the n-type light doping region 70 is covered by the p-type forming doping region 80;
forming a p-type heavily doped body region contact region 30, an n-type lightly doped drift region 20 and a p-type channel region 60 in the semiconductor substrate 10 by means of ion implantation, wherein the p-type channel region 60 is positioned below the n-type lightly doped region 70;
processing the p-type heavily doped body region contact region 30 and the n-type lightly doped drift region 20 by ion implantation to form an n-type heavily doped source region 50 and an n-type heavily doped drain region 40, wherein the n-type heavily doped source region 50 and the n-type heavily doped drain region 40 are respectively matched with a source electrode and a drain electrode, and the n-type lightly doped region 70 is electrically contacted or electrically combined with the n-type heavily doped source region 50, so that the p-type doped region 80 is electrically contacted or electrically combined with the n-type lightly doped drift region 20;
and forming a gate oxide layer 200 on the surface of the p-type semiconductor substrate 10, forming a p-type doped gate 100 on the gate oxide layer, etching the morphology of the gate, and finally forming the high-mobility p-type polysilicon gate LDMOS device structure as shown in FIG. 3.
Further, the ion implantation concentration of the p-type heavily doped body contact region 30 is 4×10 13 -2*10 14 cm 2 The energy is 25-150KEV, and the ion implantation concentration of the n-type lightly doped drift region 20 is 1 x 10 12 -4*10 12 cm 2 The energy is 50-200 KEV, the temperature of the thermal diffusion treatment of the p-type heavily doped body region contact region 30 and the n-type lightly doped drift region 20 is 800-1000 ℃ and the time is 20-40min; the ion implantation concentration of the n-type heavily doped source region 50 and the n-type heavily doped drain region 40 is 5×10 14 ～5*10 15 cm 2 The energy is 25-100KEV; the ion implantation concentration of the n-type lightly doped region 70 and the p-type doped region 80 is 1×10 11 -6*10 12 cm 2 The energy is 25-150KEV.
The above only shows a main manufacturing process of the p-type polysilicon gate LDMOS device with high mobility, wherein specific manufacturing process parameters and other conditions can be realized by the existing process by a person skilled in the art, and the specific process parameters can be adjusted and determined according to actual situations.
The p-type polysilicon gate LDMOS device structure with high mobility provided by the embodiment of the invention is shown in fig. 2 and 3, and the core of the two device structures is that an n-type lightly doped region is added in a channel region, the doping distribution in the channel region is changed, and as the voltage of a grid electrode of the device is increased, an inversion layer of the channel region can be preferentially arranged below the n-type lightly doped region in the process of slowly conducting the device, and as the voltage of the grid electrode is increased, the inversion layer gradually moves towards the surface of the device or a semiconductor substrate; because the doping concentration of the n-type lightly doped region is low, under the condition of high gate voltage, the inversion layer can be expanded to the surface of the channel region, even if the inversion layer is still distributed in the semiconductor substrate, and under the condition of most gate voltages of normal operation of the device, the inversion layer mainly occurs in the semiconductor substrate and is far away from the surface, thereby reducing the influence of surface defects on electron mobility, reducing hot carrier injection effect and further improving the saturation current of the device; and the n-type lightly doped region in the channel region lowers the threshold voltage; in addition, the embodiment of the invention adopts the P-type polysilicon as the grid electrode, so that the threshold voltage is improved and the compatibility with the existing application environment is realized.
According to the P-type polysilicon gate LDMOS device with high mobility, the n-type lightly doped region is arranged in the P-type doped channel region, so that the doping distribution of the channel region is changed; when the device starts to be conducted, the inversion layer is positioned below the n-type lightly doped region, and gradually thickens and approaches the surface of the channel region along with the lifting of the grid voltage; when the device works, the inversion layer is positioned in the semiconductor substrate and far away from the surface, so that the influence of surface defects on electron mobility is reduced, the influence of hot carrier injection effect on the surface of the semiconductor device and the gate oxide layer is reduced, and the saturation current of the device and the quality factor of hot carrier injection reliability are improved.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (8)
1. The p-type polysilicon gate LDMOS device with high mobility is characterized by comprising a semiconductor substrate and a grid electrode, wherein a body region contact region and a drift region are distributed in the semiconductor substrate, an active region and a drain region are respectively formed in the body region contact region and the drift region, the source region and the drain region are respectively matched with a source electrode and a drain electrode, a channel region is also distributed in the semiconductor substrate, the channel region is positioned below the grid electrode, a first doping region is also formed in a region, which is close to the surface of the semiconductor substrate, in the channel region, and the first doping region is also electrically contacted with or combined with the source region, wherein the semiconductor substrate, the grid electrode, the body region contact region and the channel region are of a first doping type, and the source region, the drain region, the drift region and the first doping region are of a second doping type;
when the gate voltage exceeds the threshold voltage and the channel region is in inversion form to form an electron layer, an inversion layer close to the source region will first occur below the first doped region;
and a second doped region is further formed in the channel region or in the first doped region, which is close to the surface of the semiconductor substrate, wherein the second doped region is of a first doped type, and is also in electrical contact or electrical combination with the first doped region and the drift region, and at least a local region of the first doped region is covered by the second doped region.
2. A high mobility p-type polysilicon gate LDMOS device as recited in claim 1, wherein: the doping concentration of the first doping region and the second doping region is 1 x 10 11 ~6*10 12 cm 2 。
3. A high mobility p-type polysilicon gate LDMOS device as recited in claim 1, wherein: an oxide layer is further formed on the surface of the semiconductor substrate, and the grid electrode is arranged above the oxide layer.
4. The high mobility p-type polysilicon gate LDMOS device of claim 1 comprising a p-type semiconductor substrate and a p-type doped gate, wherein a p-type heavily doped body contact region and an n-type lightly doped drift region are distributed in the p-type semiconductor substrate, an n-type heavily doped source region and an n-type heavily doped drain region are formed in the p-type heavily doped body contact region and the n-type lightly doped drift region respectively, the n-type heavily doped source region and the n-type heavily doped drain region are respectively matched with a source electrode and a drain electrode, a p-type channel region is also distributed in the p-type semiconductor substrate, the p-type channel region is positioned below the p-type doped gate, an n-type lightly doped region is also formed in the p-type channel region near the surface of the p-type semiconductor substrate, and the n-type lightly doped region is also electrically contacted or electrically combined with the n-type heavily doped source region; when the p-doped gate voltage exceeds a threshold voltage, an inversion layer near the n-type heavily doped source region will first occur below the n-type lightly doped region when the p-type channel region is inversion-formed into an electron layer.
5. A method of fabricating a high mobility p-type polysilicon gate LDMOS device as recited in any of claims 1-4, comprising:
providing a semiconductor substrate, and manufacturing a grid electrode on the semiconductor substrate;
a body region contact region, a drift region and a channel region are formed in the semiconductor substrate, a source region and a drain region are formed in the body region contact region and the drift region respectively, the source region and the drain region are matched with a source electrode and a drain electrode respectively, and the channel region is positioned below the grid electrode;
forming a first doped region in the channel region, which is close to the surface of the semiconductor substrate, at least a partial region of the channel region is covered by the first doped region, and the first doped region is electrically contacted or combined with the source region;
forming a second doped region in the channel region near the surface of the semiconductor substrate or in the region of the first doped region near the surface of the semiconductor substrate, wherein at least a partial region of the first doped region is covered by the second doped region, and the second doped region is electrically contacted or electrically combined with the first doped region and the drift region;
the body region contact region and the drift region are formed by local processing of a semiconductor substrate in an ion implantation and thermal diffusion mode, the source region is formed by local processing of the body region contact region in an ion implantation mode, the drain region is formed by local processing of the drift region in an ion implantation mode, the first doped region is formed by local processing of the channel region in an ion implantation mode, and the second doped region is formed by local processing of the channel region or the first doped region in an ion implantation mode.
6. The manufacturing method according to claim 5, characterized by comprising the following steps: and manufacturing an oxide layer on the surface of the semiconductor substrate, and then manufacturing a grid electrode on the oxide layer.
7. The method of manufacturing according to claim 6, wherein: the material of the grid electrode comprises polysilicon, and the material of the oxide layer comprises silicon dioxide.
8. The method of manufacturing according to claim 6, wherein: the thickness of the oxide layer is 0.01-0.06nm.
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| PCT/CN2020/111569 WO2022016659A1 (en) | 2020-07-21 | 2020-08-27 | High-mobility p-type polysilicon gate ldmos device and manufacturing method therefor |
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| CN1866541A (en) * | 2005-05-12 | 2006-11-22 | 英飞凌科技股份公司 | Field effect transistor and method for manufacturing same |
| CN109830538A (en) * | 2019-01-22 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | LDMOS device and its manufacturing method |
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| JP2001060686A (en) * | 1999-08-20 | 2001-03-06 | Ricoh Co Ltd | Ldmos type semiconductor device and manufacture thereof |
| JP4211884B2 (en) * | 1999-08-30 | 2009-01-21 | 株式会社リコー | Manufacturing method of LDMOS type semiconductor device |
| US7855414B2 (en) * | 2006-07-28 | 2010-12-21 | Broadcom Corporation | Semiconductor device with increased breakdown voltage |
| JP2008182106A (en) * | 2007-01-25 | 2008-08-07 | Denso Corp | Semiconductor device |
| CN111354792B (en) * | 2018-12-20 | 2023-09-12 | 中芯国际集成电路制造(上海)有限公司 | LDMOS device and forming method thereof, and forming method of semiconductor device |
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| CN1866541A (en) * | 2005-05-12 | 2006-11-22 | 英飞凌科技股份公司 | Field effect transistor and method for manufacturing same |
| CN109830538A (en) * | 2019-01-22 | 2019-05-31 | 上海华虹宏力半导体制造有限公司 | LDMOS device and its manufacturing method |
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