JP2008078397A - Method for manufacturing insulated-gate semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce on-resistance, wherein a high-concentration n type impurity region (proton layer) suppresses the advance of diffusion of a channel layer making it possible to form the channel layer shallowly. <P>SOLUTION: In this manufacturing method, the high-concentration n type impurity region is prepared under the channel layer. As the n type impurity, proton is employed. The control of injection depth is easy for proton. Since the n type impurity layer obstructs the advance of diffusion of the channel layer, the depth of the channel layer can be controlled correctly by forming the n type impurity layer in the position where the desired depth of the channel layer is obtained. Thereby, since the channel layer and a trench can be formed so as to be required and sufficient depth, low capacitance, low on-resistance can be attained. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a method of manufacturing an insulated gate semiconductor device, and more particularly, to a method of manufacturing an insulated gate semiconductor device that realizes low capacitance and low on-resistance in an insulated gate semiconductor device having a trench structure.

  FIG. 11 is a cross-sectional view of a conventional semiconductor device, showing an n-channel type MOSFET having a trench structure as an example.

  A drain region is provided by, for example, laminating an n− type epitaxial layer 22 on an n + type silicon semiconductor substrate 21, and a p type channel layer 24 is provided on the surface thereof.

  The trench 27 penetrates the channel layer 24 and reaches the drain region. The inner wall of the trench 27 is coated with a gate oxide film 31 and a gate electrode 33 made of polysilicon filled in the trench 27 is provided.

  An n + type source region 35 is provided on the surface of the channel layer 24 adjacent to the trench 27, and a p + type body region 34 is disposed on the surface of the channel layer 24 between the source regions 35 of two adjacent cells. Further, when applied to the gate electrode 33, a channel (not shown) is formed from the source region 35 along the trench 27. The gate electrode 33 is covered with an interlayer insulating film 36. A barrier metal layer (not shown) is in contact with the source region 35 and the body region 34 exposed in the contact hole CH between the interlayer insulating films 36, and a source electrode 38 made of aluminum alloy or the like is provided.

  A conventional method for manufacturing a semiconductor device will be described with reference to FIG.

  A drain region is formed by stacking an n− type epitaxial layer 22 on an n + type silicon semiconductor substrate 21. A p-type channel layer 24 is formed on the surface, and a trench 27 that penetrates the channel layer 24 and reaches the drain region 22 is formed (FIG. 12A).

  A gate oxide film 31 is formed on the inner wall of the trench 27, and a gate electrode 33 embedded in the trench 27 with polysilicon is formed (FIG. 12B).

  An n + type impurity region is formed on the surface of the channel layer 24 around the trench 27 by ion implantation, and a p + type impurity region is formed on the surface of the channel layer 24 between adjacent n + type impurity regions. An insulating film is formed on the entire surface to form an n + -type source region 35 and a p + -type body region 34, a contact hole CH is formed in the insulating film, and an interlayer insulating film 36 covering the gate electrode 33 is formed (FIG. 12 (C)).

Thereafter, a metal layer to be a source electrode is formed on the entire surface, and a final structure shown in FIG. 11 is obtained (for example, see Patent Document 1).
JP 2002-343805 A

  A conventional MOSFET will be described with reference to FIGS. FIG. 13A is an enlarged cross-sectional view of a MOSFET having a conventional structure.

  The channel layer 24 is a region formed by ion implantation and diffusion, and the impurity profile is not uniform along the depth direction (substrate vertical direction), and the impurity concentration is greatly reduced particularly near the bottom.

  The channel layer 24 is required to have a predetermined impurity concentration in consideration of withstand voltage and suppression of leakage current, and a predetermined depth in consideration of on-resistance, capacitance, and the like. However, as described above, the impurity concentration is greatly reduced near the bottom of the channel layer 24, and a region that does not substantially affect the substantial characteristics is generated (hereinafter, this region is referred to as a tail portion 24t). That is, the channel layer 24 is formed sufficiently deeper than the effective channel portion 24 s in consideration of the formation depth of the tail portion 24 t, where the effective channel portion 24 s is a region having a depth necessary for the channel layer 24.

  On the other hand, the gate electrode 33 is buried in the trench 27 and a channel is formed in the channel layer 24 along the trench 27, so that the trench 27 needs to be provided deeper than the channel layer 24. However, if the trench 27 is deeper than necessary, the gate insulating film (oxide film) 31 provided on the inner wall increases the capacity, and there is a problem that the switching characteristics deteriorate.

  That is, in order to reduce the capacitance, it is desirable that the depth of the trench 27 is as shallow as possible. Therefore, the distance d2 from the lower end of the channel layer 24 (tail portion 24t) to the bottom of the trench 27 is reduced to the limit in consideration of process variations, and is, for example, 0.2 μm to 0.3 μm.

  In the manufacturing process, the trench 27 is formed by anisotropic etching after the channel layer 24 is formed as shown in FIG. After the trench 27 is formed, a gate oxide film 31 is formed on the inner wall by thermal oxidation (FIG. 12B).

  However, the channel layer 24, which is an impurity diffusion region, is diffused to a predetermined depth or more under the influence of this thermal oxidation. That is, if the distance d2 between the lower end of the channel layer 24 (tail portion 24t) and the bottom of the trench 27 is very small as described above, the channel layer 24 becomes deeper than the bottom of the trench 27 as shown in FIG.

  In general, the gate oxide film 31 is formed by high-temperature heat treatment. However, when the gate oxide film 31 is formed thick (for example, about 600 to 1500 mm) in order to reduce the capacity, the heat treatment time is long. It will be time. Here, the film thickness of the gate oxide film 31 is described as being about 700 to 1000 mm, for example. In that case, the temperature of thermal oxidation is about 1100 ° C. and the time is about 120 minutes (700 mm) to 180 minutes (1000 mm). That is, if the heat treatment is performed at such a high temperature for a long time after the channel layer 24 is formed, the diffusion of the channel layer 24, which is an impurity diffusion region, proceeds from a predetermined depth.

  Furthermore, the specific resistance ρ of the n − type epitaxial layer 22 may be increased in order to improve the drain-source breakdown voltage. In this case, since the impurity concentration of the n − type epitaxial layer 22 is lowered, the impurities of the channel layer 24 are likely to diffuse.

  In other words, in the MOSFET in which the capacitance is reduced and the drain-source breakdown voltage is improved, the depth of the trench 27 is further increased in consideration of the influence of diffusion due to thermal oxidation of the gate oxide film 31 (and subsequent manufacturing steps). There is a limit to reducing the capacity of the apparatus.

  Further, when the shape of the channel layer is as shown in FIG. 14, there is a problem that the area (namely, the current path area) a2 of the n − type semiconductor layer in contact with the bottom of the trench 24 becomes narrow and the resistance increases.

  The present invention has been made in view of such problems. First, a step of laminating a one-conductivity-type semiconductor layer on a one-conductivity-type semiconductor substrate, and a high-concentration one-conductivity-type impurity at a predetermined depth from the surface of the semiconductor layer. Forming a layer, forming a reverse conductivity channel layer on the surface of the semiconductor layer on the one conductivity type impurity layer, forming a trench penetrating the one conductivity type impurity layer, at least the above A step of forming an insulating film on the inner wall of the trench, a step of forming a gate electrode in the trench, and a step of forming a source region of one conductivity type on the surface of the semiconductor layer adjacent to the trench. It is a solution.

  According to the present invention, first, a high-concentration n-type impurity region (proton layer) forms a channel layer shallow (to a necessary and sufficient depth) in order to suppress the progress of diffusion of the channel layer. Can do. As a result, the channel length can be shortened as compared with the conventional case where the channel layer is formed deeper than necessary in consideration of excessive diffusion of the channel layer, and the on-resistance can be reduced.

  Second, as the channel layer can be made shallower than before, the trench depth can be made shallower (necessary and sufficient depth). That is, since the gate electrode depth (gate length) can be shortened, the area of the MOS structure composed of the gate electrode and the semiconductor can be reduced, for example, the gate-source capacitance Cgs can be reduced. That is, the capacitance of the MOSFET can be reduced without changing design parameters such as the channel layer. Furthermore, the input capacitance Ciss approximately represented by the gate-source capacitance Cgs + the gate-drain capacitance Cgd can be reduced, and the switching characteristics (speed) can be improved.

  Third, even when the impurity concentration of the n − type semiconductor layer is low and the gate oxide film is formed thick by long-time heat treatment, the channel layer can be prevented from diffusing more than necessary. Therefore, in the semiconductor device that realizes an improvement in drain-source breakdown voltage and a reduction in capacitance, it is possible to accurately control the diffusion depth of the channel layer.

  Fourth, excessive diffusion of the channel layer can be suppressed even after the heat treatment step after the channel layer is formed. When the channel layer is excessively diffused, the channel layer becomes deeper than the trench, and there is a problem that the area a2 of the n − type semiconductor layer in contact with the bottom of the trench is narrowed and the resistance is increased. However, according to the present embodiment, this can be avoided.

  Conventionally, since the diffusion of the channel layer also proceeds by the heat treatment process after forming the channel layer, it is necessary to consider the influence of the plurality of heat treatment processes after forming the channel layer, and the control of the formation conditions of the channel layer is complicated. there were. However, according to the present embodiment, the channel layer depth can be controlled by the depth of the n-type impurity layer without considering the influence of the subsequent heat treatment process. Accordingly, it becomes easy to control the channel layer forming conditions.

  An embodiment of the present invention will be described with reference to FIGS. 1 to 10 by taking an n-channel type MOSFET having a trench structure as an example.

  FIG. 1 is a cross-sectional view showing the structure of a MOSFET.

  The MOSFET includes a semiconductor substrate 1, a semiconductor layer 2, a trench 7, a channel layer 4, a gate electrode 13, a source region 15, and a one conductivity type impurity layer 3.

  A drain region D is provided by a substrate 10 in which an n− type semiconductor layer 2 is stacked on an n + type silicon semiconductor substrate 1. The n − type semiconductor layer 2 is an epitaxial layer formed on the n + type silicon semiconductor substrate 1 by epitaxial growth, for example. A channel layer 4 is provided on the surface of the n − type semiconductor layer 2.

The channel layer 4 is an impurity region provided by ion implantation and diffusion of p-type impurities, and has a predetermined depth in consideration of an impurity dose (for example, about 2E13 cm ⁻² ) for obtaining a predetermined breakdown voltage, on-resistance, capacitance, and the like. (For example, about 2 μm).

A high concentration (n ++) n-type impurity layer 3 is provided below the channel layer 4. The n-type impurity layer 3 is provided by, for example, proton (H +) irradiation (dose amount: about 1E11 cm ^{−2 to} 1E13 cm ⁻² ), and the impurity concentration is sufficiently higher than that of the channel layer 4 and the n − type semiconductor layer 2. high. The n-type impurity layer 3 is disposed at least over the entire region where the channel layer 4 is provided. The n-type impurity layer 3 of this embodiment prevents excessive diffusion of the channel layer 4. That is, the channel layer 4 does not diffuse deeper than the n-type impurity layer 3.

  As will be described in detail later, the n-type impurity layer 3 is gradually diffused into the n − -type semiconductor layer 2 under the influence of the heat treatment after the n-type impurity layer 3 is formed. That is, in the final structure shown in FIG. 1, the high-concentration n-type impurity layer 3 does not actually remain. However, here, for convenience of explanation, the position (and impurity concentration) immediately after the formation of the n-type impurity layer 3 is shown, and the channel layer 4 shows that the diffusion is controlled by the depth immediately after the formation of the n-type impurity layer 3. .

  The trench 7 is provided at a depth penetrating the channel layer 4 and the n-type impurity layer 3. A high concentration n-type (n +) source region 15 is provided on the surface of the channel layer 4 adjacent to the trench 7, and a high concentration p-type (p +) is provided on the surface of the channel layer 4 between two adjacent source regions 15. Body region 14 is arranged. Thus, a channel (not shown) is formed from the source region 15 along the trench 7 when applied to the gate electrode 13. The gate electrode 13 is covered with an interlayer insulating film 16, and a space between the interlayer insulating films 16 becomes a contact hole CH with the source electrode 18. A source electrode 18 formed of an aluminum alloy or the like is electrically connected to the source region 15 and the body region 14 exposed from the contact hole CH through a barrier metal layer (not shown).

  FIG. 2 is an enlarged cross-sectional view showing the MOSFET of this embodiment. As described above, the n-type impurity layer 3 is actually widely diffused in the n − -type semiconductor layer 2 in the final structure shown in FIG. However, for convenience of explanation, the position (and impurity concentration) immediately after the formation of the n-type impurity layer 3 is indicated by a broken line.

  Referring to FIG. 2, n-type impurity layer 3 is provided by proton irradiation. The thickness d11 immediately after the formation of the n-type impurity layer 3 indicated by the broken line is about 0.1 μm to 0.2 μm, and the depth d12 from the surface of the substrate 10 (channel layer 4) is about 1.8 μm.

Then, after the n-type impurity layer 3 is formed, an impurity is implanted into the surface of the n ⁻ -type epitaxial layer 2 and the channel layer 4 is provided by diffusing the impurity by a long-time heat treatment.

  At this time, since the n-type impurity layer 3 is a very high-concentration impurity layer having a reverse conductivity type with respect to the channel layer 4, the diffusion of the channel layer 4 proceeds and reaches the n-type impurity layer 3. However, it is offset by the n-type impurity layer 3 and does not diffuse beyond this. Therefore, the diffusion depth of the channel layer 4 can be kept at the depth d12 immediately after the formation of the n-type impurity layer 3.

  Therefore, the channel layer 4 depth can be accurately controlled by setting the depth d12 of the n-type impurity layer 3 to a depth necessary and sufficient for the channel layer 4.

  In addition, since the generation of the tail portion can be suppressed, the depth can be reduced under the same channel formation conditions as in the prior art. Accordingly, the on-resistance can be reduced.

  Further, since it is not necessary to consider the depth of the tail portion, the trench 7 can be formed to a necessary and sufficient depth. Conventionally, it is necessary to form the trench 27 that penetrates to the tail portion 24t that does not substantially affect the operation, and the trench 27 is formed to have a depth greater than that actually required. That is, the channel length Xc ′ is longer than necessary (see FIG. 13).

  However, according to the present embodiment, it is not necessary to consider the conventional tail portion depth (or the tail portion depth can be very shallow), so that the trench 7 can be formed shallow and the channel length Xc is also short. it can.

  Thereby, the area of the MOS structure made of the gate electrode 13 and the semiconductor can be reduced. Therefore, for example, the gate-source capacitance Cgs is reduced, and the input capacitance Ciss approximated by the gate-source capacitance Cgs + the gate-drain capacitance Cgd is reduced, so that the switching characteristics are improved.

  Further, conventionally, the diffusion of the channel layer 24 proceeds, and the diffusion proceeds not only in the depth (vertical) direction of the substrate but also in the horizontal direction (lateral diffusion). Therefore, the n − type semiconductor layer (that is, the current) in contact with the bottom of the trench. There is a problem that the area a2 of the route) is narrowed (see FIG. 14). However, in this embodiment, since the diffusion of the channel layer 4 can be suppressed, it is possible to prevent the area a1 of the n − type semiconductor layer in contact with the bottom of the trench 7 from being narrowed as shown in FIG. Therefore, an increase in resistance due to a reduction in the current path can be suppressed.

  The impurity concentration and depth of the channel layer 4 and the conditions for forming the n-type impurity layer 3 are examples, and these are appropriately selected according to the characteristics required for the MOSFET.

  An example of a method for manufacturing an n-channel MOSFET will be described with reference to FIGS.

  1st process (refer FIG. 3): The process of laminating | stacking a 1 conductivity type semiconductor layer on a 1 conductivity type semiconductor substrate.

First, a substrate 10 in which an n− type semiconductor layer 2 is stacked on an n + type silicon semiconductor substrate 1 is prepared, and a drain region D is formed. The n − type semiconductor layer 2 is an epitaxial layer formed by, for example, epitaxial growth on the n + type silicon semiconductor substrate 1, and the impurity concentration is a low concentration layer of about 2E14 cm ⁻³ , for example.

  Second step (see FIG. 4): a step of forming a high-concentration one-conductivity type impurity layer at a predetermined depth from the surface of the semiconductor layer.

At least the channel layer formation region is irradiated with an n-type impurity (proton: H +). The dose is about 1E11 cm ^{−2 to} 1E13 cm ⁻² . Thereby, the n-type impurity layer 3 is formed from the surface of the substrate 10 to a predetermined depth d12. The depth d12 is a necessary and sufficient depth (about 1.8 μm) for a channel layer formed in a later step. The thickness d11 of the n-type impurity layer 3 is about 0.1 μm to 0.2 μm. Proton is easy to control the injection depth.

  Third step (see FIG. 5): a step of forming a reverse conductivity type channel layer on the surface of the semiconductor layer on the one conductivity type impurity layer.

After forming an oxide film (not shown) on the surface, the oxide film in the channel layer formation region is etched to expose the surface of the substrate 10. Using this oxide film as a mask, boron or the like is implanted over the entire surface with a dose of 1.0E12 to 1.0E13 ions · cm ⁻² and an acceleration energy of about 50 KeV, and then diffused by heat treatment to form the p-type channel layer 4.

  Since the channel layer 4 is a region formed by ion implantation and diffusion, a tail portion having a low impurity concentration and substantially not affecting the operation is formed below the channel layer 4. However, in the present embodiment, the region with the lowest impurity concentration at the bottom end of the channel layer 4 is offset by the n-type impurity layer 3 having a very high concentration compared to the channel layer 4, so that a tail portion is not generated. Or even if formed, it becomes very thin.

  Further, in the channel layer 4, the progress of diffusion is suppressed by the n-type impurity layer 3 and does not diffuse deeper than this. Therefore, the depth of the channel layer 4 can be accurately controlled by providing the n-type impurity layer 3 at an appropriate depth.

  The n-type impurity layer 3 is also slightly diffused as shown by the broken line due to the influence of the heat treatment (oxide film formation and impurity diffusion not shown) in this step. However, the n-type impurity layer 3 can prevent unnecessary diffusion of the channel layer 4 in the heat treatment process after this process.

  That is, the diffusion of the p-type and n-type impurities cancels out at the boundary between the p-type channel layer 4 and the n-type impurity layer 3. On the other hand, the n-type impurity layer 3 expands slightly downward due to the downward diffusion of the n-type impurity.

  Fourth step (see FIG. 6): A step of forming a trench penetrating one conductivity type impurity layer.

  A CVD oxide film (not shown) of NSG (Non-Doped Silicate Glass) is formed on the entire surface, and a mask made of a resist film is applied except for a portion serving as a trench opening. The CVD oxide film is partially removed by dry etching to form a trench opening in which the n − type semiconductor layer 2 is exposed.

  Further, after removing the resist film, the trench 7 is formed by dry etching the silicon semiconductor substrate in the trench opening with a CF-based gas and an HBr-based gas using the CVD oxide film as a mask. The trench 7 is formed to have a depth penetrating the channel layer 4 and the n-type impurity layer 3.

  Fifth step (see FIG. 7): A step of forming an insulating film on at least the inner wall of the trench.

  Dummy oxidation is performed to form a dummy oxide film (not shown) on the inner wall of the trench 7 and the surface of the channel layer 4 to remove etching damage during dry etching. The dummy oxide film formed by this dummy oxidation is removed by an oxide film etchant such as hydrofluoric acid.

  Thereby, a stable gate oxide film can be formed. In addition, the thermal oxidation at a high temperature has an effect of rounding the opening of the trench 7 to avoid electric field concentration at the opening of the trench 7. Thereafter, a gate oxide film 11 is formed. In this embodiment, the gate oxide film 11 is formed thick (600 to 1500 mm) to reduce the gate capacitance. Here, as an example, the film thickness of the gate oxide film 11 is described as 700 to 1000 mm. That is, the entire surface is thermally oxidized at about 1100 ° C. for 120 minutes (in the case of 700 ° C.) to 180 minutes (in the case of 1000 ° C.) to form the gate oxide film 11.

  Conventionally, there has been a problem that the diffusion of the channel layer proceeds more than necessary by this degree of thermal oxidation process. However, in this embodiment, even if high-temperature heat treatment for forming the gate oxide film is performed for a long time, the n-type impurity layer 3 can suppress the diffusion of the channel layer 4 more than necessary.

  As a result of this heat treatment, the n-type impurity layer 3 is diffused deeply into the n − -type semiconductor layer 2 as indicated by the broken line, and therefore, the high-concentration n-type impurity layer 3 immediately after the formation shown in FIG. 4 hardly remains. However, even if the channel layer 4 undergoes the subsequent heat treatment steps including this step, diffusion does not proceed, and the maximum depth up to the depth d12 immediately after the formation of the n-type impurity layer 3 can be achieved.

  That is, the diffusion of the p-type and n-type impurities cancels out at the boundary between the p-type channel layer 4 and the n-type impurity layer 3. On the other hand, the n-type impurity layer 3 spreads downward due to the downward diffusion of the n-type impurity. Further, the function of the n-type impurity (proton: H +) is lost by the heat treatment step of this step.

  Sixth step (see FIG. 8): a step of forming a gate electrode in the trench.

  A non-doped polysilicon layer is deposited on the entire surface, and, for example, phosphorus (P) is implanted and diffused at a high concentration to increase the conductivity. The polysilicon layer deposited on the entire surface is dry etched without a mask to form the gate electrode 13 embedded in the trench 7. The gate electrode 13 may be embedded in the trench 7 by depositing polysilicon doped with impurities over the entire surface and then etching back.

  Seventh step (see FIG. 9): A step of forming a source region of one conductivity type on the surface of the semiconductor layer adjacent to the trench.

A p-type impurity such as boron (B) is selectively ion-implanted into the formation region of the body region with a resist film mask at an implantation energy of 50 KeV and a dose of about 10 ¹⁵ ions · cm ⁻² to form a p + -type impurity region 14 ′. Then, the resist film is removed (FIG. 9A).

Further, the source region formation region and the gate electrode 13 are masked with a new resist film, and an n-type impurity such as arsenic (As) is ion-implanted with an implantation energy of 50 KeV and a dose of about 5E15 ions · cm ^−2. Then, an n + -type impurity region 15 ′ is formed (FIG. 9B).

  Thereafter, as shown in FIG. 9C, an insulating film 16 'such as BPSG (Boron Phosphorus Silicate Glass) serving as an interlayer insulating film is deposited on the entire surface by the CVD method. By this heat treatment during film formation (less than 1000 ° C., about 30 minutes), the p + -type impurity region 14 ′ and the n + -type impurity region 15 ′ are diffused to form the source region 15 on the surface of the channel layer 4 adjacent to the trench 7. . At the same time, the body region 14 located between the source regions 15 is formed.

  In this embodiment, the n + -type impurity region 15 ′ is formed after the formation of the p + -type impurity region 14 ′. However, the p + -type impurity region 14 ′ may be formed after the n + -type impurity region 15 ′ is formed. .

  Eighth step (see FIG. 10): A step of forming a metal wiring layer.

  Using the resist film as a mask, the insulating film 16 ′ is etched to leave the interlayer insulating film 16 on at least the gate electrode 13 and form a contact hole CH in which the source region 15 and the body region 14 are exposed.

  Thereafter, in order to suppress silicon nodules and prevent spikes (interdiffusion between metal and silicon substrate), a barrier metal layer (not shown) made of a titanium-based material is formed.

  Then, for example, an aluminum alloy is sputtered to a thickness of about 5000 mm on the entire surface to form a metal wiring layer. Thereafter, an alloying heat treatment is performed to stabilize the metal and silicon surfaces. This heat treatment is performed in a hydrogen-containing gas at a temperature of 300 to 500 ° C. (for example, about 400 ° C.) for about 30 minutes to remove crystal distortion in the metal film and stabilize the interface. The metal wiring layer is patterned into a predetermined shape such as a source electrode 18 and a gate pad electrode (not shown). Source electrode 18 is electrically connected to source region 15 and body region 14 through contact hole CH. Thereby, the final structure shown in FIG. 1 is obtained.

  Further, although not shown, SiN or the like serving as a passivation film is provided. Thereafter, heat treatment is performed at 300 to 500 ° C. (for example, 400 ° C.) for about 30 minutes to remove damage.

As described above, in the embodiment of the present invention, an n-channel MOSFET has been described as an example. However, the present invention is not limited to this, and an insulated gate type in which a reverse conductivity type semiconductor layer is provided below the one conductivity type semiconductor substrate 1 of the MOSFET. Insulated gate bipolar transistors (IGBTs) and other insulated gate semiconductor elements can be implemented in the same manner and provide similar effects.

It is sectional drawing explaining the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of embodiment of this invention. It is sectional drawing explaining the conventional insulated gate semiconductor device. It is sectional drawing explaining the manufacturing method of the conventional insulated gate semiconductor device. It is sectional drawing explaining the conventional insulated gate semiconductor device. It is sectional drawing explaining the conventional insulated gate semiconductor device.

Explanation of symbols

1 n + type semiconductor substrate
2 n-type semiconductor layer
3 n-type impurity layer
4 channel layer
7 Trench
10 Substrate
11 Gate oxide film
13 Gate electrode
14 Body region
15 Source region
16 Interlayer insulation film
18 Source electrode
21 n + semiconductor substrate
22 n-type epitaxial layer (drain region)
24 channel layer
24s effective channel area
24t tail
27 Trench
31 Gate oxide film
33 Gate electrode
34 Body area
35 Source area
36 Interlayer insulation film
38 Source electrode

Claims (8)

Laminating one conductivity type semiconductor layer on one conductivity type semiconductor substrate;
Forming a high-concentration one-conductivity type impurity layer at a predetermined depth from the surface of the semiconductor layer;
Forming a reverse conductivity type channel layer on the surface of the semiconductor layer on the one conductivity type impurity layer;
Forming a trench penetrating the one conductivity type impurity layer;
Forming an insulating film on at least the inner wall of the trench;
Forming a gate electrode in the trench;
Forming a source region of one conductivity type on the surface of the semiconductor layer adjacent to the trench;
A method of manufacturing an insulated gate semiconductor device, comprising:   2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein the one conductivity type impurity layer is formed on the entire lower surface of the channel layer.   2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein the insulating film has a thickness of 600 to 1500 mm.   The method for manufacturing an insulated gate semiconductor device according to claim 1, wherein the channel layer is formed by ion implantation and diffusion.   2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein the one conductivity type impurity layer is formed by proton irradiation.   2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein an impurity concentration of the one conductivity type impurity layer is higher than that of the channel layer and the semiconductor layer.   2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein diffusion of the channel layer is controlled at a depth immediately after the formation of the one-conductivity type impurity layer.   2. The method of manufacturing an insulated gate semiconductor device according to claim 1, wherein the one conductivity type impurity layer is diffused into the semiconductor layer by a subsequent heat treatment.