JP2007087985A - Insulated-gate semiconductor device and method of manufacturing same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To avoid an increase of resistance (drain resistance) of a semiconductor layer, and to reduce capacity Cgd between a gate and a drain without arranging a low concentration impurity region near an interface between a channel layer serving as a current route and the semiconductor layer, by arranging the low concentration impurity region in the semiconductor layer where a base of a trench is positioned. <P>SOLUTION: In a semiconductor device; p-type impurity is selectively ion-implanted only in the base of the trench, and the low concentration impurity region 12 is formed in an n-type semiconductor layer (drain region) 2 where the base of the trench is positioned. Impurity concentration of the low concentration impurity region 12 is made lower than the n-type semiconductor layer. Thus, capacity Cgd between the gate and the drain can be reduced. Consequently, feedback capacity Crss can be reduced without reducing impurity concentration of the drain region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an insulated gate semiconductor device and a method for manufacturing the same, and more particularly to an insulated gate semiconductor device having a trench structure that reduces a gate-drain capacitance and a method for manufacturing the same.

  FIG. 14 is a sectional view showing an insulated gate semiconductor device having a conventional trench structure. The figure shows an n-channel MOSFET as an example.

A channel layer 24 is provided on the surface of the drain region 22 in which a semiconductor layer is stacked on the semiconductor substrate 21, and a trench 27 penetrating the channel layer 24 is formed. The inner wall of the trench 27 is covered with a gate insulating film 31 and a gate electrode 33 is embedded. A source region 35 and a body region 34 are provided on the surface of the channel layer 24, and a source electrode 38 is formed (see, for example, Patent Document 1).
Japanese Patent Laid-Open No. 11-67787

  In an insulated gate semiconductor device having a trench structure typified by a MOSFET, the insulating film on the inner wall of the trench is formed very thin as the performance of the device increases. On the other hand, for the MOSFET, the input capacitance Ciss, the output capacitance Coss, and the feedback capacitance Crss are important items, and these reductions are indispensable for improving device characteristics. In particular, since the gate-drain capacitance Cgd contributes to each of the input capacitance Ciss, the output capacitance Coss, and the feedback capacitance Crss, it is desired to reduce the gate-drain capacitance.

  In the case of a MOSFET having a trench structure, the gate-drain capacitance Cgd 'is the capacitance at the bottom of the trench (FIG. 14). The specific resistance of the semiconductor layer (drain region) 22 where the bottom of the trench is located affects the gate-drain capacitance Cgd '.

  That is, as an example, the gate-drain capacitance Cgd ′ can be reduced by increasing the specific resistance of the semiconductor layer 22 (making the impurity concentration of the semiconductor layer 22 low). However, increasing the specific resistance of the semiconductor layer 22 that is the drain region is accompanied by an increase in drain resistance. The semiconductor layer 22 is thick, and the increase in drain resistance greatly affects the increase in on-resistance of the device as compared with other factors. Further, since the fluctuation of the specific resistance of the semiconductor layer 22 affects the withstand voltage and the like, there is a problem that it is necessary to change design values of other components (each region).

  The present invention has been made in view of such problems. First, a substrate in which a semiconductor layer of one conductivity type serving as a drain region is stacked on a semiconductor substrate of one conductivity type, a channel layer of a reverse conductivity type provided on the surface of the substrate, A trench that penetrates the channel layer and reaches the semiconductor layer; an insulating film provided on the inner wall of the trench; a gate electrode embedded in the trench; and a conductive material provided adjacent to the trench on the substrate surface. This is solved by providing a source region of a type and a low-concentration impurity region of one conductivity type provided in the semiconductor layer where the bottom of the trench is located.

  Second, a substrate in which a semiconductor layer of one conductivity type serving as a drain region is stacked on a semiconductor substrate of one conductivity type is prepared, and a channel layer of reverse conductivity type is formed on the surface of the substrate; Forming a trench reaching the semiconductor layer, forming a one-conductivity type low-concentration impurity region in the semiconductor layer where the bottom of the trench is located, and forming an insulating film on the inner wall of the trench; The method includes the steps of: forming a gate electrode embedded in the trench; and forming a source region of one conductivity type adjacent to the trench on the substrate surface.

  Third, preparing a substrate in which a one-conductivity-type semiconductor layer serving as a drain region is stacked on a one-conductivity-type semiconductor substrate, forming a reverse-conductivity-type channel layer on the substrate surface, and penetrating the channel layer A step of forming a trench reaching the semiconductor layer, a step of ion-implanting a reverse conductivity type impurity in the bottom of the trench, a step of forming an insulating film on the inner wall of the trench, and a diffusion of the reverse conductivity type impurity Forming a one-conductivity type low concentration impurity region in the semiconductor layer where the bottom of the trench is located; forming a gate electrode embedded in the trench; and adjoining the trench on the substrate surface. And a step of forming a source region of one conductivity type.

  According to the present invention, first, since the low concentration impurity region is provided in the semiconductor layer in which the trench bottom is located, the gate-drain capacitance Cgd can be reduced.

  Second, since the low-concentration impurity region is selectively provided only at the bottom of the trench that contributes to the reduction of the gate-drain capacitance Cgd, the semiconductor layer serving as the drain region can be formed under the same conditions as in the prior art. Accordingly, the conventional specific resistance can be maintained as the drain region. Further, the low-concentration impurity region is not disposed near the interface between the channel layer and the semiconductor layer serving as a current path. Therefore, an increase in the resistance (drain resistance) of the semiconductor layer can be avoided, and the gate-drain capacitance Cgd can be reduced.

  Third, the low-concentration impurity region can be formed only by adding an impurity ion implantation step to the trench bottom. Specifically, it is only necessary to add an ion implantation step in the steps from the trench formation to the gate electrode formation. For example, the diffusion can be performed using a heat treatment such as a gate insulating film formation step. Therefore, it is possible to provide a method for manufacturing an insulated gate semiconductor device in which the gate-drain capacitance Cgd is reduced (without changing the design value or the like of each region) using a conventional manufacturing process.

  An embodiment of the present invention will be described in detail with reference to FIGS. 1 to 13 by taking an n-channel MOSFET having a trench structure as an example.

  FIG. 1 is a cross-sectional view showing the structure of the MOSFET of this embodiment.

  The MOSFET according to this embodiment includes a substrate 10, a channel layer 4, a trench 7, an insulating film 11, a gate electrode 13, a source region 15, and a low concentration impurity region 12.

  The substrate 10 is obtained by stacking an n− type semiconductor layer 2 on an n + type silicon semiconductor substrate 1 by epitaxial growth or the like and providing a drain region. A p-type channel layer 4 is provided on the surface of the substrate 10.

  The trench 7 is provided so as to penetrate the channel layer 4 and reach the drain region 2. The inner wall of the trench 7 is covered with a gate insulating film (oxide film) 11 having a thickness of several hundreds of millimeters. The trench 7 is embedded with a gate electrode 13 made of a semiconductor layer doped with impurities.

  An n-type low-concentration impurity region 12 is provided in the n − -type semiconductor layer (drain region) 2 where the bottom of the trench 7 is located. The low concentration impurity region 12 is provided only in the vicinity of the bottom of the trench 7 in contact with the bottom of the trench 7 as shown in the figure. The low concentration impurity region 12 has a lower impurity concentration than the n − type semiconductor layer 2, and has an impurity concentration of about 10% to 50% of the n − type semiconductor layer 2, for example.

Thus, by selectively providing the low concentration impurity region 12 in the n − type semiconductor layer 2 near the bottom of the trench 7, the impurity concentration of the n − type semiconductor layer 2 is lowered at the bottom of the trench 7. As a result, the gate-drain capacitance Cgd can be reduced as compared with the gate-drain capacitance Cgd ′ of the conventional structure (see FIG. 14). In the figure, the low-concentration impurity region 12 and the bottom of the trench 7 are in contact with each other. However, the bottom of the trench 7 and the low-concentration impurity region 12 do not have to be completely in contact with each other. That is, the bottom of the trench 7 and the low-concentration impurity region 12 may be separated from each other as long as a region where the impurity concentration is substantially increased (region where the capacitance is increased) is not generated, and the gate-drain capacitance Cgd Can contribute to reduction.

  Thus, according to the present embodiment, the impurity concentration can be reduced only in the region directly related to the gate-drain capacitance Cgd. As a result, the n − type semiconductor layer 2 can be formed under the same conditions as in the prior art, that is, the same wafer as the conventional product can be used.

  As will be described later, the low-concentration impurity region 12 is formed by ion implantation and diffusion only at the bottom of the trench 7 and is formed in a substantially circular shape at the bottom of the trench 7 as shown in the figure. That is, the impurity concentration in the vicinity of the interface with the channel layer 4 is maintained at the impurity concentration of the n − type semiconductor layer 2.

  Here, in the MOSFET having the trench structure, the current path is the channel region and the drain region 2 formed on the side wall of the trench 7. In the drain region 2, a current path is formed as shown by an arrow in the figure. That is, the current flows in the direction of 45 degrees from the side wall of the trench 7 starting from the boundary between the channel layer 4 and the n − type semiconductor layer 2. That is, the drain region 2 in which the low concentration impurity region 12 is formed is a minute region deviated from a substantial current path. Therefore, more specifically, there is almost no increase in drain resistance due to the provision of the low concentration impurity region 12.

  A source region 15 that is an n + type impurity region is provided on the surface of the substrate 10 adjacent to the trench 7, and a body region 14 that is a p + type impurity region is disposed on the surface of the substrate 10 between two adjacent source regions 15. . Thus, a channel region (not shown) is formed from the source region 15 along the trench 7 when a voltage is applied to the gate electrode 13. The gate electrode 13 is covered with an interlayer insulating film 16, and the space between the interlayer insulating films 16 becomes a contact hole CH with the metal wiring layer 17. A metal wiring layer (source electrode) 17 made of an aluminum alloy or the like is electrically connected to the source region 15 and the body region 14 exposed from the contact hole CH via a barrier metal layer (not shown).

FIG. 2 is a diagram showing the characteristics of the MOSFET of this embodiment. An impurity concentration profile in the side wall shown in FIG. 2 (A) is the trench 7, and FIG. 2 (B) is the drain - a diagram showing the relationship between the feedback capacitance Crss and source voltage V _DS. In each figure, the solid line is the MOSEFT of the present embodiment shown in FIG. 1, and the broken line is the MOSFET having the conventional structure shown in FIG.

As an example, when the impurity is p-type boron (B), the impurity implantation conditions for the low-concentration impurity region 12 are a dose of 2 × 10 ¹² cm ⁻² and an implantation energy of 150 KeV.

As apparent from FIG. 2A, the impurity concentration of the n − type semiconductor layer 2 is reduced only near the bottom of the trench 7 (about 2.5 μm from the surface of the substrate 10). Thus the gate as shown in FIG. 2 (B) - the drain can be reduced drain capacitance Cgd (i.e. feedback capacitance Crss) is - 3V to the case of the power supply, such as practical as the range of, for example portable devices source voltage V _DS It is about 10V. That is, in this embodiment, the feedback capacity Crss can be reduced by about 10% in this range.

FIG. 3 shows the relationship between the impurity dose of the low concentration impurity region 12 and the feedback capacitance Crss. FIG. 3A is a table showing simulation results obtained by measuring the feedback capacitance Crss while changing the impurity dose, and FIG. 3B is a graph of FIG. 3A. The drain-source voltage _VDS was compared for 0V, 5V, and 10V.

  The ratio in FIG. 3A is the ratio of the feedback capacitance Crss at each impurity dose in the low concentration impurity region 12 when the low concentration impurity region 12 is not provided (none) is 100%.

  This shows that there is a correlation between the impurity dose of the low concentration impurity region 12 and the feedback capacitance Crss.

That is, in order to reduce the feedback capacity Crss, the impurity dose may be increased. For example, at 8.0 × 10 ¹² cm ⁻² , the feedback capacity Crss can be reduced by about 40%. However, there is a trade-off between the reduction of Crss and the on-resistance due to the provision of the low concentration impurity region 12. Although the manufacturing method will be described in detail later, the low concentration impurity region 12 is formed by ion implantation of p-type impurities. That is, depending on the formation conditions, the impurity concentration of the channel layer 4 is affected. For example, when the dose amount of the low concentration impurity region 12 is too large, the impurity concentration of the channel layer 4 increases. As a result, the gate threshold voltage V _{GS (th)} becomes higher than the design value, and the on-resistance increases.

Specifically, in the case of FIG. 3, the gate threshold voltage V _{GS (th)} (not shown) begins to gradually increase with the implantation of the impurity, and the impurity dose is reduced from about 5.0 × 10 ¹² cm ^−2. It will increase rapidly. Similarly, when the impurity dose is about 5.0 × 10 ¹² cm ⁻² or more, the low-concentration impurity region 12 is inverted into a p-type region. Inversion of the low-concentration impurity region 12 has no problem as a reduction of the feedback capacitance Crss, but if the inverted p-type impurity concentration is too high, the MOSFET does not operate.

In other words, if priority is given to the reduction of the feedback capacitance Crss, the impurity threshold is set to a range where the gate threshold voltage V _{GS (th)} gradually increases, that is, about 5.0 × 10 ¹² cm ⁻² or less, and accordingly. The impurity concentration of the channel layer 4 may be designed low from the beginning.

However, if the impurity dose amount is 2.0 × 10 ^{12 to} 3.0 × 10 ¹² cm ⁻² , the gate threshold voltage V _{GS (th)} is hardly affected, and the drain-source voltage V _{DS is} not affected. The effect of reducing the feedback capacitance Crss when the voltage is 5 V can be enhanced.

More specifically, when the drain-source voltage V _DS is 5 V and the impurity dose is 2 × 10 ¹² cm ⁻² , the feedback capacitance Crss can be reduced by 11%. Further, under this condition, there is almost no influence on the gate threshold voltage V _{GS (th)} , so the design value of the channel layer 4 may be the same as the conventional value, and the effect is great.

  The impurity concentration of the low concentration impurity region 12 is not limited to the above example, but varies depending on the impurity concentration of the n − type semiconductor layer 2 and the channel layer 4.

  When the low-concentration impurity region 12 is located away from the bottom of the trench 7, the depletion layer spreads up and down when the gate voltage is applied, and the thickness can be increased to reduce the capacitance.

Therefore, the formation conditions of the low concentration impurity region 12 are appropriately selected according to the switching characteristics such as the input capacitance Ciss, the output capacitance Coss, and the feedback capacitance Crss in consideration of the impurity concentrations of the n − type semiconductor layer 2 and the channel layer 4. . In particular, if the low-concentration impurity region 12 does not invert or does not affect the gate threshold voltage V _{GS (th)} of the channel layer 4, a conventional wafer can be adopted, and the design value of the channel layer 4 is changed. Without this, the gate-drain capacitance Cgd can be reduced.

  Next, a method for manufacturing an insulated gate semiconductor device according to the present invention will be described with reference to FIGS.

  4 to 10 show a first embodiment of the manufacturing method of the present invention.

  First step (FIG. 4): A step of preparing a substrate in which a semiconductor layer of one conductivity type serving as a drain region is laminated on a semiconductor substrate of one conductivity type, and forming a channel layer of opposite conductivity type on the substrate surface.

  A substrate 10 in which an n− type semiconductor layer 2 is stacked on an n + type silicon semiconductor substrate 1 is prepared. The n − type semiconductor layer is, for example, an epitaxial layer or the like and serves as a drain region.

A mask made of an oxide film (not shown) is provided, and p-type boron, for example, is ion-implanted on the entire surface with an implantation energy of 50 KeV and a dose of 1 × 10 ^{13 to} 3 × 10 ¹³ cm ⁻² . Then, heat treatment at about 1100 ° C. is performed, and boron is diffused to form the channel layer 4.

  Second step (FIG. 5): a step of forming a trench that penetrates the channel layer and reaches the semiconductor layer.

  A CVD oxide film 5 of NSG (Non-doped Silicate Glass) is formed on the entire surface by CVD. Thereafter, a mask made of a resist film is applied except for the opening of the trench. The CVD oxide film 5 is partially removed by dry etching to form a trench opening 6 in which the channel region 4 is exposed, and the resist is removed (FIG. 5A).

  Thereafter, using the CVD oxide film 5 as a mask, the silicon semiconductor substrate in the trench opening 6 is dry-etched with CF-based gas and HBr-based gas to form a trench 7 that penetrates the channel layer 4 and reaches the drain region 2 (FIG. 5 ( B)).

  Third step (FIG. 6): A step of ion-implanting a reverse conductivity type impurity into the bottom of the trench.

Dummy oxidation is performed to form a dummy oxide film 8 on the inner wall of the trench 7 and the surface of the channel layer 4. Next, a p-type (for example, boron: B) impurity is ion-implanted into the entire surface through the dummy oxide film 8. The implantation conditions are a dose such that the n − type semiconductor layer 2 is not inverted after the heat treatment, for example, a dose of about 2 × 10 ¹² cm ⁻² and an implantation energy of 150 KeV. Here, although the p-type impurity is ion-implanted also into the channel layer 4, it has the same conductivity type, and the gate threshold voltage V _{GS (th)} is hardly affected under the above conditions. There is no.

  Thereafter, the dummy oxide film 8 and the CVD oxide film 5 are removed by etching. Thereby, the etching damage of the dry etching at the time of forming the trench 7 is removed.

  The reverse conductivity type impurities are ion-implanted through the dummy oxide film 8, so that the silicon on the inner wall of the trench 7 is not damaged. Further, since the dummy oxide film 8 is removed as described above, there is no problem even if the dummy oxide film 8 is damaged by ion implantation.

  Fourth step (FIG. 7): a step of forming an insulating film on the inner wall of the trench, and a step of diffusing reverse conductivity type impurities to form a reverse conductivity type low concentration impurity region in the semiconductor layer where the bottom of the trench is located.

  The entire surface is thermally oxidized (1100 ° C., about 5 to 30 minutes) to form a gate insulating film (oxide film) 11 on the inner wall of the trench 7. The gate oxide film 11 is formed in several hundreds of gallons (for example, a thickness of about 300 mm to 700 mm) according to the driving voltage. Then, the impurity ion-implanted into the bottom of the trench 7 is diffused by the heat treatment at this time, and a one-conductivity type low-concentration impurity region 12 is formed in the n − -type semiconductor layer 2 where the bottom of the trench 7 is located. If the impurity and the dose amount are under the above conditions, the low concentration impurity region 12 is not inverted and becomes n (n−−) type.

  The low concentration impurity region 12 is formed in a substantially circular shape at the bottom of the trench 7. Since impurities are ion-implanted only into the bottom of the trench 7, the low concentration impurity region 12 is formed only under the bottom of the trench 7, and the side wall near the bottom of the trench 7 is in contact with the n − type semiconductor layer 2.

  As shown in FIG. 1, the current path in the drain region 2 is formed to extend in the direction of 45 degrees with respect to the sidewall of the trench 7. Since the low-concentration impurity region 12 is formed immediately below the trench 7 deviated from the substantial current path, even if the resistance slightly increases in this region, the substantial current path is not affected.

  Fifth step (FIG. 8): A step of forming a gate electrode embedded in the trench.

  Non-doped polysilicon 13a is deposited on the entire surface and filled in the trench 7 (FIG. 8A). The entire surface is doped with impurities to reduce resistance, and the entire surface is etched back. Thereby, the gate electrode 13 embedded in the trench 7 is formed (FIG. 8B). Alternatively, the gate electrode 13 may be formed by depositing polysilicon 13a doped with impurities and etching back the entire surface.

  Sixth step (FIGS. 9 and 10): a step of forming a source region of one conductivity type adjacent to the trench on the substrate surface.

A resist PR mask (not shown) exposing the formation region of the source region is formed, and an n-type impurity (for example, arsenic (As)) 15a is implanted on the entire surface with an implantation energy of 140 KeV and a dose of 5 × 10 ^{15 to} 6 × 10 ¹⁵ cm. ^-2 for ion implantation.

Subsequently, a resist PR mask (not shown) in which the formation region of the body region is exposed is formed, and a p-type impurity (for example, boron (B)) 14a is implanted at an energy of 40 KeV and a dose of 2 × 10 ^{15 to} 5 × 10 ¹⁵ cm ^{−. 2} is ion-implanted (FIG. 9A).

  Thereafter, a BPSG (Boron Phosphorus Silicate Glass) layer 16a serving as an interlayer insulating film is deposited on the entire surface by about 6000 mm and reflowed at about 900.degree. By this heat treatment, p-type impurities and n-type impurities are diffused. As a result, a source region 15 is formed on the surface of the substrate 10 adjacent to the trench 7, and a body region 14 is formed between the source regions 15 (FIG. 9B). The ion implantation of the source region 15 and the body region 14 is not limited to the above order and may be interchanged.

  Thereafter, as shown in FIG. 10, a resist PR mask (not shown) opened in a predetermined pattern is provided on the BPSG layer 16a for etching, and after removing the resist, reflow at about 900 ° C. is performed to form the interlayer insulating film 16 To do.

  Further, aluminum or the like is deposited on the entire surface by a sputtering apparatus and patterned into a desired shape. A source electrode 17 in contact with the source region 15 and the body region 14 is formed to obtain the final structure shown in FIG. A drain electrode (not shown) is formed on the back surface of the substrate.

  Here, the ion implantation process of the low concentration impurity region 12 is not limited to the above example. Hereinafter, another embodiment of the ion implantation process will be described with reference to FIGS.

  FIG. 11 shows a second embodiment of the manufacturing method of the present invention. In the second embodiment, ion implantation is performed immediately after trench formation.

  As shown in FIG. 11A, after the trench 7 is formed in the second step of the first embodiment, an impurity of a reverse conductivity type is ion-implanted. Thereafter, a dummy oxide film 8 is formed as shown in FIG. The impurities are diffused by the heat treatment at this time, and the low concentration impurity region 12 can be formed in the n − type semiconductor layer 2 where the bottom of the trench 7 is located.

  FIG. 12 shows a third embodiment. In the third embodiment, ions are implanted after the dummy oxide film 8 is removed.

  In the third step of the first embodiment, the dummy oxide film 8 and the CVD oxide film 5 are removed, and then an impurity of a reverse conductivity type is ion-implanted (FIG. 12A). Thereafter, a gate oxide film 11 is formed. The impurities are diffused by the heat treatment at this time, and the low concentration impurity region 12 can be formed in the n − type semiconductor layer 2 where the bottom of the trench 7 is located.

  FIG. 13 shows a fourth embodiment. The fourth embodiment is a case where ions are implanted after the gate oxide film 11 is formed.

  In the fourth step of the first embodiment, after the gate oxide film 11 is formed, ions of reverse conductivity type are ion-implanted through the gate oxide film 11 (FIG. 13A). Thereafter, the gate electrode 13 is formed in the fifth to sixth steps of the first embodiment. For example, an impurity of a reverse conductivity type is diffused by heat treatment such as diffusion of impurities into the non-doped polysilicon serving as the gate electrode 13 or reflow of the interlayer insulating film 16, and low concentration impurities are formed in the n − type semiconductor layer 2 where the bottom of the trench 7 is located Region 12 can be formed (FIG. 13B).

  In the present embodiment, an n-channel MOSFET has been described as an example. However, a p-channel type in which the conductivity type is reversed can be similarly implemented. In that case, the low concentration impurity region 12 is formed of an n-type impurity.

Furthermore, not only MOSFET but also insulated gate semiconductor devices such as IGBT can be implemented in the same manner, and the same effect can be obtained.

It is sectional drawing explaining the insulated gate semiconductor device of this invention. It is a characteristic view explaining the insulated gate semiconductor device of this invention. It is a characteristic view explaining the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the manufacturing method of the insulated gate semiconductor device of this invention. It is sectional drawing explaining the conventional insulated gate semiconductor device.

Explanation of symbols

1 n + type semiconductor substrate
2 n-type semiconductor layer (drain region)
4 channel layer
7 Trench
8 Dummy oxide film
11 Gate insulation film
12 Low concentration impurity region
13a polysilicon
13 Gate electrode
14 Body region
15 Source region
16 Interlayer insulation film
17 Metal wiring layer
21 n + type semiconductor substrate
22 n-type semiconductor layer (drain region)
24 channel layer
27 Trench
31 Gate oxide film
33 Gate electrode
34 Body area
35 Source area

Claims (7)

A substrate in which a semiconductor layer of one conductivity type serving as a drain region is stacked on a semiconductor substrate of one conductivity type;
A reverse conductivity type channel layer provided on the substrate surface;
A trench that penetrates the channel layer and reaches the semiconductor layer;
An insulating film provided on the inner wall of the trench;
A gate electrode embedded in the trench;
A source region of one conductivity type provided adjacent to the trench on the substrate surface;
An insulated gate semiconductor device comprising: a one-conductivity type low-concentration impurity region provided in the semiconductor layer in which the trench bottom is located.   2. The insulated gate semiconductor device according to claim 1, wherein the low concentration impurity region is provided in contact with a bottom portion of the trench.   2. The insulated gate semiconductor device according to claim 1, wherein the low concentration impurity region has an impurity concentration lower than that of the semiconductor layer. Preparing a substrate in which a semiconductor layer of one conductivity type serving as a drain region is stacked on a semiconductor substrate of one conductivity type, and forming a channel layer of reverse conductivity type on the substrate surface;
Forming a trench that penetrates the channel layer and reaches the semiconductor layer;
Forming a low-concentration impurity region of one conductivity type in the semiconductor layer where the bottom of the trench is located;
Forming an insulating film on the inner wall of the trench;
Forming a gate electrode embedded in the trench;
Forming a source region of one conductivity type adjacent to the trench on the surface of the substrate, and a method for manufacturing an insulated gate semiconductor device. Preparing a substrate in which a semiconductor layer of one conductivity type serving as a drain region is stacked on a semiconductor substrate of one conductivity type, and forming a channel layer of reverse conductivity type on the substrate surface;
Forming a trench that penetrates the channel layer and reaches the semiconductor layer;
Ion-implanting a reverse conductivity type impurity into the bottom of the trench;
Forming an insulating film on the inner wall of the trench;
Diffusing the reverse conductivity type impurity to form a one conductivity type low concentration impurity region in the semiconductor layer where the bottom of the trench is located;
Forming a gate electrode embedded in the trench;
Forming a source region of one conductivity type adjacent to the trench on the surface of the substrate, and a method for manufacturing an insulated gate semiconductor device.   7. The method of manufacturing an insulated gate semiconductor device according to claim 5, wherein the impurity in the low concentration impurity region is ion-implanted into a bottom portion of the trench before the gate electrode is formed. 7. The method of manufacturing an insulated gate semiconductor device according to claim 5, wherein the impurity in the low concentration impurity region is ion-implanted into a bottom portion of the trench after dummy oxidation of the trench.

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