JP2021120990A - diode - Google Patents

Abstract

To provide a technique that can reduce the on resistance without enlarging the size of a diode.SOLUTION: A diode includes a semiconductor layer, a front surface electrode disposed on a front surface of the semiconductor layer, a trench extending from the front surface of the semiconductor layer to a back surface, an insulating film covering an inner wall surface of the trench, a conductive part filling the trench in contact with the front surface electrode, and a back surface electrode disposed on the back surface of the semiconductor layer. The insulating film covers a part of the back surface side of the semiconductor layer on the inner wall surface of the trench. The conductive part may be in contact with the semiconductor layer on the front surface side of the semiconductor layer in the trench.SELECTED DRAWING: Figure 1

Description

The present specification relates to diodes. The present specification specifically discloses a technique relating to a diode having a trench on the surface of a semiconductor layer.

Patent Document 1 discloses a trench MOS type Schottky barrier diode. The Schottky barrier diode includes a semiconductor substrate, an epitaxial layer, a Schottky metal, and an electrode metal. The epitaxial layer is arranged on the surface of the semiconductor substrate. A plurality of inner trenches are formed on the surface of the epitaxial layer. The Schottky metal is formed so as to face the epitaxial layer including the inner wall surface of the inner trench.

Japanese Unexamined Patent Publication No. 2015-153769

In the Schottky barrier diode, the on-resistance increases as the contact area between the Schottky metal and the epitaxial layer increases. Therefore, in the above technique, it is necessary to increase the size of the diode in order to reduce the on-resistance, that is, to increase the contact area between the Schottky metal and the epitaxial layer.

The present specification provides a technique capable of reducing the on-resistance without increasing the size of the diode.

The techniques disclosed herein relate to diodes. The semiconductor is filled with a semiconductor layer, a surface electrode arranged on the surface of the semiconductor layer, a trench extending from the front surface of the semiconductor layer toward the back surface, an insulating film covering the inner wall surface of the trench, and the trench. In addition, the insulating film includes a conductive portion that comes into contact with the front surface electrode and a back surface electrode that is arranged on the back surface of the semiconductor layer, and the insulating film is formed on the back surface side of the semiconductor layer among the inner wall surfaces of the trench. A part of the conductive portion may be covered and the conductive portion may be in contact with the semiconductor layer on the surface side of the semiconductor layer of the trench.

According to this configuration, the semiconductor layer can come into contact with not only the surface electrodes arranged on the surface of the semiconductor layer but also the conductive portions located on the surface side of the semiconductor layer among the conductive portions filled in the trench. .. Thereby, the contact area between the semiconductor layer and the surface electrode and the conductive portion can be increased as compared with the contact area when the semiconductor layer is in contact with only the surface electrode. As a result, the on-resistance can be reduced without increasing the size of the diode.

The surface electrode may be a metal electrode, the conductive portion may be a metal portion, and the surface electrode and the conductive portion may be in Schottky contact with the semiconductor layer. According to this configuration, the area of Schottky contact can be increased in the Schottky barrier diode. Thereby, the on-resistance can be reduced.

The inner wall surface of the trench includes a bottom surface located on the back surface side of the semiconductor layer and a side surface extending from the bottom surface to the surface of the semiconductor layer, and the bottom surface and the side surface are connected by a curved surface. You may be. According to this configuration, on the back surface of the trench where the electric field concentration occurs, by connecting the bottom surface and the side surface of the trench with a curved surface, it is possible to suppress the concentration of the electric field at the boundary between the bottom surface and the side surface of the trench. can.

The inner wall surface of the trench may be inclined so as to widen the width of the trench at the end portion of the semiconductor layer on the surface side. According to this configuration, the contact area between the semiconductor layer and the conductive portion can be made larger.

The semiconductor layer located on the back surface side of the back surface side end of the trench may have a low concentration region having a lower impurity concentration than other parts of the semiconductor layer. According to this configuration, the depletion layer can be easily spread by lowering the impurity concentration in the vicinity of the back surface side end of the trench where the electric field concentration occurs. Thereby, the withstand voltage when the reverse voltage is applied can be improved.

Details of the techniques disclosed herein and further improvements will be described in the "Modes for Carrying Out the Invention" below.

It is sectional drawing of the main part of the diode of 1st Example. It is a figure explaining the manufacturing method of the diode of 1st Example. It is a figure explaining the manufacturing method of the diode following FIG. It is a figure explaining the manufacturing method of the diode following FIG. It is a figure explaining the manufacturing method of the diode following FIG. It is a figure explaining the manufacturing method of the diode following FIG. It is sectional drawing of the main part of the diode of 2nd Example. It is a simulation result which shows the voltage-current relationship of the diode of the 2nd Example. This is a simulation result showing the relationship between the contact depth of the diode of the second embodiment and the current increase ratio. This is a simulation result showing the relationship between the contact depth and the withstand voltage of the diode of the second embodiment. This is a simulation result showing the relationship between the contact depth of the diode of the second embodiment and the withstand voltage / on-resistance.

The diode 100 of the first embodiment will be described with reference to FIG. The diode 100 is a vertical Schottky diode having a trench MOS region, a so-called trench MOS type Schottky barrier diode.

The diode 100 includes a semiconductor layer 12, an anode electrode 30, a cathode electrode 10, insulating films 21 and 31, an insulating layer 22, and a conductive portion 32. The semiconductor layer 12 includes a substrate 14 and an epitaxial layer 16 deposited on the surface of the substrate 14 by epitaxial growth.

The substrate 14 and the epitaxial layer 16 are made of gallium oxide (Ga ₂ O ₃ ) containing n-type impurities. Examples of n-type impurities include silicon (Si). The impurity concentration of the substrate 14 is higher than the impurity concentration of the epitaxial layer 16. The impurity concentration of the substrate 14 is, for example, 5 × 10 ¹⁸ cm ^-3 , and the impurity concentration of the epitaxial layer 16 is, for example, 2 × 10 ¹⁶ cm ^-3 .

A cathode electrode 10 is arranged on the back surface side (lower surface side in FIG. 1) of the substrate 14. The cathode electrode 10 is made of a metal (for example, nickel (Ni) silicide, cobalt (Co) silicide) that makes ohmic contact with the substrate 14.

A plurality of trenches 18 are arranged on the surface of the epitaxial layer 16, that is, the surface 12b of the semiconductor layer 12. The number of trenches 18 is not limited to the number shown in FIG. The plurality of trenches 18 are formed by digging the epitaxial layer 16 from the surface 12b. The plurality of trenches 18 are formed by dry etching. The plurality of trenches 18 have the same shape as each other. The trench 18 includes an inner wall surface (18c, 18d) including a pair of side surfaces 18c and a bottom surface 18d. The trench 18 is dug vertically from the front surface of the semiconductor layer 12 toward the back surface side (from the upper side to the lower side in FIG. 1). The pair of side surfaces 18c extend vertically downward from the surface 12b. In a plan view, the side surfaces 18c of the plurality of trenches 18 are arranged parallel to each other. The distance between the pair of side surfaces 18c is constant.

At the end of the pair of side surfaces 18c on the back surface side of the semiconductor layer 12, a bottom surface 18d connecting the pair of side surfaces 18c is arranged. The bottom surface 18d has a plane extending perpendicular to the pair of side surfaces 18c. The boundary between the bottom surface 18d and each of the pair of side surfaces 18c is connected by a curved surface 18b. In the modified example, the bottom surface 18d may have curved surfaces arranged on the pair of side surfaces 18c. In this case, the boundary between the bottom surface 18d and each of the pair of side surfaces 18c may be connected by a curved surface.

Each of the pair of side surfaces 18c includes an inclined surface 18a that is inclined in a direction in which the distance between the pair of side surfaces 18c is widened at the end portion of the semiconductor layer 12 on the surface side. The inclined surface 18a is formed over the entire length in the longitudinal direction of the trench 18. The inclined surface 18a is inclined at 45 degrees with respect to other parts of the side surface 18c and the surface 12b, for example. In FIG. 1, reference numerals 18a, 18b, 18c, and 18d are attached to only one trench 18, and the reference numerals 18a, 18b, 18c, and 18d of the other trenches 18 are omitted, but a plurality of trenches are omitted. 18 has the same configuration.

On the surface of the epitaxial layer 16, the termination trench 20 is arranged on the termination side of the diode 100 rather than the plurality of trenches 18. The terminal trench 20 circles the outside of the plurality of trenches 18 along the outer circumference of the semiconductor layer 12. The terminal trench 20 is formed by digging the epitaxial layer 16 from the surface of the epitaxial layer 16. The terminal trench 20 is formed by dry etching like the trench 18. The boundary between the side surface and the bottom surface of the end trench 20 is connected by a curved surface as in the trench 18.

A low concentration region 40 having a lower n-type impurity concentration than the surroundings is arranged on the epitaxial layer 16 in contact with the bottom surface (that is, the lower surface of FIG. 1) of each of the plurality of trenches 18 and the terminal trench 20. The low concentration region 40 located below the trench 18 has a width equal to or greater than the width of the trench 18, and the low concentration region 40 located below the termination trench 20 has a width equal to or greater than the width of the termination trench 20. Has a width of. The height of the low concentration region 40 (that is, the vertical length in FIG. 1) is, for example, 0.1 to 0.5 times the distance between two adjacent trenches 18 (that is, the width of the mesa portion 12a). Is. The low concentration region 40 is formed by forming the trenches 18 and 20 in the epitaxial layer 16 and then implanting ions into the epitaxial layer 16 at the bottom of the trenches 18 and 20 to perform an annealing treatment. In the ion implantation, counter ion implantation is performed so as to implant magnesium (Mg) ions into the semiconductor layer 12 of _{gallium oxide (Ga 2} O ₃ ) containing n-type impurities.

An insulating film 31 is arranged on the bottom surface 18d and the side surface 18c of each of the plurality of trenches 18. The insulating film 31 covers the entire surface of the bottom surface 18d. Further, the insulating film 31 covers a part of the back surface side of the semiconductor layer 12 on the side surface 18c. The insulating film 31 does not cover the side surface 18c from the surface of the semiconductor layer 12 to the depth D, but covers the side surface 18c on the back surface side of the semiconductor layer 12 from the depth D.

Similarly, an insulating film 21 is arranged on the bottom surface and the side surface of the terminal trench 20. The insulating film 21 covers the entire bottom surface and side surface of the terminal trench 20. The insulating films 21 and 31 are insulating materials such as _{hafnium oxide (HfO 2).} The insulating films 21 and 31 are formed by, for example, a laminated film of _{silicon dioxide (SiO 2} ) and hafnium oxide (HfO _{2 ) or alumina (Al 2} O) by chemical vapor deposition (that is, CVD (abbreviation of Chemical Vapor Deposition)). _It may be the laminated film of 3).

The terminal trench 20 is filled with an insulating layer 22 via an insulating film 21. The insulating layer 22 is formed by further depositing _{hafnium oxide (HfO 2} ) only in the terminal trench 20 after the insulating films 21 and 31 are deposited. The surface of the insulating layer 22 coincides with the surface of the epitaxial layer 16, that is, the semiconductor layer 12.

The plurality of trenches 18 are filled with the conductive portion 32. The conductive portion 32 includes a polysilicon layer 32b and a metal layer 32a. A polysilicon layer 32b is arranged at the lower end of the trench 18. The polysilicon layer 32b is filled in the trench 18 at a portion surrounded by the insulating film 31. The surface of the polysilicon layer 32b on the surface 12b side coincides with the upper end of the insulating film 31. A metal layer 32a is arranged on the surface 12b side of the polysilicon layer 32b. The metal layer 32a is filled up to the end of the trench 18 on the surface 12b side. The metal layer 32a is in direct contact with the side surface 18c. As a result, the conductive portion 32 is arranged so as to face the epitaxial layer 16, that is, the semiconductor layer 12 with the insulating film 31 sandwiched between the polysilicon layer 32b, and the epitaxial layer 16, that is, the semiconductor directly in the metal layer 32a. It is arranged so as to face the layer 12. The metal layer 32a is in Schottky contact with the semiconductor layer 12 on the side surface of the semiconductor layer 12, that is, the mesa portion 12a of the semiconductor layer 12 sandwiched between the plurality of trenches 18 and the terminal trench 20. In FIG. 1, reference numerals 31, 32, 32a, and 32b are attached to only one trench 18, and reference numerals 32, 32a, and 32b are omitted in the other trenches 18, but the plurality of trenches 18 are designated by reference numerals 32, 32a, and 32b. Similarly, the insulating film 31 is arranged, and the conductive portion 32 composed of the polysilicon layer 32b and the metal layer 32a is filled.

The anode electrode 30 is arranged at the upper end of the conductive portion 32, that is, at the upper end of the plurality of trenches 18. The anode electrode 30 is formed on a flat plate on the surface of the semiconductor layer 12. The anode electrode 30 is in contact with the conductive portion 32 at the upper ends of the plurality of trenches 18. The anode electrode 30 is integrally formed with the conductive portion 32. That is, the anode electrode 30 is formed by continuously depositing a conductive material on the conductive portion 32. The anode electrode 30 is a metal electrode, and is in Schottky contact with the semiconductor layer 12 on the surface of the semiconductor layer 12, that is, the mesa portion 12a of the semiconductor layer 12 sandwiched between the plurality of trenches 18 and the terminal trench 20. There is.

The anode electrode 30 has a field plate structure formed by contacting the surface of the insulating layer 22.

Next, a method for manufacturing the diode 100 will be described with reference to FIGS. 2 to 6. In addition, in FIGS. 2 to 6, only the peripheral structure of the trench 18 is shown. As shown in FIG. 2, the trench 18 is formed by digging the epitaxial layer 16 from the surface of the epitaxial layer 16. Next, ions are implanted into the epitaxial layer 16 at the bottom of the trench 18 and an annealing treatment is performed to form a low concentration region 40. The trench 20 and the low-concentration region 40 at the bottom of the trench 20 are formed in the same manner as the trench 18 and the low-concentration region 40 at the bottom of the trench 18.

Next, as shown in FIG. 3, an insulating material 33 such as _{hafnium oxide (HfO 2) is deposited on the surface of the epitaxial layer 16.} Then, as shown in FIG. 4, the polysilicon 32c is filled in the trench 18 by chemical vapor deposition. Then, as shown in FIG. 5, the surface of the epitaxial layer 16 and the polysilicon 32c in the trench 18, specifically, the polysilicon 32c up to the depth D in the trench 18 are removed by etching (dry or wet). .. At this time, a part of polysilicon 32c is left at the bottom of the trench 18. As a result, the polysilicon layer 32b is formed. The trench 20 is filled with the insulating layer 22 in another step.

Then, as shown in FIG. 6, the insulating material 33 of the information rather than the surface of the epitaxial layer 16 and the polysilicon layer 32b in the trench 18 is removed by etching (dry or wet). Subsequently, the metal layer 32a and the anode electrode 30 are integrally formed. As a result, the diode 100 shown in FIG. 1 is formed.

(Second Example)
The difference between the diode 200 of the present embodiment and the diode 100 of the first embodiment will be described with reference to FIG. 7. In the diode 200, the conductive portion 232 filled in the trench 18 is made of the same metal material as the metal layer 32a. The other configurations of the diode 200 are the same as those of the diode 100.

(Effect of diode 200)
The effect of the diode 200 will be described with reference to FIGS. 8 to 11. 8 to 11 are graphs showing the simulation results using the diode 200. In this simulation, in the diode 200 in which the depth from the surface of the semiconductor layer 12 of the trench 18 is 6 μm, the depth D in which the conductive portion 232 is in direct contact with the semiconductor layer 12 (hereinafter, “contact depth”). "D") is 0 μm (that is, the mode in which the conductive portion 232 is not in direct contact with the semiconductor layer 12, hereinafter referred to as “comparative diode”), and a plurality of diodes 200 between 1 and 6 μm are provided. It is used.

FIG. 8 is a graph showing the voltage-current relationship of the diode 200. In FIG. 8, the vertical axis represents current and the horizontal axis represents voltage. Result 80 represents the simulation result of the diode of the comparative example having the contact depth D of 0 μm, and each of the results 83, 84 and 85 represents the simulation result of the diode 200 having the contact depth of 3 μm, 4 μm and 5 μm, respectively. .. FIG. 9 is a graph showing the rate of increase of the current of the diode 200 when the current flowing through the diode of the comparative example is 1 when a constant voltage is applied to the diode 200. In FIG. 9, the vertical axis represents the current increase rate, and the horizontal axis represents the contact depth D. As is clear from the simulation results of FIGS. 8 and 9, the larger the contact depth D, that is, the larger the contact area between the conductive portion 232 and the semiconductor layer 12, the larger the current value when the voltage is the same. .. That is, the larger the contact area between the conductive portion 232 and the semiconductor layer 12 (that is, the area of Schottky contact), the lower the on-resistance.

FIG. 10 shows a simulation result of the withstand voltage of the diode 200 when a reverse voltage is applied. In FIG. 10, the vertical axis represents the pressure resistance and the horizontal axis represents the contact depth D. As shown in FIG. 10, the diode 200 having a contact depth D of 3 μm has a withstand voltage substantially equal to that of the diode of the comparative example. On the other hand, when the contact depth D is larger than 3 μm, the withstand voltage becomes lower than that of the diode of the comparative example. Further, as the contact depth D increases, the withstand voltage decreases.

FIG. 11 shows the ratio of the withstand voltage to the on-resistance of the diode 200. In FIG. 11, the vertical axis represents the ratio of withstand voltage to the on-resistance, and the horizontal axis represents the contact depth D. As a result, in the diode 200 having a contact depth D of 4 μm or less as compared with the diode of the comparative example, the on-resistance can be reduced while suppressing the decrease in the withstand voltage. The same effect can be obtained with the diode 100.

Further, in the diodes 100 and 200, the inclined surface 18a is arranged at the end portion of the trench 18 on the surface side of the semiconductor layer 12. According to this configuration, the contact area between the semiconductor layer 12 and the conductive portions 32 and 232 can be further increased. Thereby, the on-resistance can be reduced.

In the diodes 100 and 200, by arranging the low concentration region 40 near the lower ends of the plurality of trenches 18, the depletion layer can be easily expanded while the reverse voltage is applied. Thereby, the withstand voltage when the reverse voltage is applied can be improved.

In the diodes 100 and 200, the insulating layer 22 is embedded in the terminal trench 20. As a result, it is not necessary to arrange the insulating layer for arranging the field plate structure on the surface of the semiconductor layer 12. Thereby, the surface of the diode 100 can be flattened. As a result, it is possible to design a device on which the diode 100 is mounted without considering the convex shape of the surface of the diode 100. As a result, the device on which the diode 100 is mounted can be miniaturized.

In the diodes 100 and 200, the bottom surface 18d and the side surface 18c of the trench 18 are connected by a curved surface 18b. According to this configuration, in the bottom surface 18d of the trench 18 where the electric field concentration occurs, the electric field is concentrated at the boundary between the bottom surface 18d and the side surface 18c as compared with the configuration in which the bottom surface 18d and the side surface 18c are connected by the corners. Can be suppressed.

Although specific examples of the present invention have been described in detail above, these are merely examples and do not limit the scope of claims. The techniques described in the claims include various modifications and modifications of the specific examples illustrated above.

(1) The above technique can be applied to wide-gap semiconductors other than gallium oxide, such as silicon carbide (SiC). Further, the diodes 100 and 200 can be applied not only to Schottky diodes but also to PN diodes.

(2) In the above-described embodiment, the low concentration region 40 is also arranged below the terminal trench 20. However, the low concentration region 40 may not be arranged below the terminal trench 20. In this case, the semiconductor layer 12 below the terminal trench 20 may have an impurity concentration equivalent to that of the other semiconductor layers 12.

(3) The conductive portion 32 may be made of a conductive material different from that of the anode electrode 30, such as polysilicon.

The technical elements described herein or in the drawings exhibit their technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques illustrated in the present specification or drawings can achieve a plurality of purposes at the same time, and achieving one of the purposes itself has technical usefulness.

10: Cathode electrode, 12: Semiconductor layer, 12b: Surface, 14: Substrate, 16: epitaxial layer, 18: Trench, 18a: Inclined surface, 18b: Curved surface, 18c: Side surface, 18d: Bottom surface 20: Termination trench, 21 , 31: Insulation film, 22: Insulation layer, 30: Anode electrode, 31: Insulation film, 32, 232: Conductive part, 32a: Metal layer, 32b: Polysilicon layer, 40: Low concentration region, 100, 200: Diode

Claims (5)

With the semiconductor layer
A surface electrode arranged on the surface of the semiconductor layer and
A trench extending from the front surface to the back surface of the semiconductor layer,
An insulating film that covers the inner wall surface of the trench and
A conductive portion that is filled in the trench and is in contact with the surface electrode, and
A diode including a back surface electrode arranged on the back surface of the semiconductor layer.
The insulating film covers a part of the inner wall surface of the trench on the back surface side of the semiconductor layer.
The conductive portion is a diode that is in contact with the semiconductor layer on the surface side of the semiconductor layer of the trench. The surface electrode is a metal electrode and
The conductive portion is a metal portion and
The diode according to claim 1, wherein the surface electrode and the conductive portion are in Schottky contact with the semiconductor layer. The inner wall surface of the trench includes a bottom surface located on the back surface side of the semiconductor layer and a side surface extending from the bottom surface to the front surface of the semiconductor layer.
The diode according to claim 1 or 2, wherein the bottom surface and the side surface are connected by a curved surface. The diode according to any one of claims 1 to 3, wherein the inner wall surface of the trench is inclined so as to widen the width of the trench at the end portion of the semiconductor layer on the surface side. The invention according to any one of claims 1 to 4, wherein the semiconductor layer located on the back surface side of the back surface side end of the trench has a low concentration region having a lower impurity concentration than other portions of the semiconductor layer. Diode.

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