JP2011199306A - Semiconductor device and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device that is easy to manufacture and has lower loss while securing a high breakdown voltage, and to provide a method of manufacturing the semiconductor device.SOLUTION: A Schottky diode 10 as a semiconductor device includes a substrate 11 made of a semiconductor and an n-type layer 12 formed on the substrate 11. The n-type layer 12 has a groove 13 formed to extend from a second surface 12B as a surface on the opposite side from a first surface 12A as a surface on the side of the substrate 11 toward the first surface 12A. An oxide layer 14 as an insulator is arranged at a position where it comes into contact with a bottom wall 13A as a bottom portion of the groove 13, and the groove 13 is filled with a metal film 15 capable of coming into Schottky contact with the n-type layer 12 so as to contact a sidewall 13B of the groove 13. Further, an anode electrode 16 is arranged so as to contact the second surface 12B of the n-type layer 12.

Description

  The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device including a substrate made of a semiconductor and a manufacturing method thereof.

  With the recent improvement in performance of automobiles, home appliances, etc., the power electronics field of semiconductor devices used for these devices has been reduced in power consumption and cooling fins, etc. ), Etc., to reduce loss. On the other hand, improvement in breakdown voltage is also required from the viewpoint of improving reliability.

  In general, in a semiconductor device such as a diode or a transistor, if the material constituting the drift layer that bears the breakdown voltage is the same, the thickness and carrier concentration of the drift layer necessary to ensure a desired breakdown voltage are determined. As a result, the resistance of the drift layer is also determined. Since a semiconductor device in the power electronics field requires a high breakdown voltage, the ratio of the resistance of the drift layer to the loss of the semiconductor device is large. Therefore, the loss of the semiconductor device can be reduced by reducing the resistance of the drift layer. Here, by reducing the thickness of the drift layer and increasing the carrier concentration, the resistance of the drift layer can be lowered, but the breakdown voltage is lowered accordingly. That is, there is a contradictory demand for reducing the resistance of the drift layer and improving the breakdown voltage. Therefore, conventionally, it has been difficult to reduce the loss while ensuring a high breakdown voltage.

  On the other hand, by alternately arranging thin p-type layers (layers made of a p-type material) and thin n-type layers (layers made of an n-type material) in the drift layer, pn A structure having a junction (super junction structure; SJ structure) has been proposed. According to this, the drift layer having the SJ structure has a high breakdown voltage due to the function of the depletion layer formed by the pn junction described above. On the other hand, the n-type layer in the SJ structure can serve as a current flow path to ensure low resistance. Furthermore, the resistance of the drift layer can be further reduced by increasing the number of p-type layers and n-type layers. As a result, it is possible to reduce the loss while ensuring a high breakdown voltage (see, for example, Non-Patent Document 1).

TSUTSUHIKO FUJIHIRA, “Theory of Semiconductor Super Junction Devices”, J. Am. Appl. Phys. 1997, Vol. 36, p 6254-6262.

  When the above-described SJ structure is applied to a drift layer of a semiconductor device, for example, a vertical MOSFET that is an oxide field effect transistor (MOSFET) that is advantageous in reducing resistance of the drift layer, a plane including the substrate It is necessary to form a thin p-type layer and an n-type layer repeating structure extending in a direction intersecting (longitudinal direction). In general, the p-type layer and the n-type layer are formed by introducing impurities by a method such as ion implantation and then diffusing the impurities by annealing. However, in order to form the above-mentioned thin p-type layer and n-type layer, it is necessary to selectively diffuse in the vertical direction while suppressing the diffusion of impurities in the horizontal direction, and actual manufacture is very difficult. It is. In addition, even if it is possible to manufacture a vertical MOSFET including an SJ structure by employing a complicated manufacturing process, there arises a problem that the manufacturing cost increases. Further, as described above, in order to further reduce the resistance of the drift layer, it is necessary to increase the number of p-type layers and n-type layers (to increase the degree of integration). However, since the impurities in the SJ structure diffuse in processes such as epitaxial growth and thermal oxidation performed in the manufacturing process of the semiconductor device after the SJ structure is formed, there is a limit to the increase in the degree of integration.

  SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device that is easy to manufacture and that can achieve low loss while ensuring a high breakdown voltage, and to provide a manufacturing method for manufacturing the semiconductor device. It is.

  A semiconductor device according to the present invention includes a substrate made of a semiconductor and an n-type layer formed on the substrate. The n-type layer has a groove formed so as to extend from the second surface, which is the surface opposite to the first surface, which is the surface on the substrate side, toward the first surface. An insulator is disposed at the bottom of the groove, and a metal film capable of making Schottky contact with the n-type layer is formed so as to be in contact with the side wall of the groove.

  The present inventor has intensively studied a semiconductor device that is easy to manufacture and that can achieve low loss while ensuring a high breakdown voltage. As a result, instead of the pn junction in the conventional SJ structure, a structure using a Schottky barrier (Super Schottky Barrier structure; SSB structure) is arranged in the drift layer, so that manufacturing is easy and high breakdown voltage is secured. However, the present inventors have found that a semiconductor device capable of reducing loss can be provided. Specifically, in the n-type layer on the substrate, which is a drift layer, a groove is provided in which a metal film capable of Schottky contact with the n-type layer is formed on the side wall. As a result, according to the semiconductor device of the present invention, in the off state where no current flows in the n-type layer, the SSB structure is caused by the function of the depletion layer formed near the sidewall of the groove in the n-type layer by the Schottky contact described above. The drift layer having can secure a high breakdown voltage. On the other hand, in the ON state in which current flows through the n-type layer, the conductive impurity concentration of the n-type layer that becomes the current flow path in the SSB structure can be increased, so that the resistance of the current flow path is consequently reduced. Can be lowered.

  Furthermore, by disposing an insulator at the bottom of the groove, it is possible to prevent the metal film and the electrode disposed in contact with the substrate from being electrically short-circuited.

  Further, as described above, since it is necessary to form a pn junction in the SJ structure, it is introduced when a process performed at a high temperature such as thermal oxidation or epitaxial growth is performed after the process of forming the pn junction. Impurities are diffused to each other beyond the pn junction. In the SJ structure, due to this restriction, there is a limit to increasing the integration degree of the repetitive structure of the p-type layer and the n-type layer and reducing the resistance of the drift layer. On the other hand, according to the SSB structure provided in the semiconductor device of the present invention, since the Schottky contact is employed instead of the pn junction in the SJ structure, the degree of integration of the grooves for forming the Schottky contact is increased. On the other hand, there is no restriction due to diffusion as described above. As a result, the resistance of the drift layer can be further reduced by increasing the degree of integration of the grooves.

  Further, as described above, in the SJ structure, as applied to the drift layer of the vertical MOSFET, the thin p-type layer and the n-type layer are repeatedly extended in the direction (vertical direction) intersecting the plane including the substrate. It may be necessary to form a structure. However, in the method generally adopted in the formation of the p-type layer and the n-type layer, the impurity is diffused by annealing after introducing the impurity by a method such as ion implantation, and the lateral diffusion of the impurity is suppressed. However, it is necessary to selectively diffuse in the vertical direction, and actual manufacture is very difficult. In addition, even if it is possible to manufacture a vertical MOSFET including an SJ structure by employing a complicated manufacturing process, there arises a problem that the manufacturing cost increases. On the other hand, according to the SSB structure provided in the semiconductor device of the present invention, a Schottky junction is adopted instead of the pn junction in the SJ structure, and the groove for forming the Schottky contact is formed by RIE (Reactive Ion Etching). It can be formed by general etching such as reactive ion etching, and metal film can be formed by EB (Electron Beam), CVD (Chemical Vapor Deposition), etc. The general method can be adopted. As a result, a semiconductor device including a drift layer having an SSB structure can be manufactured easily and without increasing the manufacturing cost. Furthermore, since the barrier height can be freely set by the material of the metal film, the degree of freedom of the configuration of the semiconductor device is improved.

  As described above, according to the semiconductor device of the present invention, it is possible to provide a semiconductor device capable of reducing loss while ensuring a high breakdown voltage. That is, in a semiconductor device having a general structure, if the material of the drift layer is determined, the breakdown voltage cannot be improved and the drift layer resistance cannot be simultaneously reduced beyond a certain limit (physical limit). However, like the SJ structure, by providing the drift layer with the SSB structure, the resistance of the drift layer can be reduced while improving the breakdown voltage beyond the physical limit. Since the SSB structure can improve the degree of integration more than that of the SJ structure, the resistance of the drift layer can be further lowered than that of the SJ structure. Furthermore, since the SSB structure is easier to manufacture than the SJ structure, the manufacturing cost of the semiconductor device can be kept lower than that of the SJ structure.

  Here, the n-type layer refers to a layer made of a material whose conductivity type is n-type. Further, the metal film includes not only a film that is thinner than the width of the groove and formed along the side wall of the groove, but also a film that is formed so as to fill the groove.

In addition, the metal capable of Schottky contact with the n-type layer is appropriately selected according to the concentration of an n-type impurity (n-type impurity), the required breakdown voltage, the material of the n-type layer, and the like. be able to. For example, when the n-type impurity concentration is 1 × 10 ¹⁶ / cm ³ , the Schottky barrier is preferably 1.06 eV or more. Thereby, the leakage current in 250 degreeC and 1200V can be 1000 microamperes or less. Here, for example, when silicon carbide is used as the material of the n-type layer, the metals that can be in Schottky contact with the n-type layer are cobalt (Co), nickel (Ni), germanium (Ge), selenium (Se), and tellurium. (Te), palladium (Pd), rhodium (Rh), iridium (Ir), platinum (Pt), gold (Au), and the like.

Further, in order to further reduce the resistance of the drift layer, for example, when the concentration of the n-type impurity is 1 × 10 ¹⁷ / cm ³ , the Schottky barrier is preferably 1.16 eV or more. Thereby, the leakage current at 250 ° C. and 1200 V can be set to 100 μA or less. Here, for example, when silicon carbide is employed as the material for the n-type layer, the metals that can be in Schottky contact with the n-type layer are nickel (Ni), palladium (Pd), iridium (Ir), platinum (Pt), gold (Au).

In order to further reduce the resistance of the drift layer, for example, when the concentration of the n-type impurity is 1 × 10 ¹⁸ / cm ³ , the Schottky barrier is preferably 1.27 eV or more. Thereby, the leakage current at 250 ° C. and 1200 V can be 10 μA or less. Here, for example, when silicon carbide is used as the material for the n-type layer, the metals that can be in Schottky contact with the n-type layer are nickel (Ni), palladium (Pd), iridium (Ir), platinum (Pt), and the like. Can be mentioned.

  Preferably, the semiconductor device further includes a p-type region formed at a position adjacent to the insulator. As described above, in the semiconductor device of the present invention, by disposing the insulator at the bottom of the groove, it is possible to prevent the metal film and the electrode disposed in contact with the substrate from being electrically short-circuited. ing. Here, the electric field concentrates in the vicinity of the boundary between the insulator and the n-type layer. On the other hand, by further providing a p-type region at a position adjacent to this insulator, the concentration of the electric field can be reduced. Note that the p-type region is a region made of a material whose conductivity type is p-type.

  In the semiconductor device, preferably, in the n-type layer, the concentration of the n-type impurity is gradually increased from the first surface side to the second surface side.

  In order to reduce the resistance of the drift layer, it is desirable to increase the concentration of the n-type impurity in the n-type layer. However, simply increasing the concentration of the n-type impurity may increase the leakage current, particularly at high temperatures. On the other hand, on the first surface side having a large influence on the leakage current, the reduction of the leakage current is emphasized and the concentration of the n-type impurity is reduced, and the second surface side having a relatively small influence on the leakage current is directed to. Thus, by placing importance on reducing the resistance of the drift layer and gradually increasing the concentration of the n-type impurity, the resistance of the drift layer can be reduced while suppressing the leakage current.

  The concentration gradient of the n-type impurity may increase linearly from the first surface to the second surface, for example, but may increase in a curved shape or a step shape, and at least the first The region having a thickness of about 1 μm, preferably about 2 μm from the surface side, may have a lower n-type impurity concentration than the region having a thickness of about 2 μm from the second surface side.

  Preferably, in the semiconductor device, in the n-type layer, the region between the end of the metal film on the substrate side and the first surface has an n-type impurity in the surface layer on the second surface side with respect to the n-type impurity. A region having an impurity concentration relatively lower than the impurity concentration is formed.

  Thereby, the resistance of the drift layer can be reduced while suppressing the leakage current. Specifically, the concentration of the n-type impurity in the region between the substrate side end of the metal film having a large influence on the leakage current and the first surface is higher than the concentration in the surface layer on the second surface side. By forming a low region, the increase in leakage current is suppressed, and by increasing the n-type impurity concentration in other regions that have a relatively small effect on the leakage current, the resistance of the low drift layer is secured. Yes. This region having a low n-type impurity concentration is preferably formed in the vicinity of the boundary between the insulator and the n-type layer where the concentration of the electric field is large. The surface layer on the second surface side refers to a region having a thickness of 2 μm from the surface on the second surface side.

  In the semiconductor device, the substrate and the n-type layer are preferably made of a wide band gap semiconductor. A wide band gap semiconductor has a higher breakdown field strength than a semiconductor such as silicon (Si) generally used in a semiconductor device, so that it is easy to secure a breakdown voltage even if the n-type layer as a drift layer is thinned. . As a result, by reducing the thickness of the drift layer, the resistance of the drift layer can be reduced, and a low-loss semiconductor device can be provided.

  Here, the wide band gap semiconductor refers to a semiconductor material having a band gap larger than that of Si, which has been conventionally used as a semiconductor, and examples thereof include silicon carbide (SiC), gallium nitride (GaN), and diamond.

  The method of manufacturing a semiconductor device according to the present invention includes a step of preparing a substrate made of a semiconductor, an n-type layer forming step of forming an n-type layer on the substrate, and a surface on the substrate side of the n-type layer. A groove forming step of etching to form a groove extending from the second surface, which is the surface opposite to the first surface, toward the first surface, a step of forming an insulator at the bottom of the groove, Forming a metal film capable of being in Schottky contact with the n-type layer so as to be in contact with the side wall of the formed groove. According to the method for manufacturing a semiconductor device of the present invention, the semiconductor device of the present invention having the above-described excellent characteristics can be easily manufactured.

  Preferably, in the method for manufacturing a semiconductor device, the n-type layer forming step includes forming a first n-type layer on the substrate and opening the first n-type layer on a surface opposite to the substrate side. Forming a mask layer having a pattern; and forming a p-type region in the first n-type layer by performing ion implantation on the first n-type layer using the mask layer as a mask. , Removing the mask layer, and forming a second n-type layer on the first n-type layer from which the mask layer has been removed. Further, the groove formed in the groove forming step is formed so as to penetrate the second n-type layer and reach the p-type region.

  Thus, by providing a p-type region formed at a position adjacent to the insulator, it is possible to easily manufacture the semiconductor device of the present invention that can alleviate electric field concentration near the boundary between the insulator and the n-type layer. Can do.

  Preferably, in the method for manufacturing a semiconductor device, the concentration of the impurity whose conductivity type is n-type in the n-type layer formed in the n-type layer forming step is gradually increased from the first surface side to the second surface side. The n-type layer forming step is performed so as to be higher.

  Thereby, in the n-type layer, the n-type impurity concentration gradually increases from the first surface side toward the second surface side, thereby reducing the resistance of the drift layer while suppressing the leakage current. The semiconductor device of the present invention capable of being manufactured can be easily manufactured.

  Note that the n-type layer forming step can be performed by gradually increasing the concentration of the n-type impurity contained in the source gas when the n-type layer forming step is performed by vapor phase epitaxial growth, for example. .

  Preferably, in the semiconductor device manufacturing method, in the n-type layer formed in the n-type layer forming step, the conductivity type is n-type in a region between the end of the metal film on the substrate side and the first surface. The n-type layer formation step is performed so that a region having an n-type impurity concentration relatively lower than the impurity concentration in the surface layer on the second surface side is formed for the impurities.

  As a result, in the n-type layer, an impurity relatively lower than the concentration of the n-type impurity in the surface layer on the second surface side is formed in the region between the end of the metal film on the substrate side and the first surface By forming the region having the concentration, the semiconductor device of the present invention capable of reducing the resistance of the drift layer while suppressing the leakage current can be easily manufactured.

  Note that the n-type layer forming step is performed, for example, when a region between the end of the metal film on the substrate side and the first surface is formed when the n-type layer forming step is performed by vapor phase epitaxial growth. This can be implemented by providing a period during which the concentration of the n-type impurity contained in the gas is lowered.

  Preferably, in the semiconductor device manufacturing method, the concentration of the n-type impurity in the first n-type layer is relative to the concentration of the n-type impurity in the second n-type layer. Therefore, the step of forming the first n-type layer and the step of forming the second n-type layer are carried out so as to be low.

  More specifically, the first n-type layer and the second n-type layer are formed under certain conditions in the steps of forming the first n-type layer and forming the second n-type layer. In forming the first n-type layer, the conditions for forming the first n-type layer can be such that the n-type impurities are less than the conditions for forming the second n-type layer. As a result, on the first surface side that has a large influence on the leakage current, the concentration of the n-type impurity is reduced while focusing on the reduction of the leakage current, and on the second surface side that has a relatively small influence on the leakage current The first n-type layer and the second n-type layer can be formed so that the concentration of the n-type impurity is increased with emphasis on reducing the resistance of the layer. Therefore, the semiconductor device of the present invention capable of reducing the resistance of the drift layer while suppressing the leakage current can be easily manufactured.

  The step of forming the first n-type layer and the step of forming the second n-type layer are, for example, in the step of forming the first n-type layer when these steps are performed by vapor phase epitaxial growth. This can be implemented by making the concentration of the n-type impurity contained in the source gas lower than the step of forming the second n-type layer.

  Preferably, in the semiconductor device manufacturing method, a substrate made of a wide band gap semiconductor is prepared in the step of preparing a substrate made of semiconductor, and an n type layer made of the wide band gap semiconductor is formed in the n type layer forming step. The

  As a result, the wide band gap semiconductor has a higher breakdown electric field strength than a semiconductor such as Si generally used in a semiconductor device, so that it is easy to ensure a breakdown voltage even if the n-type layer as the drift layer is thinned. . As a result, by reducing the thickness of the n-type layer as the drift layer formed in the n-type layer forming step, the resistance of the drift layer can be reduced, and a low-loss semiconductor device can be manufactured.

  As is clear from the above description, according to the semiconductor device and the manufacturing method thereof of the present invention, it is easy to manufacture the semiconductor device and the semiconductor device capable of reducing the loss while ensuring a high breakdown voltage. It is possible to provide a method for manufacturing a semiconductor device that can be manufactured easily.

1 is a schematic cross-sectional view illustrating a configuration of a Schottky diode as a semiconductor device according to a first embodiment. It is a schematic plan view showing a configuration of a one-chip Schottky diode element formed by arranging Schottky diodes. It is a schematic plan view showing a configuration of a one-chip Schottky diode element formed by arranging Schottky diodes. FIG. 3 is a diagram showing an outline of a Schottky diode manufacturing process of the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the Schottky diode of the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the Schottky diode of the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the Schottky diode of the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the Schottky diode of the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the Schottky diode of the first embodiment. FIG. 5 is a schematic cross sectional view for illustrating the method for manufacturing the Schottky diode of the first embodiment. FIG. 6 is a schematic cross-sectional view showing a configuration of a Schottky diode as a semiconductor device of a second embodiment. FIG. 6 is a diagram showing an outline of a Schottky diode manufacturing method of a second embodiment. FIG. 10 is a schematic cross-sectional view for illustrating the method for manufacturing the Schottky diode of the second embodiment. FIG. 10 is a schematic cross-sectional view for illustrating the method for manufacturing the Schottky diode of the second embodiment. FIG. 10 is a schematic cross-sectional view for illustrating the method for manufacturing the Schottky diode of the second embodiment. FIG. 10 is a schematic cross-sectional view for illustrating the method for manufacturing the Schottky diode of the second embodiment. FIG. 10 is a schematic cross-sectional view for illustrating the method for manufacturing the Schottky diode of the second embodiment. FIG. 10 is a schematic cross-sectional view showing a configuration of an oxide field effect transistor (MOSFET) as a semiconductor device of a fourth embodiment. It is a schematic plan view which shows the structure of 1-chip MOSFET element formed by arranging MOSFET. FIG. 10 is a diagram showing an outline of a manufacturing process of a MOSFET according to a fourth embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET of the fourth embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET of the fourth embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET of the fourth embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET of the fourth embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET of the fourth embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET of the fourth embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET of the fourth embodiment. FIG. 10 is a schematic cross sectional view for illustrating the method for manufacturing the MOSFET of the fourth embodiment. FIG. 10 is a schematic cross-sectional view showing a configuration of a modified example of the MOSFET as the semiconductor device of the fourth embodiment. FIG. 10 is a schematic cross-sectional view showing a configuration of a junction field effect transistor (JFET) as a semiconductor device of a fifth embodiment. It is a figure which shows the outline of the manufacturing process of JFET of Embodiment 5. FIG. It is a schematic sectional drawing for demonstrating the manufacturing method of JFET of Embodiment 5. FIG. It is a schematic sectional drawing for demonstrating the manufacturing method of JFET of Embodiment 5. FIG. It is a schematic sectional drawing for demonstrating the manufacturing method of JFET of Embodiment 5. FIG. It is a schematic sectional drawing for demonstrating the manufacturing method of JFET of Embodiment 5. FIG. It is a schematic sectional drawing for demonstrating the manufacturing method of JFET of Embodiment 5. FIG. It is a schematic sectional drawing for demonstrating the manufacturing method of JFET of Embodiment 5. FIG. It is a schematic sectional drawing for demonstrating the manufacturing method of JFET of Embodiment 5. FIG. It is a schematic sectional drawing for demonstrating the manufacturing method of JFET of Embodiment 5. FIG.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

(Embodiment 1)
FIG. 1 is a schematic cross-sectional view showing a configuration of a Schottky diode as a semiconductor device according to the first embodiment which is an embodiment of the present invention. 2 and 3 are schematic plan views showing the configuration of a one-chip Schottky diode element formed by arranging Schottky diodes. With reference to FIGS. 1 to 3, the configuration of a Schottky diode which is a semiconductor device according to the first embodiment of the present invention will be described.

  Referring to FIG. 1, a Schottky diode 10 which is a semiconductor device according to the first embodiment of the present invention includes a substrate 11 made of a wide band gap semiconductor, and an n-type layer 12 formed on the substrate 11. Yes. The n-type layer 12 has a groove 13 formed so as to extend from the second surface 12B, which is the surface opposite to the first surface 12A, which is the surface on the substrate 11 side, toward the first surface 12A. ing. Inside the groove 13, an oxide layer 14 as an insulator is disposed at a position in contact with the bottom wall 13 </ b> A that is the bottom of the groove 13, and the n-type layer 12 is in contact with the side wall 13 </ b> B of the groove 13. And a Schottky contactable metal film 15 is formed to fill the groove 13. Furthermore, an anode electrode 16 is disposed on the second surface 12B of the n-type layer 12. The end face of the anode electrode 16 is located at a position away from the position of the side wall 13B of the groove 13 by a predetermined distance. From a different point of view, the width of the anode electrode 16 is smaller than the distance between two adjacent grooves 13. Therefore, in the region adjacent to the end face of the anode electrode 16, the metal film 15 is in contact with the second surface 12 </ b> B that is the upper surface of the n-type layer 12. The metal film 15 is formed so as to extend from the inside of the groove 13 to the second surface 12B, which is the upper surface of the n-type layer 12, and the anode electrode 16. Further, a cathode electrode (not shown) is disposed on the substrate 11 so as to be in contact with the substrate 11.

  Further, the Schottky diode 10 in FIG. 1 is one unit of a repetitive structure in a one-chip Schottky diode element. For example, the Schottky diode element 1 has an anode electrode 16 of the Schottky diode 10 as shown in FIG. It may be arranged in a stripe shape, or may be arranged in a lattice shape as shown in FIG. The planar shape of the anode electrode 16 can be a polygonal shape, for example.

  Next, the operation of the Schottky diode 10 in the first embodiment will be described. Referring to FIG. 1, when a reverse voltage is applied (when the Schottky diode is in an off state), that is, when a negative voltage is applied to the anode electrode, the n-type layer starts from the sidewall of groove 13. A depletion layer spreads toward 12. For this reason, no current flows through the n-type layer 12 and a breakdown voltage is secured. On the other hand, when a forward voltage is applied (when the Schottky diode is in an on state), that is, when a positive voltage is applied to the anode electrode, the depletion layer does not spread in the n-type layer 12, so that the n-type A current flows using the layer 12 as a current path.

  The oxide layer 14 has a function of preventing an electrical short circuit between the metal film 15 and the cathode electrode. Considering that the breakdown voltage of the oxide is about 10 MV / cm, the thickness of the oxide layer 14 is 1.0 μm or more with respect to a withstand voltage of 1 kV, and further considering the reliability, it is 1.5 μm or more. It is preferable.

  With the above configuration, according to the Schottky diode as the semiconductor device of the present embodiment having the SSB structure, the concentration of the n-type impurity in the n-type layer is increased while ensuring a high breakdown voltage, and the groove By increasing the degree of integration, the resistance of the drift layer can be further reduced to reduce the loss.

  Next, as an embodiment of a method for manufacturing a semiconductor device of the present invention, a method for manufacturing a Schottky diode according to Embodiment 1 will be described with reference to the drawings. FIG. 4 is a diagram schematically showing the Schottky diode manufacturing process of the first embodiment. 5 to 10 are schematic cross-sectional views for explaining the method for manufacturing the Schottky diode of the first embodiment. A manufacturing method of the Schottky diode according to the first embodiment will be described with reference to FIGS.

  As shown in FIG. 4, after a substrate preparation step, which is a step of preparing a substrate made of a wide band gap semiconductor, is first performed, an n-type layer formation step of forming an n-type layer on the substrate is performed. Specifically, as shown in FIG. 5, n-type layer 12 (for example, a silicon carbide layer containing an n-type impurity) is formed on a wide band gap semiconductor prepared in the substrate preparation step, for example, substrate 11 made of silicon carbide. It is formed. This n-type layer forming step can be performed, for example, by vapor phase epitaxial growth using a source gas containing an n-type impurity.

  Next, as shown in FIG. 4, a groove extending from the second surface, which is the surface opposite to the first surface, which is the substrate-side surface, to the first surface is etched in the n-type layer. A groove forming step to be formed is performed. The groove forming process is performed in the order of a mask layer forming process, a mask pattern forming process, and an etching process. Specifically, as shown in FIG. 5, for example, a thermal oxide film 17 </ b> A and an oxide film 18 </ b> A are formed as a mask layer on the second surface 12 </ b> B that is the surface opposite to the substrate 11 side of the n-type layer 12. The process is performed as a mask layer forming process. This mask layer forming step can be performed, for example, by forming the thermal oxide film 17A by thermally oxidizing the second surface 12B side and further forming the oxide film 18A by CVD.

  Further, as shown in FIG. 6, a resist film having an opening corresponding to the shape of the desired groove 13 is formed on the oxide film 18A, for example, by photolithography, and the oxide film 18A and By removing a part of the thermal oxide film 17A, a mask pattern forming process is performed. Thereafter, a step of removing the resist film is performed. Then, using the thermal oxide film 17A and the oxide film 18A in which the opening pattern is formed by the above process as a mask, the etching process is performed by forming the groove 13 in the n-type layer 12 by RIE, for example.

  Next, as shown in FIG. 4, an insulator forming step for forming an insulator at the bottom of the groove is performed. The insulator forming step is performed in the order of the oxide layer forming step and the etching step. Specifically, as shown in FIG. 7, the inner peripheral surface of the groove 13 is sacrificial oxidized by, for example, thermal oxidation. Then, the oxide film, thermal oxide film 17A and oxide film 18A formed by the sacrificial oxidation are removed by etching. Thereafter, a thermal oxide film 17B extending from the inner peripheral surface of the trench 13 to the second surface 12B of the n-type layer 12 is formed by, for example, thermal oxidation. Then, on the thermal oxide film 17B, an oxide film 18B that fills the inside of the trench 13 and extends to the second surface 12B of the n-type layer 12 is formed by CVD. In this way, the oxide layer forming step is completed. Further, as shown in FIG. 8, the thermal oxide film 17B and the oxide film 18B are reduced by, for example, RIE, and the thermal oxide film 17B and the oxide film other than the thermal oxide film 17B and the oxide film 18B near the bottom wall 13A of the trench 13 are formed. The etching process is completed by removing 18B. The thermal oxide film 17B and the oxide film 18B remaining in the vicinity of the bottom wall 13A of the groove 13 are the oxide layer 14 as an insulator. Thereafter, sacrificial oxidation is performed on the surface of the second surface 12B of the n-type layer 12 and the inner peripheral surface of the groove 13 where the n-type layer 12 is exposed by thermal oxidation. Thereafter, the thermal oxide film formed by sacrificial oxidation is removed by etching.

  Next, an anode electrode forming step is performed as shown in FIG. Specifically, as shown in FIG. 9, for example, a resist film is applied so as to fill the inside of the groove 13 and extend onto the second surface 12 </ b> B of the n-type layer 12. Then, the resist film of the other part is removed by development processing while leaving the resist film 21 slightly wider than the width of the groove 13 by photolithography with respect to the resist film. In this manner, a resist film 21 that fills the inside of the groove 13 and partially extends on the second surface 12B of the n-type layer 12 is formed. Then, a metal such as tungsten (W) constituting the anode electrode 16 is deposited so as to cover the second surface 12B of the n-type layer 12 and the upper surface of the resist film 21. Thereafter, the metal film deposited on the resist film 21 is removed together with the resist film 21 by removing the resist film 21. As a result, the anode electrode 16 made of the metal film located on the second surface 12B of the n-type layer 12 is formed, and the metal other than the portion that becomes the anode electrode 16 (positioned on the groove 13) is formed. Metal) was removed (lift-off). Further, the position of the end surface of the anode electrode 16 on the groove 13 side is arranged at a position away from the position of the side wall of the groove 13 toward the outside of the groove 13. Note that the position of the end face of the anode electrode 16 may be determined so as to overlap the position of the side wall of the groove 13 (so that the side wall of the groove 13 and the end face of the anode electrode 16 constitute the same plane).

  Next, as shown in FIG. 4, a metal film is formed to form a metal film capable of being in Schottky contact with the n-type layer so as to be in contact with the side wall 13B of the groove 13 in which the oxide layer 14 as an insulator is formed. A process is performed. The metal film forming process is performed in the order of the Schottky metal film forming process and the bonding electrode forming process. Specifically, as shown in FIG. 10, first, a metal such as Ni that can make Schottky contact with the n-type layer 12 is formed from the upper surface of the oxide layer 14 located at the bottom of the groove 13, and the sidewalls 13B, n of the groove 13 A Schottky metal film forming step of forming the Schottky metal film 22 by performing vapor deposition so as to cover the second surface 12B of the mold layer 12 and the anode electrode 16 is performed. Since the thickness of the Schottky metal film 22 is sufficiently smaller than the width of the groove 13 as can be seen from FIG. 10, the inside of the groove 13 is not filled with the Schottky metal film 22. Thereafter, a bonding electrode forming step for forming the bonding electrode 23 is performed by depositing a metal such as aluminum (Al) which is easy to bond on the Schottky metal film 22. As can be seen from FIG. 10, the bonding electrode 23 fills the inside of the groove 13 and is formed so as to extend on the second surface 12 </ b> B of the n-type layer 12. The metal film 15 is constituted by the bonding electrode 23 and the Schottky metal film 22 formed in this way. Thus, the metal film 15 is in contact with the side wall 13B of the groove 13 (which is a metal capable of being in Schottky contact with the n-type layer 12) and one or more other metal films (one or more layers). A multilayer film structure including the bonding electrodes 23) may be used, but depending on the type of metal constituting the Schottky metal film 22, the entire metal film 15 may be composed of only the Schottky metal film 22.

  The Schottky diode 10 of the first embodiment can be manufactured by the above manufacturing method. Since this manufacturing method does not include difficult steps, the Schottky diode 10 according to the first embodiment can be easily manufactured according to this manufacturing method.

The first embodiment can be implemented, for example, under the following conditions. With reference to FIG. 1, 4H—SiC (hexagonal crystal) can be used as the substrate 11 and the (0001) plane can be used as the main surface. At this time, the substrate 11 can be used as an n ⁺ substrate by including about 1 × 10 ¹⁹ / cm ³ of nitrogen as an n-type impurity. The thickness of the substrate 11 can be about 0.4 mm. The distance from the first surface 12A of the n-type layer 12 to the second surface 12B is about 10 μm, and the width of the n-type layer 12 in the portion where the groove 13 is formed (the groove 13 adjacent to the side wall 13B of the groove 13). The distance to the side wall 13B of the groove 13 can be about 1.8 μm, and the width of the groove 13 (the distance between the side walls 13B and 13B in the groove 13) can be about 2 μm. Furthermore, the distance between the oxide layer 14 and the substrate 11 can be about 1 μm, and the thickness of the oxide layer 14 can be about 1.0 μm to 2.0 μm.

In the manufacturing method, referring to FIG. 5, n-type layer 12 may be formed by, for example, vapor phase homoepitaxial growth of SiC using silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases. it can. The n-type layer 12 contains about 1 × 10 ¹⁷ / cm ³ of nitrogen as an n-type impurity, and can have a thickness of about 10 μm. Furthermore, the thermal oxide film 17A can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C. The oxide film 18A can be formed to a thickness of about 3 μm by CVD or the like.

Referring to FIG. 6, removal of thermal oxide film 17A and oxide film 18A can be performed by, for example, RIE using a tetrafluoromethane (CF ₄ ) -based gas. Further, the groove 13 can be formed by RIE using sulfur hexafluoride (SF ₆ ) and oxygen (O ₂ ) based gases. The depth of the groove 13 can be about 9 μm.

  Referring to FIG. 7, thermal oxide film 17B can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C. Furthermore, the oxide film 18B can be formed to a thickness of about 1.5 μm by CVD using tetraethoxysilane (TEOS).

Referring to FIG. 8, thermal oxide film 17B and oxide film 18B are thinned by reducing the thickness of thermal oxide film 17B and oxide film 18B in trench 13 by about 8 μm by RIE using CF ₄ gas. Can be implemented. Furthermore, the thermal oxide film by sacrificial oxidation can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C.

  Referring to FIG. 9, anode electrode 16 may be formed by vapor-depositing a metal such as tungsten (W), molybdenum (Mo), titanium (Ti) or the like to a thickness of about 0.1 μm. it can. Furthermore, referring to FIG. 10, Schottky metal film 22 can be formed by vapor-depositing a metal such as Ni or Pt to a thickness of about 0.2 μm. The bonding electrode 23 can be formed by evaporating a metal such as Al to a thickness of 2 μm or more and 5 μm or less.

(Embodiment 2)
FIG. 11 is a schematic cross-sectional view showing a configuration of a Schottky diode as a semiconductor device according to the second embodiment which is an embodiment of the present invention. With reference to FIG. 11, the structure of the Schottky diode which is the semiconductor device of Embodiment 2 of this invention is demonstrated.

  Referring to FIG. 11, Schottky diode 10 in the second embodiment and Schottky diode 10 in FIG. 1 described above have basically the same configuration. However, the Schottky diode 10 according to the second embodiment is further provided with a p-type region 19 at a position in contact with the bottom wall 13A of the groove 13 adjacent to the oxide layer 14 as an insulator. This is different from the Schottky diode 10 of FIG.

  Note that the Schottky diode 10 in FIG. 11 is equivalent to one unit of a repetitive structure in a one-chip Schottky diode element, like the Schottky diode 10 in FIG. 1 in the first embodiment. As shown in FIG. 2, for example, the Schottky diode element 1 may be one in which the anode electrodes 16 of the Schottky diode 10 are arranged in a stripe shape, or arranged in a lattice shape as shown in FIG. It may be a thing. The planar shape of the anode electrode 16 can be a polygonal shape, for example. Further, the position where p type region 19 is arranged is not limited to the position in contact with bottom wall 13A of groove 13, for example, so as to be adjacent to the bottom and sides of oxide layer 14 (that is, the bottom wall of oxide layer 14). And may be disposed so as to contact the side wall or to face the bottom wall and / or the side wall of the oxide layer 14 with a space therebetween. The width of the p-type region 19 may be the same as the width of the groove 13, but the width of the p-type region 19 is preferably wider than the width of the groove 13. Further, the p-type region 19 may be disposed with a gap from the oxide layer 14.

  Next, the operation of the Schottky diode 10 in the second embodiment will be described. The Schottky diode 10 of the second embodiment basically operates in the same manner as the Schottky diode 10 of the first embodiment. However, there are differences in the following points. That is, in the Schottky diode 10, by disposing the oxide layer 14 as an insulator at the bottom of the groove 13, the metal film 15 and a cathode electrode (not shown) disposed in contact with the substrate are electrically short-circuited. The state is prevented. Here, when a reverse voltage is applied, the electric field concentrates in the vicinity of the region α, which is near the boundary between the oxide layer 14 and the n-type layer 12. In the Schottky diode 10 of the second embodiment, unlike the Schottky diode 10 of the first embodiment, the p-type region 19 is further provided at a position adjacent to the oxide layer 14 to thereby concentrate the electric field described above. Can be relaxed. As a result, in the Schottky diode 10 of the second embodiment, the reliability regarding the breakdown voltage is further improved.

  Next, as an embodiment of a method for manufacturing a semiconductor device of the present invention, a method for manufacturing a Schottky diode according to Embodiment 2 will be described with reference to the drawings. FIG. 12 is a diagram schematically illustrating a method for manufacturing the Schottky diode according to the second embodiment. 13 to 17 are schematic cross-sectional views for explaining the method for manufacturing the Schottky diode of the second embodiment. A manufacturing method of the Schottky diode according to the second embodiment will be described with reference to FIGS.

  The method for manufacturing the Schottky diode according to the second embodiment is basically the same as the method for manufacturing the Schottky diode according to the first embodiment. However, in the n-type layer forming process in the first embodiment, the above-described p-type region needs to be formed in the second embodiment, and the groove formed in the groove forming process in the first embodiment is the same as that described above. The second embodiment is different from the first embodiment in that the p-type region is formed. Specifically, referring to FIG. 12, the manufacturing process of the second embodiment is different from that of the first embodiment in the processes from the substrate preparation process to the insulator formation process. Hereinafter, these steps will be mainly described.

  As shown in FIG. 12, after the substrate preparation step is performed as in the first embodiment, a first n-type layer forming step for forming a first n-type layer on the substrate is performed. Specifically, as shown in FIG. 13, first n-type layer 12E (for example, a silicon carbide layer containing n-type impurities) is formed on substrate 11 made of a wide bandgap semiconductor, for example, silicon carbide, prepared in the substrate preparation step. ) Is formed. This first n-type layer forming step can be performed, for example, by vapor phase epitaxial growth using a source gas containing an n-type impurity.

  Next, as shown in FIG. 12, a p-type region forming step for forming a p-type region in the first n-type layer 12E is performed. Specifically, as shown in FIG. 14, for example, a surface of the first n-type layer 12E opposite to the substrate 11 is thermally oxidized to form a thermal oxide film 17A, and further, an oxide film 18A is formed by CVD. Is formed. Then, for example, a resist film having an opening is formed on oxide film 18A by photolithography. Then, by partially removing the oxide film 18A and the thermal oxide film 17A by RIE using the resist film as a mask, the thermal oxide film 17A and the oxide film 18A are formed on the first n-type layer 12E. A step of forming a mask layer having an opening pattern is performed. By performing ion implantation using this mask layer as a mask, a step of forming p-type region 19 in first n-type layer 12E is performed.

  Next, as shown in FIG. 12, a second n-type layer forming step for forming a second n-type layer on the first n-type layer is performed. Specifically, as shown in FIG. 15, activation annealing is performed after a step of removing the mask layer formed of the thermal oxide film 17A and the oxide film 18A used as the mask is performed. Further, the first n-type layer 12E is sacrificial oxidized by, for example, thermal oxidation to form a thermal oxide film 17B. Thereafter, as shown in FIG. 16, after thermal oxide film 17B is removed using a technique such as wet etching, second n-type layer 12F (for example, containing an n-type impurity) is formed on first n-type layer 12E. A step of forming a silicon carbide layer) is performed. The step of forming the second n-type layer can be performed by vapor phase epitaxial growth using a source gas containing an n-type impurity, for example, as in the first n-type layer forming step. The n-type layer 12 of FIG. 11 is configured by the second n-type layer 12F and the first n-type layer 12E thus formed. The second n-type layer 12F may be a single layer as shown in FIG. 16, but may be a multilayer film of two or more layers.

  Next, as shown in FIG. 12, a groove forming step is performed in which grooves are formed so as to penetrate the second n-type layer and reach the p-type region. The groove forming process is performed in the order of a mask layer forming process, a mask pattern forming process, and an etching process. Specifically, as shown in FIG. 16, a process of forming, for example, the thermal oxide film 17C and the oxide film 18B as the mask layer on the second surface 12B of the second n-type layer 12F is a mask layer forming process. To be implemented. This mask layer forming step can be performed by, for example, forming the thermal oxide film 17C by thermally oxidizing the second surface 12B of the second n-type layer 12F and further forming the oxide film 18B by CVD. .

  Further, as shown in FIG. 17, for example, a resist film having an opening corresponding to the shape of the desired groove 13 is formed on the oxide film 18B by photolithography, and using this as a mask, the oxide film 18B and By partially removing the thermal oxide film 17C, an opening pattern corresponding to the opening formed in the resist film in the oxide film 18B and the thermal oxide film 17C is formed. Thereafter, the resist film is removed. In this way, the mask pattern forming process is performed. Then, the second n-type layer 12F is partially removed by, for example, RIE, using the thermal oxide film 17C and the oxide film 18B in which the opening pattern is formed by the above-described process as a mask, so that the second n-type layer is removed. A groove 13 that penetrates 12F and reaches the p-type region is formed. In this way, the etching process is performed.

  Next, as shown in FIG. 12, the insulator forming step, the anode electrode forming step, and the metal film formability step are sequentially performed as in the first embodiment.

  The Schottky diode 10 of the second embodiment can be manufactured by the above manufacturing method. Since this manufacturing method does not include difficult steps, the Schottky diode 10 according to the second embodiment can be easily manufactured according to this manufacturing method.

  The conditions for carrying out the second embodiment can be basically the same as those in the first embodiment, but the specific conditions for carrying out the second embodiment are as follows. For example, the following conditions can be employed.

Referring to FIG. 11, p-type region 19 can have a thickness of about 1 μm. In the manufacturing method, referring to FIG. 13, first n-type layer 12E is formed by vapor phase homoepitaxial growth of SiC using, for example, silane (SiH ₄ ) and propane (C ₃ H ₈ ) as source gases. can do. Further, it contains about 1 × 10 ¹⁵ / cm ³ of nitrogen as an n-type impurity, and the thickness can be about 2 μm.

  Referring to FIG. 14, thermal oxide film 17A can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C. The oxide film 18A can be formed to a thickness of about 1 μm by CVD or the like.

  Referring to FIG. 15, activation annealing can be performed at a temperature of about 1700 ° C. for about 20 minutes, for example. The thermal oxide film 17B can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C.

Referring to FIG. 16, second n-type layer 12F can be formed, for example, by vapor phase homoepitaxial growth of SiC using SiH ₄ and C ₃ H ₈ as source gases. The second n-type layer 12F contains about 1 × 10 ¹⁷ / cm ³ of nitrogen as an n-type impurity and can have a thickness of about 9 μm.

Referring to FIG. 17, removal of thermal oxide film 17C and oxide film 18B can be performed, for example, by RIE using a CF ₄ gas. Furthermore, the groove 13 can be formed by RIE using SF ₆ and O ₂ -based gas, and the depth of the groove 13 can be about 8 μm.

Note that the first n-type layer 12E contains about 1 × 10 ¹⁵ / cm ³ of nitrogen as an n-type impurity under the above conditions, whereas the second n-type layer 12F has 1 × 10 ¹⁷ / cm ^3. The reason for the degree will be described in a third embodiment to be described later.

(Embodiment 3)
Next, the structure of the Schottky diode which is the semiconductor device of Embodiment 3 which is one embodiment of the present invention will be described. The Schottky diode in the third embodiment and the Schottky diode in the first and second embodiments described above basically have the same configuration. However, the Schottky diode of the third embodiment has a relatively low n-type impurity concentration on the first surface side and a relatively high n-type impurity concentration on the second surface side in the n-type layer. This is different from the Schottky diodes of the first and second embodiments. Specifically, referring to FIGS. 1 and 11, in the Schottky diode of the third embodiment, in the n-type layer, the concentration of n-type impurities is directed from the first surface 12A side to the second surface 12B side. It is getting higher gradually.

  Next, the operation of the Schottky diode 10 in the third embodiment will be described with reference to FIG. 1 and FIG. The Schottky diode 10 of the third embodiment basically operates in the same manner as the Schottky diode 10 of the first and second embodiments. However, there are differences in the following points. That is, when a reverse voltage is applied to the n-type layer 12 of the Schottky diode 10, the concentration of the n-type impurity is low on the first surface 12A side having a large influence on the leakage current. Reduced. On the other hand, since the concentration of the n-type impurity is increased toward the second surface 12B side having a relatively small influence on the leakage current, the resistance when a forward voltage is applied can be reduced.

  The concentration gradient of the n-type impurity may increase linearly from the first surface to the second surface, for example, but the same effect can be obtained even if it increases in a curved or stepped manner. It is done.

  In the Schottky diode according to the modification of the third embodiment, the n-type impurity concentration in the n-type layer 12 does not gradually change, but the end portion and the first surface of the metal film 15 on the substrate 11 side. A region having an n-type impurity concentration that is relatively lower than the n-type impurity concentration in the surface layer on the second surface 12B side is formed in the region between 12A.

  According to the modification of the third embodiment, as in the third embodiment where the concentration of the n-type impurity is gradually changed, the end of the metal film 15 on the substrate 11 side having a large influence on the leakage current is In the region between the first surface 12A and the n-type impurity concentration is low, the leakage current is reduced. On the other hand, since the concentration of the n-type impurity is relatively high in other portions having a relatively small influence on the leakage current, the resistance when a forward voltage is applied can be reduced.

  Next, a method for manufacturing a Schottky diode according to the third embodiment will be described as an embodiment of a method for manufacturing a semiconductor device of the present invention.

The manufacturing method of the Schottky diode of the third embodiment is basically the same as the manufacturing method of the Schottky diode of the first and second embodiments. However, in the step of forming the n-type layer in the first embodiment and the second embodiment, the third embodiment needs to change the concentration of the n-type impurity in the n-type layer in the third embodiment. It is different from Form 2. Specifically, with respect to the manufacturing method of the Schottky diode of the third embodiment whose basic structure is the same as that of the Schottky diode shown in FIG. 1, with reference to FIG. 4 and FIG. The n-type layer forming step can be performed so that the concentration gradually increases from the first surface 12A side toward the second surface 12B side. More specifically, for example, when the n-type layer 12 is formed by vapor phase epitaxial growth, the amount of nitrogen added as an n-type impurity is gradually increased, and the n-type impurity concentration in the n-type layer 12 is set to the first level. The n-type layer forming step can be performed so that the surface 12A side has 5 × 10 ¹⁶ / cm ³ and the second surface 12B side has 5 × 10 ¹⁷ / cm ³ . Thereby, the Schottky diode of Embodiment 3 can be manufactured.

4 and 5, in the n-type layer 12 formed in the n-type layer forming step, in the region between the end of the metal film 15 on the substrate 11 side and the first surface 12A. The n-type layer forming step can be performed so that a region having an impurity concentration relatively lower than the n-type impurity concentration in the surface layer on the second surface 12B side is formed. Specifically, for example, when the n-type layer 12 is formed by vapor phase epitaxial growth, the amount of nitrogen added as an n-type impurity is set to the end of the metal film 15 on the substrate 11 side and the first surface 12A. The concentration of the n-type impurity in the n-type layer 12 is 1 × 10 ¹⁵ / cm ³ in part or all of the process of growing the region between and 1 × 10 ¹⁷ / cm ³ in the other growth processes. An n-type layer forming step can be performed. Thereby, the Schottky diode of the modification of Embodiment 3 can be manufactured.

In addition, with respect to the manufacturing method of the Schottky diode of the third embodiment having the same basic structure as that of the Schottky diode shown in FIG. 11, the first n-type layer formation will be described with reference to FIGS. In the step, the first n-type layer 12E is formed so that the concentration of the n-type impurity is reduced, and in the second n-type layer forming step, the concentration of the n-type impurity is n in the first n-type layer 12E. The second n-type layer 12F may be formed so as to be relatively higher than the concentration of the type impurity. Specifically, as described in the second embodiment, when the first n-type layer 12E and the second n-type layer 12F are formed by vapor phase epitaxial growth, the n-type impurity in the first n-type layer 12E is formed. The amount of nitrogen added as an n-type impurity is changed so that the concentration of nitrogen is about 1 × 10 ¹⁵ / cm ³ and the second n-type layer 12F is about 1 × 10 ¹⁷ / cm ^3. Can do. Thereby, the Schottky diode of the modification of Embodiment 3 can be manufactured.

(Embodiment 4)
FIG. 18 is a schematic cross-sectional view showing a configuration of an oxide film field effect transistor (MOSFET) which is a semiconductor device according to the fourth embodiment which is an embodiment of the present invention. FIG. 19 is a schematic plan view showing the configuration of a one-chip MOSFET element formed by arranging MOSFETs. With reference to FIG. 18 and FIG. 19, the structure of MOSFET which is the semiconductor device of Embodiment 4 of this invention is demonstrated.

  Referring to FIG. 18, MOSFET 30 which is a semiconductor device according to the fourth embodiment of the present invention includes a substrate 31 made of a wide band gap semiconductor and an n-type layer 32 formed on substrate 31. The n-type layer 32 has a groove 33 formed so as to extend from the second surface 32B, which is the surface opposite to the first surface 32A, which is the surface on the substrate 31 side, toward the first surface 32A. ing. Inside the groove 33, an oxide layer 34 as an insulator is disposed at a position in contact with the bottom wall 33 </ b> A that is the bottom of the groove 33. Furthermore, a p-type region 36 containing an impurity (p-type impurity) having a high-concentration conductivity type is formed at a position facing the sidewall 33B of the groove 33 near the second surface 32B of the n-type layer 32. Has been. In addition, an n-type region 37 containing a high-concentration n-type impurity is adjacent to the p-type region 36 in the vicinity of the second surface 32B and on the side opposite to the side where the trench 33 is located when viewed from the p-type region 36. Is formed. Further, it is in contact with the bottoms of the p-type region 36 and the n-type region 37 and extends to a region further away from the groove 33 than the n-type region 37 in a direction away from the groove 33 (that is, the n-type region 37 and p A p-type well 35 containing a low-concentration p-type impurity is formed so as to surround the mold region 36. In the p-type well 35, the upper surface of the portion that is located farther from the groove 33 than the n-type region 37 is located on the same plane as the second surface 32 </ b> B of the n-type layer 32. That is, the p-type well 35 is exposed in the same plane as the second surface 32 B of the n-type layer 32 at a position away from the n-type region 37 when viewed from the groove 33.

  A gate electrode 38 is formed through a gate oxide film 39 so that the p-type well 35 extends from a portion exposed on the second surface 32B of the n-type layer 32 in a direction away from the trench 33. Is formed. The side wall and upper surface of the gate electrode 38 are also covered with the gate oxide film 39. The position of the side wall of the gate oxide film 39 is substantially equal to the position of the end of the n-type region 37 on the side far from the groove 33.

  Further, the groove 33 is in contact with the upper surface of the oxide layer 34, fills the groove 33, and further extends to the second surface 32B that is the upper surface of the n-type layer 32. A source electrode 41 is formed. The source electrode 41 is formed so as to be in contact with the upper surfaces of the p-type region 36 and the n-type region 37, and the sidewall and upper surface of the gate oxide film 39. Further, a drain electrode (not shown) is arranged on the substrate 31 so as to be in contact with the substrate 31.

  18 is one unit of a repetitive structure in a one-chip MOSFET element. For example, as shown in FIG. 19, the MOSFET element 3 has the grooves 33 of the MOSFET 30 arranged in a lattice pattern. it can. The planar shape of the region surrounded by the grooves 33 can be, for example, a polygonal shape. Further, instead of the above-described arrangement described with reference to FIG. 19, MOSFET 30 may be arranged in such a manner that the region surrounded by the lattice shown in FIG.

  Next, the operation of MOSFET 30 in the fourth embodiment will be described. Referring to FIG. 18, when the voltage of gate electrode 38 is 0V, that is, in the off state, the p-type well 35 and the n-type layer 32 located immediately below the gate oxide film 39 are reversely biased to be in a non-conductive state. It becomes. At this time, a depletion layer spreads around the portion of the n-type layer 32 that is in contact with the source electrode 41, and there is no gap between the source electrode 41 and a drain electrode (not shown) arranged so as to contact the substrate 31. No electrical short circuit (SSB structure). Therefore, the n-type impurity concentration of the n-type layer 32 can be increased, and the thickness of the n-type layer 32 can be reduced.

  On the other hand, when a positive voltage is applied to the gate electrode 38, an inversion layer is formed in the vicinity of the p-type well 35 in contact with the gate oxide film 39. As a result, the n-type region 37 and the n-type layer 32 are electrically connected, and current flows as electrons move along the electron flow 47A. At this time, as described above, the MOSFET 30 having the SSB structure can increase the concentration of the n-type impurity in the n-type layer 32 and reduce the thickness of the n-type layer 32, thereby reducing the resistance of the n-type layer 32. be able to. As a result, the MOSFET 30 has a low loss.

  Note that the n-type layer 32 may further include a p-type region at a position adjacent to the oxide layer 34 as in the Schottky diode of the second embodiment. Thereby, the concentration of the electric field in the vicinity of the interface between the oxide layer 34 and the n-type layer 32 can be relaxed. As a result, the reliability related to the breakdown voltage of MOSFET 30 of the fourth embodiment can be further improved.

  Similarly to the Schottky diode of the third embodiment described above, in the n-type layer 32, the n-type impurity concentration is gradually increased from the first surface 32A side to the second surface 32B side. Alternatively, in the region between the end of the source electrode 41 on the substrate 31 side and the first surface 32A, the concentration of the n-type impurity in the surface layer on the second surface 32B side is relatively lower. A region having an n-type impurity concentration may be formed. Thereby, since the concentration of the n-type impurity is low in a region having a large influence on the leakage current, the leakage current is reduced. On the other hand, since the concentration of the n-type impurity is high in the region where the influence on the leakage current is relatively small, the resistance of the n-type layer 32 can be reduced.

  Next, as an embodiment of a method for manufacturing a semiconductor device of the present invention, a method for manufacturing a MOSFET according to Embodiment 4 will be described with reference to the drawings. FIG. 20 is a diagram schematically showing the manufacturing process of the MOSFET according to the fourth embodiment. 21 to 28 are schematic cross-sectional views for explaining the method of manufacturing the MOSFET according to the fourth embodiment. A manufacturing method of the MOSFET according to the fourth embodiment will be described with reference to FIGS.

  As shown in FIG. 20, after a substrate preparation step, which is a step of preparing a substrate made of a wide band gap semiconductor, is first performed, an n-type layer forming step for forming an n-type layer on the substrate is performed. Specifically, as shown in FIG. 21, n-type layer 32 (for example, a silicon carbide layer containing n-type impurities) is formed on a wide band gap semiconductor prepared in the substrate preparation step, for example, substrate 31 made of silicon carbide. It is formed. This n-type layer forming step can be performed, for example, by vapor phase epitaxial growth using a source gas containing an n-type impurity.

  Next, as shown in FIG. 20, a p-type well formation step is performed in which a p-type well is formed in the n-type layer formed in the n-type layer formation step. Specifically, as shown in FIG. 21, for example, a surface of the n-type layer 32 opposite to the surface on the substrate 31 side is thermally oxidized to form a thermal oxide film 42A. Further, an oxide film 43A is formed on the thermal oxide film 42A by CVD. Then, for example, a resist film having an opening is formed on oxide film 43A by photolithography. Then, the oxide film 43A and the thermal oxide film 42A are partially removed by RIE using the resist film as a mask, thereby forming the thermal oxide film 42A and the oxide film 43A having an opening pattern on the n-type layer 32. A mask layer is formed. Thereafter, the resist film is removed by etching or the like. The p-type well 35 is formed in the n-type layer 32 by performing ion implantation into the n-type layer 32 using this mask layer as a mask.

  Next, as shown in FIG. 20, a p-type region forming step for forming a p-type region containing a high-concentration p-type impurity in the p-type well formed in the p-type well forming step is performed. Specifically, as shown in FIG. 22, for example, after all of oxide film 43A and thermal oxide film 42A are removed, oxide film 43B is formed by CVD. Then, for example, a resist film having an opening is formed on oxide film 43B by photolithography. Using this resist film as a mask, the oxide film 43B is partially removed by RIE, whereby a mask layer made of the oxide film 43B having an opening pattern is formed on the p-type well 35. Thereafter, the resist film is removed. By performing ion implantation using this mask layer as a mask, a p-type region 36 is formed in the p-type well 35.

  Next, as shown in FIG. 20, an n-type region forming step is performed in which an n-type region containing a high-concentration n-type impurity is formed in the p-type well in which the p-type region is formed in the p-type region forming step. . Specifically, as shown in FIG. 23, for example, after all oxide film 43B is removed, oxide film 43C is formed by CVD. Then, for example, a resist film having an opening is formed on oxide film 43C by photolithography. Using this resist film as a mask, oxide film 43C is partially removed by RIE, whereby a mask layer made of oxide film 43C having an opening pattern is formed on p-type well 35 and p-type region 36. The opening pattern formed in the oxide film 43C is formed at a position where the end of the p-type region 36 is exposed. By performing ion implantation using this mask layer as a mask, n-type region 37 is formed.

  Next, as shown in FIG. 20, a groove extending from the second surface, which is the surface opposite to the first surface, which is the substrate-side surface, to the first surface is etched in the n-type layer. A groove forming step to be formed is performed. Specifically, as shown in FIG. 24, for example, after all oxide film 43C is removed, activation annealing is performed. Thereafter, an oxide film 43D is formed by CVD. Then, for example, a resist film having an opening corresponding to a desired groove shape is formed on oxide film 43D by photolithography. Using this resist film as a mask, oxide film 43D is partially removed by RIE according to the opening. As a result, an oxide film 43D having an opening pattern is formed. Thereafter, the resist film is removed by etching or the like. Further, for example, by partially removing n-type layer 32 by RIE using oxide film 43D as a mask, trench 33 is formed in n-type layer 32. At this time, the position of the groove 33 is determined so that the surface of the p-type region 36 and the p-type well 35 is exposed on the side surface of the groove 33.

  Next, as shown in FIG. 20, an insulator forming step for forming an insulator at the bottom of the groove is performed. The insulator forming step is performed in the order of the oxide layer forming step and the etching step. Specifically, as shown in FIG. 25, in the n-type layer 32 in which the groove 33 is formed, the side wall 33B of the groove 33 is sacrificial oxidized by, for example, thermal oxidation. Thereafter, the oxide film 43D and all oxide films including the oxide film formed by the sacrificial oxidation are removed by etching. Thereafter, a thermal oxide film extending from the inner peripheral surface of the trench 33 to the surface of the p-type region 36, the n-type region 37, the p-type well 35 and the second surface 32B of the n-type layer 32 by thermal oxidation, for example. 42B is formed. An oxide film 43E that fills the inside of the trench 33 and extends to the second surface 32B of the n-type layer 32 is formed on the thermal oxide film 42B by CVD. In this way, the oxide layer forming step is completed by forming the thermal oxide film 42B and the oxide film 43E, respectively. Further, the thermal oxide film 42B and the oxide film 43E are reduced by RIE, for example, and the thermal oxide film 42B and the oxide film 43E other than the thermal oxide film 42B and the oxide film 43E near the bottom wall 33A of the trench 33 are removed. The etching process is completed. The thermal oxide film 42B and the oxide film 43E remaining in the vicinity of the bottom wall 33A of the groove 33 are the oxide layer 34 as an insulator.

  Next, as shown in FIG. 20, a gate forming step for forming the gate of the MOSFET is performed. The gate forming process includes a gate oxide film forming process and a gate electrode forming process. Specifically, as shown in FIG. 26, the second surface 32B of the n-type layer 32, the p-type region 36, the n-type region 37, the surface of the p-type well 35, and the inner periphery of the groove 13 by thermal oxidation, for example. Sacrificial oxidation is performed on the surface where the n-type layer 12 is exposed. Thereafter, the thermal oxide film formed by sacrificial oxidation is removed by etching. Thereafter, the surface of the p-type region 36, the n-type region 37, the p-type well 35, and the second of the n-type layer 32 are formed on the inner peripheral surface where the oxide layer 34 is not formed in the groove 33 by thermal oxidation, for example. Thermal oxide film 39A is formed so as to extend onto surface 32B. Further, a polysilicon film 38 is formed on the thermal oxide film 39A by, for example, CVD. Then, for example, a resist film 44A having an opening in a portion other than the shape of the desired gate electrode is formed on the polysilicon film 38 by photolithography. The polysilicon film 38 is partially removed by RIE using the resist film 44A as a mask, whereby the gate electrode 38 is formed as shown in FIG. 26 (gate electrode forming step). Further, as shown in FIG. 27, for example, after removing resist film 44A, oxide film 39B is formed by CVD so as to cover second surface 32B of n-type layer 32 on which gate electrode 38 is formed. . Then, for example, a resist film 44B having openings in portions other than the shape of the desired gate oxide film is formed on oxide film 39B by photolithography. Using this resist film 44B as a mask, oxide film 39B is partially removed by RIE. As a result, the oxide film 39B remains so as to cover the gate electrode 38. The remaining thermal oxide film 39A and oxide film 39B so as to surround the gate electrode 38 are the gate oxide film 39 (gate oxide film forming step).

  Next, as shown in FIG. 20, a metal film forming step of forming a metal film capable of being in Schottky contact with the n-type layer so as to be in contact with the sidewall of the groove in which the oxide layer as an insulator is formed is included. A source electrode forming step is performed. The source electrode forming step is performed in the order of the metal film forming step and the bonding electrode forming step. Specifically, as shown in FIG. 28, for example, after removing the resist film 44B, the sidewall 33B of the groove 33 and the second surface 32B of the n-type layer 32 from above the oxide layer 34 located at the bottom of the groove 33. By depositing a metal such as Ni that can contact the n-type layer 32 and Schottky so as to extend on the surface of the p-type region 36 and the n-type region 37 on the side, the side surface of the gate oxide film 39 and the upper surface. A metal film forming step for forming the metal film 45 is performed. Metal film 45 is Schottky connected to n-type layer 32 and electrically connected to p-type region 36 and n-type region 37. Since the thickness of the metal film 45 is sufficiently smaller than the width of the groove 33, the groove 33 is not filled with the metal film 45. Thereafter, a bonding electrode forming step for forming the bonding electrode 46 is performed by evaporating a metal such as Al that is easy to bond on the metal film 45. The bonding electrode 46 is formed thicker than the metal film 45 and is formed so as to fill the groove 33. The metal film 45 and the bonding electrode 46 become the source electrode 41. Note that the metal film 45 may be thickened to fill the groove 33 (that is, the source electrode 41 is constituted only by the metal film 45), or the bonding electrode 46 may have a multilayer film structure of two or more layers. Also good.

  The MOSFET 30 of the fourth embodiment can be manufactured by the above manufacturing method. Since this manufacturing method does not include difficult steps, the MOSFET 30 of the fourth embodiment can be easily manufactured according to this manufacturing method.

The fourth embodiment can be implemented, for example, under the following conditions. Referring to FIG. 18, 4H—SiC (hexagonal crystal) can be used as the substrate 31 and the (0001) plane can be used as the main surface. At this time, by including about 1 × 10 ¹⁹ / cm ³ of nitrogen as an n-type impurity, it can be used as an n ⁺ substrate. The thickness can be about 0.4 mm. Further, the distance from the first surface 32A to the second surface 32B of the n-type layer 32 as the n drift layer is about 11 μm, and the width of the n-type layer 32 in the portion where the groove 33 is formed (the side wall 33B of the groove 33). To the side wall 33B of the adjacent groove 33: the drift layer width) can be about 3.2 μm, and the width of the groove 33 (the distance between the side walls 33B and 33B in the groove 33) can be about 2 μm. Furthermore, the distance between the oxide layer 34 and the substrate 31 can be about 1 μm, and the thickness of the oxide layer 34 can be about 1 μm to 2 μm. The thickness of the p-type well 35 can be about 1 μm.

In the manufacturing method, referring to FIG. 21, n-type layer 32 can be formed, for example, by vapor phase homoepitaxial growth of SiC using SiH ₄ and C ₃ H ₈ as source gases. The n-type layer 32 contains about 5 × 10 ¹⁶ / cm ³ of nitrogen as an n-type impurity and can have a thickness of about 11 μm. Furthermore, the thermal oxide film 42A can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C. The oxide film 43A can be formed to a thickness of about 1.5 μm by CVD. In addition, for example, Al, boron (B), etc. can be implanted at a depth of about 1 μm and a concentration of about 1 × 10 ¹⁶ / cm ³ by high-temperature ion implantation in which the heating temperature of the substrate 31 is about 500 ° C.

Referring to FIGS. 21 and 22, removal of thermal oxide film 42A, oxide film 43A, and oxide film 43B can be performed by, for example, RIE using CF ₄ gas. Referring to FIG. 22, oxide film 43B can be formed to a thickness of about 1 μm, for example, by CVD. In addition, for example, Al, B, etc. can be implanted at a depth of about 0.3 μm and a concentration of about 1 × 10 ¹⁹ / cm ³ by high temperature ion implantation of about 500 ° C.

Referring to FIG. 23, oxide film 43C can be formed to a thickness of about 1 μm, for example, by CVD. Further, the ion implantation is performed by, for example, high temperature ion implantation at a heating temperature of the substrate 31 of about 500 ° C., and nitrogen (N), phosphorus (P), etc. are implanted at a depth of about 0.3 μm and a concentration of about 1 × 10 ¹⁹ / cm ³ . be able to.

Referring to FIG. 24, activation annealing can be carried out under conditions where the heating temperature is about 1700 ° C. and the heating time is about 20 minutes. Furthermore, the oxide film 43D can be formed to a thickness of about 3 μm by, for example, CVD. The partial removal (pattern formation) of the oxide film 43D can be performed by, for example, RIE using a CF ₄ gas. Furthermore, the groove 33 can be formed by RIE using SF ₆ and O ₂ gas, and the depth of the groove 33 can be about 10 μm.

Referring to FIG. 25, the thermal oxide film by thermal oxidation and thermal oxide film 42B can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C. Furthermore, the oxide film 43E can be formed to a thickness of about 3 μm by, for example, CVD. Further, the thermal oxide film 42B and the oxide film 43E can be reduced by reducing the thickness by about 10 μm by RIE using a CF ₄ gas.

Referring to FIG. 26, the thermal oxide film by thermal oxidation and the thermal oxide film 39A can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C. Further, for example, a polysilicon film for forming the gate electrode 38 can be formed to have a thickness of about 0.3 μm by low pressure chemical vapor deposition (LPCVD). For example, the removal of the polysilicon film for forming the gate electrode 38 can be performed by RIE using a CF ₄ gas.

  Referring to FIG. 27, oxide film 39B can be formed to a thickness of about 0.4 μm by, for example, CVD. Furthermore, referring to FIG. 28, metal film 45 can be formed by evaporating a metal such as Ni or Pt to a thickness of about 0.1 μm. The bonding electrode 46 can be formed by evaporating a metal such as Al to a thickness of about 2 to 5 μm.

  FIG. 29 is a schematic cross-sectional view showing a configuration of a modified example of the MOSFET which is the semiconductor device according to the fourth embodiment of the present invention. With reference to FIG. 29, the structure of the modification in MOSFET which is a semiconductor device of Embodiment 4 of this invention is demonstrated.

  Referring to FIG. 29, MOSFET 30 of the modification of the fourth embodiment and MOSFET 30 shown in FIG. 18 of the above-described fourth embodiment have basically the same configuration. However, the MOSFET 30 of the fourth embodiment has a planar structure, whereas the MOSFET 30 of the modified example is different in that it has a trench structure. Specifically, the gate electrode and the structure adjacent thereto are different. That is, in the modified example, it extends from the position in contact with the groove 33 at the bottom of the n-type region 37 and the p-type region 36 to the n-type region 37 so as to contact the bottom of the p-type region 36 and the n-type region 37. Thus, a p-type well 35 containing a low-concentration p-type impurity is formed. A gate electrode 38 is formed through a gate oxide film 39 so as to face the p-type well 35 and the n-type region 37 in the vicinity of the second surface 32B of the n-type layer 32. That is, the position of the lower surface of the gate electrode 38 is substantially the same as the position of the lower surface of the p-type well 35 in the thickness direction of the n-type layer 32 (the direction from the second surface 32B toward the first surface 32A). Is arranged. In addition, in the thickness direction of the n-type layer 32, the position of the upper surface of the gate electrode 38 is arranged at substantially the same position as the position of the upper surface of the n-type region 37. From a different viewpoint, in the thickness direction of the n-type layer 32, the position of the lower surface of the gate electrode 38 is located closer to the first surface 32A than the position of the upper surface of the n-type region 37. More preferably, in the thickness direction of the n-type layer 32, the position of the lower surface of the gate electrode 38 is the same as the position of the lower surface of the p-type well 35, or is positioned closer to the first surface 32A than the position of the lower surface. Further, the upper surface and the lower surface of the gate electrode 38 are also covered with the gate oxide film 39.

  Further, the groove 33 is in contact with the upper surface of the oxide layer 34, fills the groove 33, and further extends to the second surface 32B that is the upper surface of the n-type layer 32. A source electrode 41 is formed. The source electrode 41 is formed so as to be in contact with the upper surfaces of the p-type region 36 and the n-type region 37, and the sidewall and upper surface of the gate oxide film 39. Note that the source electrode 41 may have a multilayer film structure including the metal film 45 and the bonding electrode 46 as described with reference to FIG.

  Next, with reference to FIG. 29, the operation of MOSFET 30 in the modification of the fourth embodiment will be described. The MOSFET 30 of the modification of the fourth embodiment basically operates in the same manner as the MOSFET 30 of the fourth embodiment. However, there is a difference in the portion where the inversion layer is formed when a positive voltage is applied to the gate electrode. That is, when a positive voltage is applied to the gate electrode 38 of the MOSFET 30 in the modification of the fourth embodiment, an inversion layer is formed in the vicinity of the p-type well 35 in contact with the gate oxide film 39. As a result, the n-type region 37 and the n-type layer 32 are electrically connected, and an electric current flows as the electrons move along the electron flow 47B. At this time, as described above, the MOSFET 30 having the SSB structure can increase the concentration of the n-type impurity in the n-type layer 32 and reduce the thickness of the n-type layer 32, thereby reducing the resistance of the n-type layer 32. be able to. As a result, the MOSFET 30 has a low loss.

  Next, a method for manufacturing the MOSFET in the modification of the fourth embodiment will be described. As shown in FIG. 29, MOSFET 30 in the modification of the fourth embodiment has a configuration in which an SSB structure is applied to a drift layer of a MOSFET having a general trench structure. Therefore, it can be manufactured by combining the method for manufacturing the SSB structure in the method for manufacturing the MOSFET of the fourth embodiment described above and the method for manufacturing the MOSFET having a general trench structure.

(Embodiment 5)
FIG. 30 is a schematic cross-sectional view showing a configuration of a junction field effect transistor (JFET) as a semiconductor device according to the fifth embodiment of the present invention. With reference to FIG. 30, the configuration of a JFET as a semiconductor device according to the fifth embodiment of the present invention will be described.

  Referring to FIG. 30, both JFET 50 in the fifth embodiment and MOSFET 30 in FIG. 18 in the above-described fourth embodiment are field effect transistors having the same SSB structure. Therefore, the substrate 51, the lower n-type layer 52 and the upper n-type layer 62, the groove 53, and the oxide layer 54 as an insulator in FIG. 30 are the substrate 31, the n-type layer 32, the groove 33, and the insulator in FIG. The oxide layer 34 basically has a common configuration. Further, the JFET 50 in FIG. 30 is equivalent to one unit of the repetitive structure of the one-chip JFET element as in the MOSFET 30 in FIG. 18, and can constitute the same JFET element as the MOSFET element 3 described based on FIG. it can.

  However, the JFET of the fifth embodiment is different from the MOSFET of the fourth embodiment in the following points. That is, in the n-type layer including the lower n-type layer 52 formed on the substrate 51 and the upper n-type layer 62 formed on the lower n-type layer 52, the lower n-type layer 52 is opposite to the substrate 51. A p-type region 56 containing a high-concentration p-type impurity is formed at a position facing the side wall 53B of the groove 53 in the vicinity of the boundary surface 52B, which is the surface of. Further, at a position facing the side wall 53B of the groove 53 in the vicinity of the boundary surface 52B, a low concentration p is provided so as to surround the bottom wall of the p-type region 56 and the side wall opposite to the side wall constituting the side wall 53B of the groove 53. A buried p-type layer 55 containing a type impurity is formed. That is, the buried p-type layer 55 is disposed in contact with the side wall 53B of the groove, the bottom surface of the upper n-type layer 62, the bottom surface of the p-type region 56, and the side wall opposite to the side wall 53B of the groove 53.

  An n-type region 57 containing a high-concentration n-type impurity is located at a position facing the side wall 53B of the groove 53 in the vicinity of the second surface 62B, which is the surface opposite to the substrate 51 of the upper n-type layer 62. Is formed. Furthermore, a gate electrode 58 is formed so as to extend from the position facing the buried p-type layer 55 near the second surface 62B to the side opposite to the n-type region 57 (in the direction away from the groove 53). The gate electrode 58 is a semiconductor layer containing a medium concentration p-type impurity. An interelectrode oxide film 59 is formed on the upper n-type layer 62 so as to be in contact with the second surface 62B and to extend in the direction of the n-type region 57 from a position facing the gate electrode 58. ing. The end surface of the interelectrode oxide film 59 on the groove 53 side is located in a region between the n-type region 57 and the gate electrode 58. That is, the upper surface of the gate electrode 58 is completely covered by the interelectrode oxide film 59.

  In addition, the groove 53 contacts the upper surface of the oxide layer 54 and fills the groove 53, and further on the second surface 62 </ b> B and the interelectrode oxide film 59 which are the upper surface of the upper n-type layer 62. A source electrode 61 is formed so as to extend up to. That is, the source electrode 61 is formed so as to be in contact with the upper surface of the n-type region 57, the side wall and the upper surface of the interelectrode oxide film 59.

  Next, the operation of JFET 50 in the fifth embodiment will be described. There are two types of JFET operation, normally-off type and normally-on type, depending on the impurity concentration and thickness of the n-type layer 58 (channel region) sandwiched between the gate electrode 58 and the buried p-type region 55. Here, a normally-on type that is common as a JFET will be described. Referring to FIG. 30, when the voltage of gate electrode 58 is 0 V (the same potential as that of source electrode 61), a region (channel region) sandwiched between gate electrode 58 and buried p-type layer 55 in the upper n-type layer. ) Is not completely depleted, and the source electrode 61 and the lower n-type layer 52 are electrically connected. Therefore, an electric current flows as the electrons move along the electron flow 68A.

  On the other hand, when the gate electrode 58 is applied to a negative voltage with respect to the source electrode 61, depletion of the above-described channel region proceeds, and the source electrode 61 and the lower n-type layer 52 are electrically cut off. It becomes a state. Therefore, the electrons cannot move along the electron flow 68A, and no current flows.

  Here, in the lower n-type layer 52, a depletion layer spreads around the portion in contact with the source electrode 61, and between the source electrode 61 and a drain electrode (not shown) arranged to contact the substrate 51. Are not electrically connected (SSB structure). Therefore, the n-type impurity concentration in the lower n-type layer 52 can be increased, and the thickness of the lower n-type layer 52 can be reduced. As a result, since the resistance of the lower n-type layer 52 can be reduced, the JFET 50 has a low loss.

  Note that the lower n-type layer 52 may further include a p-type region at a position adjacent to the oxide layer 54 as in the Schottky diode of the second embodiment described above. Thereby, the concentration of the electric field in the vicinity of the interface between the oxide layer 54 and the lower n-type layer 52 can be relaxed. As a result, the reliability regarding the breakdown voltage of the JFET 50 of the fifth embodiment can be further improved.

  Similarly to the Schottky diode of the third embodiment described above, in the lower n-type layer 52, the n-type impurity concentration is gradually increased from the first surface 52A side toward the boundary surface 52B side. Alternatively, in the region between the end of the source electrode 61 on the substrate 51 side and the first surface 52A, the concentration of the n-type impurity in the surface layer on the boundary surface 52B side (in the range of about 2 μm from the boundary surface 52B). A region having a relatively lower n-type impurity concentration may be formed. Thereby, since the concentration of the n-type impurity is low in a region having a large influence on the leakage current, the leakage current is reduced. On the other hand, since the concentration of the n-type impurity is high in a region where the influence on the leakage current is relatively small, the resistance of the lower n-type layer 52 can be reduced.

  Next, as an embodiment of a method for manufacturing a semiconductor device of the present invention, a method for manufacturing a JFET of Embodiment 5 will be described with reference to the drawings. FIG. 31 is a diagram schematically showing the manufacturing process of the JFET of the fifth embodiment. 32 to 39 are schematic cross-sectional views for explaining the method of manufacturing the JFET of the fifth embodiment. A method for manufacturing the JFET of the fifth embodiment will be described with reference to FIGS.

  As shown in FIG. 31, after a substrate preparation step, which is a step of preparing a substrate made of a wide band gap semiconductor, is first performed, a lower n-type layer forming step for forming a lower n-type layer on the substrate is performed. . Specifically, as in the n-type layer forming step of the fourth embodiment, as shown in FIG. 32, a lower n-type layer 52 is formed on a substrate 51 made of a wide band gap semiconductor prepared in the substrate preparing step. It is formed.

  Next, as shown in FIG. 31, a buried p-type layer forming step is performed in which a buried p-type layer is formed in the lower n-type layer formed in the lower n-type layer forming step. Specifically, as in the p-type well formation step of the fourth embodiment, as shown in FIG. 32, for example, a thermal oxide film 63A and an oxide film 64A are formed on the surface of lower n-type layer 52 opposite to substrate 51. Is formed. Then, a resist film having a predetermined pattern is formed on oxide film 64A using, for example, photolithography. The thermal oxide film 63A and the oxide film 64A having an opening pattern as shown in FIG. 32 on the lower n-type layer 52 are obtained by partially removing the thermal oxide film 63A and the oxide film 64A by RIE using the resist film as a mask. A mask layer made of 64A is formed. By performing ion implantation using this mask layer as a mask, a buried p-type layer 55 is formed in the lower n-type layer 52.

  Next, as shown in FIG. 31, a p-type region forming step for forming a p-type region containing a high-concentration p-type impurity in the buried p-type layer formed in the buried p-type layer forming step is performed. Specifically, as in the p-type region forming step of the fourth embodiment, as shown in FIG. 33, for example, after oxide film 64A and thermal oxide film 63A are all removed, lower n-type layer 52 is formed by CVD. An oxide film 64B is formed on the surface (upper surface) opposite to the surface facing substrate 51. Then, a resist film having a predetermined pattern is formed on oxide film 64B using, for example, photolithography. By partially removing the thermal oxide film 64 by RIE using the resist film as a mask, a mask layer made of an oxide film 64B having an opening pattern as shown in FIG. 33 is formed on the buried p-type layer 55. By performing ion implantation using this mask layer as a mask, a p-type region 56 is formed in the buried p-type layer 55.

  Next, as shown in FIG. 31, an upper n-type layer forming step is performed in which an upper n-type layer is formed on the lower n-type layer 52 in which the buried p-type layer 55 and the p-type region 56 are formed. Specifically, as shown in FIG. 34, for example, after all oxide film 64B is removed, the upper surface of lower n-type layer 52 is sacrificial oxidized by thermal oxidation. Thereafter, the oxide film formed by the sacrificial oxidation is removed by etching. Then, upper n-type layer 62 (for example, a silicon carbide layer containing n-type impurities) is formed on lower n-type layer 52 by, for example, vapor phase epitaxial growth.

  Next, as shown in FIG. 31, an n-type region forming step for forming an n-type region 57 (see FIG. 35) containing high-concentration n-type impurities in the upper n-type layer 62 is performed. Specifically, as shown in FIG. 34, a thermal oxide film 63B is formed on upper n-type layer 62 and an oxide film 64C is formed on thermal oxide film 63B, for example, by thermal oxidation and CVD. Then, as shown in FIG. 35, for example, a resist film having an opening is formed on oxide film 64C by photolithography. Using this resist film as a mask, oxide film 64C and thermal oxide film 63B are partially removed by RIE, so that a predetermined opening pattern is formed on upper n-type layer 62, and thermal oxide film 63B and oxide film 63B are oxidized. A mask layer made of the film 64C is formed. By performing ion implantation using this mask layer as a mask, an n-type region 57 is formed in the upper n-type layer 62.

  Next, as shown in FIG. 31, a gate electrode formation step is performed in which a gate electrode made of a p-type semiconductor is formed in the upper n-type layer. Specifically, as shown in FIG. 36, for example, after oxide film 64C and thermal oxide film 63B are all removed, thermal oxide film 63C is formed on upper n-type layer 62 by thermal oxidation and CVD, and the heat An oxide film 64D is formed on oxide film 63C. Then, for example, a resist film having an opening is formed on oxide film 64D by photolithography. Using this resist film as a mask, oxide film 64D and thermal oxide film 63C are partially removed by RIE, whereby a mask layer composed of thermal oxide film 63C and oxide film 64D is formed on upper n-type layer 62. The This mask layer is formed so as to cover the n-type region 57. By performing ion implantation using this mask layer as a mask, gate electrode 58 containing a p-type impurity is formed in upper n-type layer 62.

  Next, as shown in FIG. 31, the upper n-type layer 62 and the lower n-type layer 52 are separated from the second surface 62B of the upper n-type layer 62, which is the surface opposite to the surface on the substrate 51 side. A groove forming step is performed in which a groove 53 extending toward the first surface 52A of the mold layer 52 is formed by etching. Specifically, as shown in FIG. 37, activation annealing is performed after all oxide film 64D and thermal oxide film 63C have been removed, for example, in the same manner as in the groove forming step of the fourth embodiment. Thereafter, an oxide film 64E is formed by CVD. Then, a resist film having a predetermined pattern is formed on oxide film 64E using, for example, photolithography. By partially removing the oxide film 64E by RIE using the resist film as a mask, a mask layer made of the oxide film 64E is formed. Further, a groove 53 is formed in the n-type layer composed of the upper n-type layer 62 and the lower n-type layer 52 by RIE using this mask layer as a mask.

  Next, as shown in FIG. 31, an insulator forming step for forming an insulator at the bottom of the groove is performed. The insulator forming step is performed in the order of the oxide layer forming step and the etching step. Specifically, as shown in FIG. 38, after all the oxide films including oxide film 64E are removed by etching, the upper n-type layer 62 is formed on the inner peripheral surface of groove 53 by, for example, thermal oxidation and CVD. The oxide layer forming step is completed by forming the thermal oxide film 63E extending to the region on the formed gate electrode 58 and the oxide film 64F on the thermal oxide film 63E. Further, the thermal oxide film 63E and the oxide film 64F are reduced by, for example, RIE, and the thermal oxide film 63E and the oxide film 64F other than the thermal oxide film 63E and the oxide film 64F near the bottom wall 53A of the trench 53 are removed. The etching process is completed. The thermal oxide film 63E and the oxide film 64F remaining in the vicinity of the bottom wall 53A of the groove 53 are the oxide layer 54 as an insulator.

  Next, as shown in FIG. 31, an interelectrode oxide film forming step for forming an interelectrode oxide film is performed. Specifically, as shown in FIG. 38, a thermal oxide film 63F is formed so as to cover second surface 62B of upper n-type layer 62 by, for example, thermal oxidation and CVD, and oxide film 64G is formed on thermal oxide film 63F. Each is formed. Then, for example, a resist film 65 having an opening is formed on the oxide film 64G by photolithography. Using this resist film 65 as a mask, oxide film 64G and thermal oxide film 63F are partially removed by RIE. The remaining thermal oxide film 63F and oxide film 64G are interelectrode oxide films 59.

  Next, as shown in FIG. 31, as in the fourth embodiment, the upper and lower n-type layers 62 and 52 are in contact with the side wall 53B of the groove 53 where the oxide layer 54 as an insulator is formed. A source electrode forming process including a metal film forming process for forming a metal film 66 capable of being in Schottky contact with each other is performed. Specifically, as shown in FIG. 38, for example, after the resist film 65 is removed, Ni that can make Schottky contact with the lower n-type layer 52 and the upper n-type layer 62 as n-type layers as shown in FIG. A metal film forming step for forming the metal film 66 by depositing a metal such as is performed. As shown in FIG. 39, the lower n-type layer 52 and the upper n-type layer 62 as n-type layers and the metal film 66 are Schottky connected, and the p-type region 56, the n-type region 57, and the metal film 66 are electrically connected. Connect. Thereafter, a bonding electrode forming step is performed in which a bonding electrode 67 is formed on the metal film 66 by depositing a metal such as Al that is easy to bond. The metal film 66 and the bonding electrode 67 become the source electrode 61. The source electrode 61 may be composed of only the metal film 66 or may be composed of the metal film 66 and a bonding electrode 67 composed of one layer or a plurality of layers.

  The JFET 50 of the fifth embodiment can be manufactured by the above manufacturing method. Since this manufacturing method does not include difficult steps, the JFET 50 of the fifth embodiment can be easily manufactured according to this manufacturing method.

Embodiment 5 can be implemented, for example, under the following conditions. Referring to FIG. 30, n ⁺ substrate similar to that in the fourth embodiment can be used as substrate 51. Further, the lower n-type layer 52 and the upper n-type layer 62 as the n-type layer can be basically configured similarly to the n-type layer of the fourth embodiment. However, the distance from the first surface 52A to the boundary surface 52B can be about 11 μm, and the distance from the boundary surface 52B to the second surface 62B can be about 1 μm. The upper n-type layer 62 can contain about 2 × 10 ¹⁶ / cm ³ of nitrogen as an n-type impurity. Furthermore, the distance between the oxide layer 54 and the substrate 51 can be about 1 μm, and the thickness of the oxide layer 54 can be about 1 μm to 2 μm. The thickness of the buried p-type layer 55 can be about 1 μm.

  In the manufacturing method, referring to FIG. 32, lower n-type layer 52 and buried p-type layer 55 can be formed in the same manner as the n-type layer and p-type well of the fourth embodiment. Further, referring to FIG. 33, p type region 56 can be formed in the same manner as the p type region of the fourth embodiment.

Referring to FIG. 34, upper n-type layer 62 can be formed basically in the same manner as lower n-type layer 52, but the thickness is about 1 μm and the concentration of nitrogen as an n-type impurity is 2 × 10. It can be set to about ¹⁶ / cm ³ .

  Referring to FIG. 35, n-type region 57 can be formed basically in the same manner as the n-type region of the fourth embodiment, but the thickness can be about 0.5 μm.

Referring to FIG. 36, thermal oxide film 63C can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C. The oxide film 64D can be formed to a thickness of about 1 μm by CVD. Furthermore, the removal of the thermal oxide film 63C and the oxide film 64D can be performed by, for example, RIE using a CF ₄ gas. The ion implantation by the high-temperature ion implantation heating temperature of about 500 ° C. of the substrate 51 for example, Al, etc. the depth 0.3μm about B, it is possible to inject a concentration of about 1 × ¹⁰ 18 / cm ^3.

Referring to FIGS. 37 and 38, formation of groove 53 and oxide layer 54 can be performed in the same manner as the formation of the groove and insulator in the fourth embodiment. Furthermore, referring to FIG. 38, in forming interelectrode oxide film 59, thermal oxide film 63F can be formed to a thickness of about 50 nm by thermal oxidation at a heating temperature of about 1200 ° C. The oxide film 64G can be formed to a thickness of about 0.4 μm by CVD. Further, the removal of the thermal oxide film 63F and the oxide film 64G can be performed by, for example, RIE using a CF ₄ gas. Referring to FIG. 39, source electrode 61 can be formed in the same manner as the source electrode of the fourth embodiment.

  In the above, the semiconductor device including the substrate made of the wide band gap semiconductor and the n-type layer and the manufacturing method thereof have been described. However, the present invention is not limited to this, and a general semiconductor such as Si is used. The present invention can also be applied to a semiconductor device provided with a substrate and an n-type layer and a manufacturing method thereof.

  The embodiment disclosed this time is to be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

  The semiconductor device and the manufacturing method thereof according to the present invention can be particularly advantageously applied to a semiconductor device including a substrate made of a semiconductor and a manufacturing method thereof.

  1 Schottky diode element, 3 MOSFET element, 10 Schottky diode, 11, 31, 51 substrate, 12, 32 n-type layer, 12A, 32A, 52A first surface, 12B, 32B, 62B second surface, 12E First n-type layer, 12F Second n-type layer, 13, 33, 53 groove, 13A, 33A, 53A Bottom wall, 13B, 33B, 53B Side wall, 14, 34, 54 Oxide layer, 15 Metal film, 16 Anode electrode, 17A-17C, 39A, 42A, 42B, 63A-63F Thermal oxide film, 18A, 18B, 39B, 43A-43E, 64A-64G oxide film, 19, 36, 56 p-type region, 21, 44A, 44B, 65 Resist film, 22 Schottky metal film, 23, 46, 67 Bonding electrode, 30 MOSFET, 35 p-type well, 37, 57 n-type region, 38 polysilicon film (gate electrode), 39 gate oxide film, 41, 61 source electrode, 45, 66 metal film, 47A, 47B, 68A electron flow, 52 lower n-type layer, 52B boundary Surface, 55 buried p-type layer, 58 gate electrode, 59 interelectrode oxide film, 62 upper n-type layer.

Claims (11)

A semiconductor substrate;
N having a groove formed on the substrate and extending from the second surface, which is the surface opposite to the first surface, which is the surface on the substrate side, toward the first surface; Mold layer,
An insulator disposed at the bottom of the groove;
A semiconductor device comprising: the n-type layer and a metal film capable of Schottky contact formed so as to be in contact with a side wall of the groove.   The semiconductor device according to claim 1, further comprising a p-type region formed at a position adjacent to the insulator.   3. The semiconductor device according to claim 1, wherein in the n-type layer, the concentration of an n-type impurity is gradually increased from the first surface side toward the second surface side.   In the n-type layer, the region between the end of the metal film on the substrate side and the first surface has an impurity concentration in the surface layer on the second surface side for the n-type conductivity type impurity. The semiconductor device according to claim 1, wherein a region having a relatively lower impurity concentration is formed.   The semiconductor device according to claim 1, wherein the substrate and the n-type layer are made of a wide band gap semiconductor. A step of preparing a semiconductor substrate;
An n-type layer forming step of forming an n-type layer on the substrate;
A groove forming step of forming, in the n-type layer, a groove extending from the second surface, which is a surface opposite to the first surface, which is the surface on the substrate side, toward the first surface by etching;
Forming an insulator at the bottom of the groove;
Forming a metal film capable of being in Schottky contact with the n-type layer so as to be in contact with a side wall of the groove in which the insulator is formed. The n-type layer forming step includes
Forming a first n-type layer on the substrate;
Forming a mask layer having an opening pattern on a surface of the first n-type layer opposite to the substrate side;
Forming a p-type region in the first n-type layer by performing ion implantation on the first n-type layer using the mask layer as a mask;
Removing the mask layer;
Forming a second n-type layer on the first n-type layer from which the mask layer has been removed,
The method of manufacturing a semiconductor device according to claim 6, wherein the groove formed in the groove forming step is formed so as to penetrate the second n-type layer and reach the p-type region.   The concentration of impurities whose conductivity type in the n-type layer formed in the n-type layer forming step is n-type is gradually increased from the first surface side toward the second surface side. The method for manufacturing a semiconductor device according to claim 6, wherein an n-type layer forming step is performed.   In the n-type layer formed in the n-type layer forming step, the region between the end of the metal film on the substrate side and the first surface has an n-type conductivity type impurity. 8. The manufacturing of a semiconductor device according to claim 6, wherein the n-type layer forming step is performed so that a region having an impurity concentration relatively lower than an impurity concentration in the surface layer on the surface side of the second surface is formed. Method.   The concentration of the impurity whose conductivity type is n-type in the first n-type layer is relatively lower than the concentration of the impurity whose conductivity type is n-type in the second n-type layer. The method for manufacturing a semiconductor device according to claim 7, wherein a step of forming a first n-type layer and a step of forming the second n-type layer are performed. In the step of preparing the substrate made of a semiconductor, a substrate made of a wide band gap semiconductor is prepared,
The method for manufacturing a semiconductor device according to claim 6, wherein an n-type layer made of a wide band gap semiconductor is formed in the n-type layer forming step.

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