JP2023101772A - Semiconductor device and manufacturing method of semiconductor device - Google Patents

Abstract

To enable increase of proof pressure by simple structure and furthermore to enable reduction of length of a termination structure portion.SOLUTION: A p+ base layer 3 is provided between a top-side surface of a semiconductor base and a n- type silicon carbide epitaxial layer 1 in an outer periphery of an active portion 102 in such a manner that the p+ base layer 3 comes in contact with a terminal construction portion 101. Inter-layer insulation films 21 and 5 are overlapped with the top-side surface of the semiconductor base. The terminal construction portion 101 is arranged outside the active portion 102, and includes first and second JTE regions 6 and 7, and a n+ type channel stopper region 4. Each of first and second JTE regions 6 and 7 is continuously provided in the p+ base layer 3, and forms a p-n junction with the n- type silicon carbide epitaxial layer 1. A distal end outside the second JTE region 7 is positioned at a depth separated from the top-side surface of the semiconductor base and does not come in contact with the inter-layer insulation film 5, and a distance between the distal end in a direction parallel to the top-side surface of the semiconductor base and the n+ type channel stopper region 4 is longer than a distance between the distal end in a depth direction and the inter-layer insulation film 5.SELECTED DRAWING: Figure 1

Description

The present invention relates to a semiconductor device such as a wide bandgap semiconductor vertical MOSFET and a method for manufacturing the semiconductor device.

Conventionally, silicon (Si) has been used as a constituent material of power semiconductor devices that control high voltages and large currents. There are multiple types of power semiconductor devices, such as bipolar transistors, IGBTs (Insulated Gate Bipolar Transistors), and MOSFETs (Metal Oxide Semiconductor Field Effect Transistors), which are used according to the application.

For example, bipolar transistors and IGBTs have higher current densities than MOSFETs and can handle large currents, but cannot be switched at high speed. Specifically, bipolar transistors are limited to use at a switching frequency of about several kHz, and IGBTs are limited to use at a switching frequency of about several tens of kHz. On the other hand, a power MOSFET has a lower current density than a bipolar transistor or an IGBT, making it difficult to increase the current, but it is capable of high-speed switching operation up to several MHz.

There is a strong demand in the market for power semiconductor devices that combine large current and high speed, and efforts have been made to improve IGBTs and power MOSFETs. From the viewpoint of power semiconductor devices, semiconductor materials to replace silicon are being investigated, and silicon carbide (SiC) is attracting attention as a semiconductor material capable of producing (manufacturing) next-generation power semiconductor devices with excellent low on-voltage, high-speed characteristics, and high-temperature characteristics.

Silicon carbide is a chemically very stable semiconductor material, has a wide bandgap of 3 eV, and can be extremely stably used as a semiconductor even at high temperatures. In addition, since silicon carbide has a maximum electric field strength that is one order of magnitude higher than that of silicon, silicon carbide is expected as a semiconductor material capable of sufficiently reducing the on-resistance. Such features of silicon carbide also apply to, for example, gallium nitride (GaN), which is a semiconductor having a wider bandgap than silicon (hereinafter referred to as a wide bandgap semiconductor) other than silicon carbide. Therefore, by using a wide bandgap semiconductor, it is possible to reduce the resistance and increase the withstand voltage of the semiconductor device.

In a power semiconductor device using a wide bandgap semiconductor, it is necessary to provide a breakdown voltage structure in the termination structure portion at the periphery of the element in order to maintain the breakdown voltage in the off state. As a typical example, there is a method of forming a junction termination structure (JTE: Junction Termination Extension) in the mesa portion (see, for example, Non-Patent Documents 1 and 2 below). It should be noted that the smaller the lateral width of the termination structure region, the smaller the element area, which is preferable.

Ranbir Singh, et al. , "SiC Power Schottky and PiN Diodes", IEEE Transactions on Electron Devices, Vol. 49, No. 4, APRIL, 2002. Dai Okamoto, et al. , "13-kV, 20-A 4H-SiC PiN Diodes for Power System Applications", Materials Science For μm, Vol. 778-780, pp 855-858, 2014

FIG. 17 is a cross-sectional view showing the structure of a termination structure of a conventional semiconductor device. In the conventional termination structure 101, when patterning is performed in a region having a different height from the active region (active portion) 102, such as the mesa portion, the depth of focus of photolithography is different, which increases process difficulty. For this reason, it is preferable that the termination structure portion 101 has the same height as the active portion 102 . The semiconductor device of FIG. 17 has a p ⁺ -type base layer 3, an n ⁺ -type channel stopper region 4, an interlayer insulating film 5, a first JTE region (p-type layer) 6, and a second JTE region (p ⁻ -type layer) 7 formed on the front surface side of an n ⁻ -type silicon carbide epitaxial layer 1 formed on an n ⁺ -type silicon carbide substrate 2.

FIG. 18 is a cross-sectional view showing the configuration of a termination structure portion of a semiconductor device in which a conventional mesa portion is not formed. If the termination structure portion 101 and the active portion 102 are at the same height, electric field concentration occurs at the corner portion of the p ⁺ -type base layer 3 formed at the end of the active portion 102, resulting in a decrease in breakdown voltage.

FIG. 19 is a diagram showing breakdown voltage calculation results by simulation of a conventional termination structure. 19A shows the breakdown voltage of the termination structure 101 of FIG. 17 for the 1200V breakdown voltage class, and FIG. 19B shows the breakdown voltage of the termination structure 101 of FIG. 18 for the 1200V breakdown class. It can be seen that the breakdown voltage is lower in the structure of FIG. 18 than in the structure of FIG.

Also, for the purpose of shortening the termination structure portion 101, it is preferable to gradually provide a gradation of the dose amount of the p-type layers 6 and 7 in the vertical direction so that the concentration decreases from the edge of the active portion 102 toward the edge of the device. However, as an example of realizing a horizontal gradation in the conventional termination structure 101, if a spatial modulation structure is used, process variations are likely to occur due to patterning accuracy, and a problem arises that process difficulty increases.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device and a method of manufacturing a semiconductor device that can improve the withstand voltage with a simple structure and shorten the length of the termination structure in order to solve the above-described problems of the prior art.

In order to solve the above-described problems and achieve the objects of the present invention, a semiconductor device according to the present invention includes an active region through which a current flows, a termination structure disposed outside the active region and having a breakdown voltage structure formed thereon, wherein each semiconductor layer is formed on a semiconductor substrate, a drift layer of a first conductivity type as the semiconductor layer, and a second conductive drift layer as the semiconductor layer provided between the front surface of the semiconductor substrate and the drift layer inside the termination structure and in contact with the termination structure. and an interlayer insulating film overlying the front surface of the semiconductor substrate from the active region to the termination structure. The termination structure portion includes a second conductivity type first semiconductor layer continuous from the base layer, a first conductivity type second semiconductor layer continuous to the drift layer and forming a pn junction in contact with the first semiconductor layer, and a channel stopper layer provided outside the first semiconductor layer and separated from the first semiconductor layer. The outer tip of the first semiconductor layer is located at a depth away from the front surface of the semiconductor substrate and does not contact the interlayer insulating film, and the distance between the tip and the channel stopper layer in the direction parallel to the front surface of the semiconductor substrate is longer than the distance between the tip and the interlayer insulating film in the depth direction.

A method of manufacturing a semiconductor device according to the present invention includes an active region through which a current flows, a termination structure disposed outside the active region and having a breakdown voltage structure formed thereon, each semiconductor layer being formed on a semiconductor substrate, and a method of manufacturing a semiconductor device having a MOS gate structure including a trench in which a gate electrode is embedded in the active region, wherein the step of forming a drift layer of a first conductivity type as the semiconductor layer is performed. A step of simultaneously forming, on the drift layer, at least part of a base layer of a second conductivity type as the semiconductor layer disposed between the MOS gate structure and the termination structure and in contact with the termination structure, and a trench bottom semiconductor layer of the second conductivity type as the semiconductor layer in contact with the bottom of the trench. forming a second conductivity type channel region of the MOS gate structure in the active region; A step of forming a first semiconductor layer of a second conductivity type as the semiconductor layer on the drift layer in the termination structure is performed. A step of forming a high-concentration semiconductor layer of a second conductivity type as the semiconductor layer having an impurity concentration higher than that of the channel region and electrically connected to the base layer is performed on the channel region. The step of forming the high-concentration semiconductor layer is performed after the step of forming the first semiconductor layer, and the position of the surface of the first semiconductor layer is set deeper in the semiconductor base than the position of the surface of the high-concentration semiconductor layer in the depth direction.

According to the semiconductor device and the method for manufacturing a semiconductor device according to the present invention, it is possible to improve the withstand voltage of the termination structure without the mesa and shorten the lateral length of the termination structure.

FIG. 1 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the first embodiment. FIG. 2 is a diagram showing a withstand voltage calculation result by simulation of the termination structure according to the first embodiment. FIG. 3 is a cross-sectional view showing a structural example of an active portion of the semiconductor device according to the first embodiment. 4A to 4D are cross-sectional views showing the manufacturing process of the termination structure of the semiconductor device according to the first embodiment. (Part 1) 5A to 5D are cross-sectional views showing the manufacturing process of the termination structure of the semiconductor device according to the first embodiment. (Part 2) 6A to 6D are cross-sectional views showing the manufacturing process of the termination structure of the semiconductor device according to the first embodiment. (Part 3) 7A to 7D are cross-sectional views showing the manufacturing process of the termination structure of the semiconductor device according to the first embodiment. (Part 4) FIG. 8 is a cross-sectional view showing a manufacturing process of the termination structure of the semiconductor device according to the first embodiment. (Part 5) FIG. 9 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the second embodiment. FIG. 10 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the third embodiment. FIG. 11 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the fourth embodiment. FIG. 12 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the fifth embodiment. FIG. 13 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the sixth embodiment. FIG. 14 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the seventh embodiment. FIG. 15 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the eighth embodiment. FIG. 16 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the ninth embodiment. FIG. 17 is a cross-sectional view showing the structure of a termination structure of a conventional semiconductor device. FIG. 18 is a cross-sectional view showing the configuration of a termination structure portion of a semiconductor device in which a conventional mesa portion is not formed. FIG. 19 is a diagram showing breakdown voltage calculation results by simulation of a conventional termination structure.

Preferred embodiments of a semiconductor device and a method of manufacturing a semiconductor device according to the present invention will be described in detail below with reference to the accompanying drawings. In this specification and the accompanying drawings, layers and regions prefixed with n or p mean that electrons or holes are majority carriers, respectively. Also, + and - attached to n and p mean that the impurity concentration is higher and lower than that of the layer or region not attached, respectively. When the notations of n and p including + and - are the same, it indicates that the concentrations are close, and the concentrations are not necessarily the same. In the following description of the embodiments and accompanying drawings, the same configurations are denoted by the same reference numerals, and overlapping descriptions are omitted. Also, in this specification, in the notation of the Miller index, "-" means a bar attached to the index immediately after it, and adding "-" before the index indicates a negative index.

(Embodiment 1)
The semiconductor device according to this embodiment is configured using a wide bandgap semiconductor. In Embodiment 1, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. Also, an example in which the first conductivity type is n-type and the second conductivity type is p-type will be described.

FIG. 1 is a cross-sectional view showing the configuration of the termination structure portion of the silicon carbide semiconductor device according to the first embodiment. An n ⁻ -type silicon carbide epitaxial layer (wide bandgap semiconductor deposited layer) 1 is deposited on a first main surface, eg, the (0001) plane (Si plane) of an n ⁺ -type silicon carbide substrate (wide bandgap semiconductor substrate) 2 .

The n ⁺ -type silicon carbide substrate 2 is, for example, a silicon carbide single crystal substrate doped with nitrogen (N). The n ⁻ -type silicon carbide epitaxial layer 1 is a low-concentration n-type drift layer (drift layer) doped with, for example, nitrogen at an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 2 . Hereinafter, n ⁺ -type silicon carbide substrate 2 alone, or n ⁺ -type silicon carbide substrate 2 and n ^- -type silicon carbide epitaxial layer 1 are collectively referred to as a silicon carbide semiconductor substrate.

A p ⁺ -type base layer (p ⁺ layer) 3 is formed in an active region (active portion) 102 on the front surface side of the n − -type silicon carbide epitaxial layer 1, a first JTE region 6 and a second JTE region 7 (p-type layer 6, p ^{− -type} layer 7: first semiconductor layer) in contact with the p ⁺ -type base layer 3 are formed in the termination structure portion 101, and an n ⁺ -type channel stopper region (channel stopper layer) 4 is formed at the end of the termination structure portion 101. The height of the lower portion of the p ⁺ layer 3 at the end of the active portion 102 and the lower portions of the p-type layer 6 and p ⁻ -type layer 7, which are the JTE regions, are arranged within ±0.3 μm. P-type layer 6 and p ⁻ -type layer 7 have bottoms at the same position as p ⁺ layer 3 when viewed in the height (depth) direction of p ⁺ layer 3 and are lower than p ⁺ layer 3 .

FIG. 2 is a diagram showing a withstand voltage calculation result by simulation of the termination structure according to the first embodiment. According to the structure of the termination structure portion 101 shown in FIG. 1, the electric field concentrated on the corner portion of the p ⁺ layer 3 at the end of the active portion 102 can be relaxed, and the withstand voltage can be improved. It is preferable that the p-type layer 6 which is the JTE region has a higher impurity concentration than the p ⁻ -type layer 7 .

FIG. 3 is a cross-sectional view showing a structural example of an active portion of the semiconductor device according to the first embodiment. A dense n ^- layer (first n-type CSL region) 15a is formed on the first main surface side of the n − -type silicon carbide epitaxial layer 1, and the dense n-type region 15a is doped with nitrogen, for example, at an impurity concentration lower than that of the n ⁺ -type silicon carbide substrate 2 and higher than that of the n-type silicon carbide epitaxial layer 1.

A back surface electrode is provided on the surface of n ⁺ -type silicon carbide substrate 2 opposite to n ⁻ -type silicon carbide epitaxial layer 1 (the back surface of the silicon carbide semiconductor substrate) to form a drain electrode. An n-layer 15 a is formed so as not to be formed in the termination structure portion 101 by patterning the silicon carbide substrate surface by photolithography and ion-implanting nitrogen.

A plurality of p ⁺ layers (trench bottom semiconductor layers) 3a are formed in the n layer 15a portion by patterning and aluminum ion implantation. The p ⁺ layer 3a preferably has an activation impurity concentration of about 1.0×10 ¹⁷ to 1.0×10 ¹⁹ cm ⁻³ and a depth of about 0.1 to 1.5 μm. Then, silicon carbide having a concentration equivalent to that of the n ⁻ layer 1 is deposited to a thickness of 0.1 to 1.5 μm by nitrogen-added epitaxial growth to form the region II.

A second n-type CSL region (n-layer) 15b is formed on the n-layer 15a so as not to be formed in the termination structure portion 101 by patterning by photolithography and ion-implanting nitrogen. At this time, the n-layer 15b is formed so as not to form a region with the same concentration as the n ⁻ -layer 1 .

Further, p ⁺ layer 3b is formed so as to be electrically connected to p ⁺ layer 3a by patterning and aluminum ion implantation. The p ⁺ layer 3b preferably has an activation impurity concentration of about 1.0×10 ¹⁷ to 1.0×10 ¹⁹ cm ⁻³ and a depth of about 0.2 to 2.0 μm. A region III is formed by depositing silicon carbide to a thickness of 0.1 to 1.5 μm by epitaxial growth with addition of nitrogen or aluminum.

A p-type channel region (p layer) 16 is formed by patterning by photolithography and ion implantation of aluminum so as not to be formed in the termination structure portion 101 . The active impurity concentration of the p-layer 16 is preferably about 1.0×10 ¹⁶ to 1.0×10 ¹⁹ cm ⁻³ and the depth is preferably about 0.3 to 1.5 μm. An n-type source region (n ⁺ layer) 17 is formed by patterning by photolithography and ion implantation of phosphorus, arsenic, or nitrogen. The n ⁺ layer 17 preferably has an activation impurity concentration of about 1.0×10 ¹⁸ to 1.0×10 ²⁰ cm ^-3 and a depth of about 0.05 to 0.5 μm.

A p-type region (p ⁺ layer: high-concentration semiconductor layer) 18 is formed so as to be electrically connected to the p ⁺ layer 3b by patterning by photolithography and ion-implanting aluminum. The p ⁺ layer 18 preferably has an activation impurity concentration of about 1.0×10 ¹⁷ to 1.0×10 ²⁰ cm ^-3 and a depth of about 0.2 to 2.0 μm.

After depositing a carbon film of about 0.01 to 5.0 μm, annealing is performed at 1500° C. to 1900° C. to activate the implanted impurity ions. By patterning by photolithography and dry etching, trench 19 is formed so as not to penetrate p ⁺ layer 3a. The trench 19 preferably has a width of about 0.1 to 1.5 μm and a depth of about 0.2 to 2.0 μm. A polysilicon insulating film is deposited so as to cover the inside of the trench 19, and the insulating film is formed of a HTO (High Temperature Oxide) film with a thickness of 30 nm to 200 nm, which is deposited at a high temperature of about 600 to 900° C. by low pressure CVD, for example.

After depositing an insulating film to fill the trench 19, the gate electrode 20 is formed by etching so as to leave at least ⅔ of the depth of polysilicon in the trench 19. As shown in FIG. After depositing an oxide film to a thickness of about 0.1 to 3.0 μm, an interlayer insulating film 21 is formed by patterning and etching.

Also, one or more of titanium, nickel, tungsten, and aluminum is deposited by vapor deposition or sputtering to a total thickness of about 0.5 to 8.0 μm, and the source electrode 22 is formed by patterning and etching. As described above, the active portion shown in the first embodiment is configured.

Although only three trench structures are shown in FIG. 3, more trench MOS structures may be arranged in parallel. Note that the p ⁺ layer 18 in the active portion 102 or the source electrode 22 is in contact with the semiconductor layer 3 of the termination structure portion 101 .

Although p ⁺ layer 3 of termination structure portion 101 of the silicon carbide semiconductor device shown in FIG. 1 is assumed to be the same as p ⁺ layer 3a of active portion 102 shown in FIG. 3, they may be different.

4 to 8 are cross-sectional views showing manufacturing steps of the termination structure of the semiconductor device according to the first embodiment. The manufacturing process of the termination structure will be described in order using these figures.

First, as shown in FIG. 4, an n ⁻ layer 1a (drift layer, second semiconductor layer) is formed by an epitaxial growth method in which nitrogen is added to an n ⁺ type silicon carbide substrate 2 . The n ^- layer 1a preferably has a concentration of about 1.0×10 ¹⁴ to 1.0×10 ¹⁷ cm ^-3 and a thickness of about 4 μm to 100 μm. A back surface electrode is provided on the surface on the n ⁺ -type silicon carbide substrate 2 side (the back surface of the silicon carbide semiconductor substrate) to constitute a drain electrode.

Next, as shown in FIG. 5, p ⁺ -type base layer (p ⁺ layer) 3a is formed by patterning and ion-implanting aluminum on the first main surface side of the silicon carbide semiconductor substrate. The p ⁺ layer 3a preferably has an activation impurity concentration of about 1.0×10 ¹⁷ to 1.0×10 ¹⁹ cm ⁻³ and a depth of about 0.1 to 1.5 μm. Further, the p ⁻ layer 6 is formed by patterning and ion-implanting aluminum at the side portion of the p ⁺ layer 3a. The p ^- layer 6 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm. Further, the p ⁻ layer 7 is formed so that the activated impurity concentration is lower than that of the p ⁻ layer 6 by patterning and ion-implanting aluminum into the side portion of the p ⁻ layer 6 . The p ^- layer 7 preferably has an activation impurity concentration of about 8.0×10 ¹⁵ to 8.0×10 ¹⁷ cm ^-3 and a depth of about 0.1 to 1.5 μm.

Next, as shown in FIG. 6, a region II (second semiconductor layer) is formed by forming an n ⁻ layer 1b on the front surface side of the silicon carbide substrate 1 by nitrogen-added epitaxial growth. The n ⁻ layer 1b preferably has a concentration of about 1.0×10 ¹⁴ to 1.0×10 ¹⁷ cm ⁻³ , the same concentration as the n ⁻ layer 1a, and a thickness of about 0.1 μm to 1.5 μm. Then, p ⁺ layer 3b is formed on p ⁺ layer 3a by patterning and aluminum ion implantation so as to be electrically connected to p ⁺ layer 3a. The p ⁺ layer 3b preferably has an activation impurity concentration of about 1.0×10 ¹⁷ to 1.0×10 ¹⁹ cm ⁻³ and a depth of about 0.2 to 2.0 μm.

Next, as shown in FIG. 7, a region III is formed by forming n ⁻ layer 1c on the front surface side of silicon carbide substrate 1 by nitrogen-added epitaxial growth. The concentration of the n ⁻ layer 1c is about 1.0×10 ¹⁴ to 1.0×10 ¹⁷ cm ⁻³ , which is the same concentration as the n ⁻ layer 1a, and the thickness is preferably about 0.1 μm to 1.5 μm. Then, p ⁺ layer 3c is formed on p ⁺ layer 3b by patterning and aluminum ion implantation so as to be electrically connected to p ⁺ layers 3a and 3b. The active impurity concentration of p ⁺ layer 3c is preferably about 1.0×10 ¹⁷ to 1.0×10 ²⁰ cm ⁻³ and the depth is preferably about 0.2 to 2.0 μm. Note that the p ⁺ layer 3 c may be formed simultaneously with the p ⁺ layer 18 of the active portion 102 .

Thereafter, patterning by photolithography and ion implantation of phosphorus, arsenic, or nitrogen are performed to form an n ⁺ type channel stopper region (n ⁺ layer) 4 at the end of the n ^- layer 1c. The n ⁺ layer 4 preferably has an activation impurity concentration of about 1.0×10 ¹⁸ to 1.0×10 ²⁰ cm ⁻³ and a depth of about 0.05 to 0.5 μm. The n ⁺ layer 4 may be formed simultaneously with the n ⁺ layer 17 of the active portion. After depositing a carbon film of about 0.01 to 5.0 μm, annealing is performed at 1500° C. to 1900° C. to activate the implanted impurity ions.

Next, as shown in FIG. 8, an oxide film is deposited to a thickness of about 0.1 to 3.0 μm to form an interlayer insulating film 5 . The interlayer insulating film 5 may be formed at the same time as the interlayer insulating film 21 in the active portion. The termination structure 101 of the first embodiment can be formed by the steps described above.

(Embodiment 2)
The semiconductor device according to this embodiment is configured using a wide bandgap semiconductor. In the second embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example.

FIG. 9 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the second embodiment. In the second embodiment, the structural example of the active portion 102 is the same as in the first embodiment (FIG. 3), and the method of manufacturing the active portion 102 is also the same as in the first embodiment.

Also, the method of manufacturing the termination structure portion 101 is the same as the steps up to the formation of the p ⁺ layer 3a described in the first embodiment (a part of FIGS. 4 and 5).

As shown in FIG. 9, the bottom of p ⁺ layer 3a is kept at the same position, and patterning and aluminum ion implantation are performed to form a plurality of p-type guard ring regions (p ⁺ layer: guard ring) 8 in the direction of the edge. The p ⁺ layer 8 preferably has an activation impurity concentration of about 1.0×10 ¹⁷ to 1.0×10 ¹⁹ cm ^-3 and a depth of about 0.1 to 1.5 μm. Note that p ⁺ layer 8 may be formed at the same time as p ⁺ layer 3a.

After that, n ⁻ layer 1b is formed by an epitaxial growth method in which nitrogen is added to the surface on the silicon carbide substrate 1 side, thereby forming region II. After that, the manufacturing process is similar to that of the first embodiment. The termination structure portion 101 of the second embodiment can be formed by the steps described above.

As shown in FIG. 9, a plurality of p ⁺ layers 8 are embedded in silicon carbide substrate 1 apart from p ⁺ layer 3 at the end of active portion 102, and the height of the lower portions of p ⁺ layers 3 and p ⁺ layers 8 is within ±0.3 μm. The p ⁺ layer 8 functions as a guard ring structure, and by alleviating electric field concentration at the corners of the p ⁺ layer 8, the withstand voltage can be improved. Incidentally, if the concentration of the p ⁺ layer 8 is the same as that of the p ⁺ layer 3, it can be formed by a single ion implantation, which is preferable. It is preferable that the lateral distance between the p ⁺ layers 8 is narrow, and the distance closest to the edge of the active portion 102 is preferably about 0.01 μm to 1.0 μm. Further, it is more preferable to widen the distance stepwise as the distance from the edge of the active portion 102 increases.

(Embodiment 3)
FIG. 10 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the third embodiment. In the third embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. In the third embodiment, the structural example of the active portion 102 is the same as in the first embodiment (FIG. 3), and the method for manufacturing the active portion 102 is also the same as in the first embodiment.

Also, the method of fabricating termination structure 101 is the same as the steps (FIGS. 4 and 5) up to formation of p ⁻ layer 6 described in the first embodiment. Next, n ⁻ layer 1b (see FIG. 6) is formed on the surface on the silicon carbide substrate 1 side by an epitaxial growth method in which nitrogen is added. The n ⁻ layer 1b preferably has a concentration of about 1.0×10 ¹⁴ to 1.0×10 ¹⁷ cm ⁻³ , the same concentration as the n ⁻ layer 1a, and a thickness of about 0.1 μm to 1.5 μm. Next, p ⁺ layer 3b is formed so as to be electrically connected to p ⁺ layer 3a by patterning and aluminum ion implantation at the position of p ⁺ layer 3a (see FIG. 6).

Next, as shown in FIG. 10, a third JTE region (p ⁻ layer: first semiconductor layer) 9 is formed by patterning and aluminum ion implantation so that at least a portion thereof is positioned above the p ⁻ layer 6 . The p ^- layer 9 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm.

Then, n ⁻ layer 1c (see FIG. 7) is formed by an epitaxial growth method in which nitrogen is added to the surface on the silicon carbide substrate 1 side. The concentration of the n ⁻ layer 1c is about 1.0×10 ¹⁴ to 1.0×10 ¹⁷ cm ⁻³ , which is the same concentration as the n ⁻ layer 1a, and the thickness is preferably about 0.1 μm to 1.5 μm. Next, as shown in FIG. 10, a fourth JTE region (p ⁻ layer) 10 is formed by patterning and aluminum ion implantation such that at least a portion thereof is positioned above the p ⁻ layer 6 . The p ^- layer 9 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm. After that, the manufacturing process is similar to that of the first embodiment. The termination structure portion 101 of the second embodiment can be formed by the steps described above.

According to the structure shown in FIG. 10, effects similar to those of the first embodiment (FIG. 1) are obtained. In FIG. 10, unlike the first embodiment (FIG. 1), a structure is provided in which a concentration gradient is provided in the height direction without changing the p ⁻ concentration in the lateral direction within the termination structure 101 to maintain the breakdown voltage. The p ⁻ layer 6 is arranged within ±0.3 μm from the height of the lower portion of the p ⁺ layer 3 at the edge of the active portion. The integrated value of the acceptor concentration in the height direction, which is indicated by the dose of the p ⁻ layer, satisfies the relationship a-line dose>b-line dose>c-line dose in the drawing, thereby forming a gradation in the horizontal direction of the termination structure 101 and obtaining the same breakdown voltage as in the first embodiment (FIG. 1).

(Embodiment 4)
FIG. 11 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the fourth embodiment. In the fourth embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. Also in the fourth embodiment, the structural example of the active portion 102 is the same as in the first embodiment (FIG. 3), and the method of manufacturing the active portion 102 is also the same as in the first embodiment.

Also, the method of manufacturing the termination structure portion 101 is the same as the steps up to the formation of the p ⁺ layer 3b described in the first embodiment (FIGS. 4 to 6). Next, as shown in FIG. 11, p ⁻ layer 9 is formed by patterning and aluminum ion implantation so that at least a portion thereof is positioned above p ⁻ layer 6 . The p ^- layer 9 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm. Next, a fifth JTE region (p − layer) 12 is formed by patterning and aluminum ion implantation such that at least a portion of the fifth JTE region (p ⁻ layer) 12 is positioned above p ⁻ layer 7 and connected to p ⁻ layer 9 . The p ^- layer 12 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm.

Next, n ⁻ layer 1c is formed on the surface on the silicon carbide substrate 1 side by an epitaxial growth method in which nitrogen is added (see FIG. 7). The concentration of the n ⁻ layer 1c is about 1.0×10 ¹⁴ to 1.0×10 ¹⁷ cm ⁻³ , which is the same concentration as the n ⁻ layer 1a, and the thickness is preferably about 0.1 μm to 1.5 μm. A p ⁺ layer 3c is formed by patterning and aluminum ion implantation so as to be electrically connected to the p ⁺ layer 3a (see FIG. 7). The active impurity concentration of p ⁺ layer 3c is preferably about 1.0×10 ¹⁷ to 1.0×10 ²⁰ cm ⁻³ and the depth is preferably about 0.2 to 2.0 μm. Note that the p ⁺ layer 3 c may be formed simultaneously with the p ⁺ layer 18 of the active portion 102 .

Thereafter, patterning and aluminum ion implantation are performed to form p ⁻ layer 10 so that at least a portion thereof is positioned above p ⁻ layer 9 . The p ^- layer 10 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm. Next, a sixth JTE region (p ⁻ layer) 14 is formed by patterning and aluminum ion implantation such that at least a portion thereof is positioned above p ⁻ layer 12 and connected to p ⁻ layer 10 . The p ^- layer 14 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm. After that, the manufacturing process is similar to that of the first embodiment. The termination structure 101 of the fourth embodiment can be formed by the steps described above.

In the example of termination structure 101 shown in FIG. 11, the front surface side of p ⁻ layer 7 is in contact with p ⁻ layers 9 and 12 . The front surface side of p ⁻ layer 12 is in contact with p ⁻ layers 10 and 14 .

11, p ^- layers 9, 10, 12 and 14 are formed on the front surface side of p ^- layers 6 and 7 in addition to the structure shown in the first embodiment (FIG. 4). Note that the integrated value of the acceptor concentration in the height direction, which is indicated by the dose of the p ⁻ layer, is preferable because the dose decreases as the distance from the end of the active portion 102 increases by forming the p ⁻ layers 6, 7, 9, 12, 10, and 14 so that the following relationship is satisfied: a-line dose > b-line dose > c-line dose > d-line dose > e-line dose > f-line dose.

For example, it is preferable to form the p ^{- layer 9 farther from the edge of the active part 102 than the p -} layer 6, the p ^- layer 10 farther from the edge of the active part 102 than the p ^- layer 9, the p ^- layer 12 farther from the edge of the active part 102 than the p ^- layer 7, and the ^{p - layer} 14 farther from the edge of the active part 102 than the p ^- layer 12. In addition, the effect of maintaining the breakdown voltage can be obtained by having at least two levels of concentration gradients in the height direction region. According to the fourth embodiment, the lateral length of the termination structure 101 can be made shorter than that of the first embodiment (FIG. 1).

(Embodiment 5)
FIG. 12 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the fifth embodiment. In the fifth embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. In the fifth embodiment, the structural example of the active portion 102 is the same as in the first embodiment (FIG. 3), and the method for manufacturing the active portion 102 is also the same as in the first embodiment.

Also, the method of manufacturing the termination structure portion 101 is the same as the steps up to the formation of the p ⁺ layer 3b described in the first embodiment (FIGS. 4 to 6). Next, n ⁻ layer 1c is formed on the surface on the silicon carbide substrate 1 side by an epitaxial growth method in which nitrogen is added (see FIG. 7). Thereafter, p ⁻ layer 10 and p ⁻ layer 14 are formed in the same manner as in the fourth embodiment. After that, the manufacturing process is similar to that of the first embodiment. The termination structure 101 of the fifth embodiment can be formed by the steps described above.

According to the structure of FIG. 12, the concentration gradient in the height direction region of the termination structure portion 101 is set to a minimum of two steps, the structure and manufacturing can be simplified, and the breakdown voltage can be maintained.

(Embodiment 6)
FIG. 13 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the sixth embodiment. In the sixth embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. In the sixth embodiment, the structural example of the active portion 102 is the same as in the first embodiment (FIG. 3), and the method of manufacturing the active portion 102 is also the same as in the first embodiment.

Also, the method of fabricating the termination structure 101 is the same as the steps up to the formation of the p ⁺ layer 3c described in the first embodiment (FIGS. 4 to 6). Next, p ⁻ layer 10 is formed by patterning and aluminum ion implantation. The p ^- layer 10 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm. After that, the manufacturing process is similar to that of the first embodiment. The termination structure 101 of Embodiment 6 can be formed by the steps described above.

According to the structure of the termination structure portion 101 in FIG. 13, in addition to the embodiment (FIG. 1), only the p ⁻ layer 10 with a single concentration is provided in the lateral direction, and the effect of maintaining the breakdown voltage can be similarly obtained without providing gradation in the lateral direction.

(Embodiment 7)
FIG. 14 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the seventh embodiment. In the seventh embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. In the seventh embodiment, the structural example of the active portion 102 is the same as in the first embodiment (FIG. 3), and the method for manufacturing the active portion 102 is also the same as in the first embodiment.

Also, the method of fabricating the termination structure 101 is the same as the steps up to the formation of the p ⁺ layer 3c described in the first embodiment (FIGS. 4 to 6). Next, n ⁻ layer 1c is formed on the surface on the silicon carbide substrate 1 side by an epitaxial growth method in which nitrogen is added (see FIG. 7). After that, the steps similar to those of the first embodiment are performed. The termination structure 101 of Embodiment 6 can be formed by the steps described above.

As shown in the structure of the termination structure portion 101 in FIG. 14, even when the vertical positional relationship of the p ⁻ layer is changed from that of the first embodiment (FIG. 1), the same effect can be obtained that the breakdown voltage can be maintained and the lateral length can be shortened.

(Embodiment 8)
FIG. 15 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the eighth embodiment. In the eighth embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. Also in the eighth embodiment, the structural example of the active portion 102 is the same as in the first embodiment (FIG. 3), and the method for manufacturing the active portion 102 is also the same as in the first embodiment.

Also, the method of manufacturing the termination structure portion 101 is the same as the steps up to the formation of the p ⁺ layer 3b in the second embodiment (FIG. 9). Thereafter, p ⁻ layer 9 is formed on the front surface side of p ⁺ layer 3b by patterning and aluminum ion implantation. The p ^- layer 9 preferably has an activation impurity concentration of about 1.0×10 ¹⁶ to 1.0×10 ¹⁸ cm ^-3 and a depth of about 0.1 to 1.5 μm. After that, it is formed in the same manner as in the third embodiment (see FIG. 10, p ⁻ layer 10 and the like are formed on the front surface side of p ⁻ layer 9). The termination structure 101 of the eighth embodiment can be formed by the steps described above.

In the structure of the termination structure portion 101 shown in FIG. 15, the p ⁻ layer 9 is in contact with the p ⁺ layer 8, the p ⁻ layer 10 is in contact with the p ^{− layer 9, and the p − layer} 10 extends to the end position more than the p ⁻ layer 9.

According to the structure of the termination structure portion 101 shown in FIG. 15, the length in the lateral direction can be shortened as compared with the second embodiment (FIG. 9). That is, the p ⁻ layers 9 and 10 arranged on the front surface side of the p ⁺ layer 8 can adjust the electric field relaxed in the lower p ⁺ layer 8, so that the lateral length of the termination structure portion 101 can be shortened.

(Embodiment 9)
FIG. 16 is a cross-sectional view showing the configuration of the termination structure portion of the semiconductor device according to the ninth embodiment. In the ninth embodiment, a silicon carbide semiconductor device manufactured using, for example, silicon carbide (SiC) as a wide bandgap semiconductor will be described using a MOSFET as an example. In the ninth embodiment, the structural example of the active portion 102 is the same as in the first embodiment (FIG. 3), and the method for manufacturing the active portion 102 is also the same as in the first embodiment.

Also, the method of manufacturing the termination structure portion 101 is the same as the steps up to the formation of the p ⁺ layer 3c in the third embodiment (FIG. 10). Thereafter, a plurality of p ⁺ layers 8 are formed by patterning the p ⁻ layer 9 on the front surface side and implanting aluminum ions. The p ⁺ layer 8 preferably has an activation impurity concentration of about 1.0×10 ¹⁷ to 1.0×10 ¹⁹ cm ^-3 and a depth of about 0.1 to 1.5 μm. Note that the p ⁺ layer 8 may be formed simultaneously with the p ⁺ layer 3 c or the p ⁺ layer 18 of the active portion 102 .

Thereafter, the n ⁺ layer 4 is formed by patterning by photolithography and ion implantation of phosphorus, arsenic, or nitrogen. The n ⁺ layer 4 preferably has an activation impurity concentration of about 1.0×10 ¹⁸ to 1.0×10 ²⁰ cm ⁻³ and a depth of about 0.05 to 0.5 μm. Note that the n ⁺ layer 4 may be formed simultaneously with the n ⁺ layer 17 of the active portion 102 . After that, the manufacturing process is similar to that of the first embodiment. The termination structure 101 of the ninth embodiment can be formed by the steps described above.

In the structure of the termination structure portion 101 shown in FIG. 16, the p ⁻ layer 9 is in contact with the front surface side of the p ⁻ layer 6 when viewed from the lower layer, and the p ⁻ layer 9 extends to the end position more than the p ⁻ layer 6. A plurality of p ⁺ layers 8 are formed in contact with the front surface side of the p ⁻ layer 9 . P ⁺ layer 8 is not in contact with p ⁺ layer 3 .

According to the structure of the termination structure portion 101 shown in FIG. 16, compared with the second embodiment (FIG. 9), even if the vertical positional relationship between the p ⁺ layer 8 and the p ⁻ layer 9 is reversed, the same effect can be obtained that the breakdown voltage can be maintained and the lateral length can be shortened.

As described above, in the present embodiment, the main surface of the silicon carbide substrate made of silicon carbide is the (0001) plane, and the MOS is formed on the (0001) plane.

Further, in each embodiment, the first conductivity type is n-type and the second conductivity type is p-type, but this embodiment can be similarly applied to the first conductivity type as p-type and the second conductivity type as n-type.

As described above, the semiconductor device and the method for manufacturing a semiconductor device according to the present embodiment are useful for high-voltage semiconductor devices used in power converters and power supply devices for various industrial machines.

1 (1a, 1b, 1c) n ^- type silicon carbide epitaxial layer (n ^- layer)
2 n ⁺ type silicon carbide substrate 3 (3a, 3b, 3c) p ⁺ base layer (p ⁺ layer)
4 n ⁺ type channel stopper region (n ⁺ layer)
5 Interlayer insulating film 6 First JTE region (p-type layer)
7 Second JTE region (p ^- type layer)
8 p-type guard ring region (p ⁺ layer)
9 3rd JTE region (p ^- layer)
10 4th JTE region (p ^- layer)
12 5th JTE region (p ^- layer)
14 6th JTE region (p ^- layer)
15a, 15b n-type CSL region (n-layer)
16 p-type channel region (p layer)
17 n-type source region (n ⁺ layer)
18 p-type region (p ⁺ layer)
19 trench 20 gate electrode 21 interlayer insulating film 22 source electrode

Claims (16)

A semiconductor device including an active region through which a current flows and a termination structure formed outside the active region and formed with a breakdown voltage structure, wherein each semiconductor layer is formed on a semiconductor substrate,
a first conductivity type drift layer as the semiconductor layer;
a base layer of a second conductivity type as the semiconductor layer provided between the front surface of the semiconductor substrate and the drift layer inside the termination structure and in contact with the termination structure;
an interlayer insulating film overlapping the front surface of the semiconductor substrate from the active region to the termination structure;
with
The termination structure is
a second conductivity type first semiconductor layer continuous from the base layer;
a second semiconductor layer of a first conductivity type that is continuous with the drift layer and forms a pn junction in contact with the first semiconductor layer;
a channel stopper layer provided outside the first semiconductor layer and separated from the first semiconductor layer;
A semiconductor device according to claim 1, wherein an outer tip of said first semiconductor layer is located at a depth away from a front surface of said semiconductor substrate and does not contact said interlayer insulating film, and a distance between said tip and said channel stopper layer in a direction parallel to said front surface of said semiconductor substrate is longer than a distance between said tip and said interlayer insulating film in a depth direction. 2. The semiconductor device according to claim 1, wherein the outer tip of the first semiconductor layer is provided at a deeper position in the semiconductor substrate than the surface of the channel stopper layer on the interlayer insulating film side in the depth direction. 3. The semiconductor device according to claim 1, wherein said channel stopper layer is formed with a depth of 0.05 μm to 0.5 μm. The second semiconductor layer surrounds the tip outside the first semiconductor layer,
4. The semiconductor device according to claim 1, wherein a depletion layer formed by said pn junction at said tip outside said first semiconductor layer also extends toward said interlayer insulating film. 5. The semiconductor device according to claim 1, wherein said first semiconductor layer has a lower impurity concentration than said base layer. 6. The semiconductor device according to claim 5, wherein the impurity concentration of said first semiconductor layer decreases from the side of said base layer toward the outside. 6. The semiconductor device according to claim 1, wherein a lower portion of said first semiconductor layer is located at a shallower depth from a front surface of said semiconductor substrate as it goes outward from said base layer side. 8. The semiconductor device according to claim 1, wherein said active region has a MOS gate structure including a trench in which a gate electrode is buried. 9. The semiconductor device according to claim 8, wherein said base layer is formed deeper than said trench on the back side of said semiconductor substrate. 10. The semiconductor device according to claim 8, wherein the first semiconductor layer is formed deeper than the trench on the back surface side of the semiconductor base. 11. The semiconductor device according to claim 1, wherein the base layer and the first semiconductor layer have end portions in the same position in the depth direction. 11. The semiconductor device according to claim 1, wherein the base layer and the first semiconductor layer have a difference in position of their ends in the depth direction within a range of ±0.2 [mu]m. 13. The semiconductor device according to claim 1, wherein said interlayer insulating film has a thickness of 0.1 μm to 3.0 μm. 14. The semiconductor device according to claim 1, wherein the base layer has an impurity concentration of 1.0×10 ¹⁷ cm ⁻³ to 1.0×10 ¹⁹ cm ⁻³ . A method for manufacturing a semiconductor device having a MOS gate structure including an active region through which a current flows and a termination structure disposed outside the active region and formed with a breakdown voltage structure, each semiconductor layer being formed on a semiconductor substrate, and including a trench in which a gate electrode is embedded in the active region,
forming a first conductivity type drift layer as the semiconductor layer;
simultaneously forming, on the drift layer, at least part of a base layer of a second conductivity type as the semiconductor layer disposed between the MOS gate structure and the termination structure and in contact with the termination structure, and a trench bottom semiconductor layer of the second conductivity type as the semiconductor layer in contact with the bottom of the trench;
forming a second conductivity type channel region of the MOS gate structure in the active region;
forming a first semiconductor layer of a second conductivity type as the semiconductor layer on the drift layer in the termination structure;
forming a high-concentration semiconductor layer of a second conductivity type on the channel region, electrically connected to the base layer and having a higher impurity concentration than the channel region as the semiconductor layer;
including
performing the step of forming the high-concentration semiconductor layer after the step of forming the first semiconductor layer;
A method of manufacturing a semiconductor device, wherein the position of the surface of the first semiconductor layer is positioned deeper in the semiconductor substrate than the position of the surface of the high-concentration semiconductor layer in the depth direction. 16. The method of manufacturing a semiconductor device according to claim 15, wherein in the step of forming the first semiconductor layer, a plurality of guard rings are formed as the first semiconductor layer.

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