JP5206248B2 - Semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device.

  2. Description of the Related Art A semiconductor device has been developed that includes a central region in which circuit elements are formed and a first conductivity type semiconductor substrate that is partitioned into a peripheral region that surrounds the outside of the central region. A technique is known in which a plurality of trenches are formed in the peripheral region of such a semiconductor device, and a second conductivity type diffusion region is formed in a range surrounding the bottom of the trench. In this technique, the depletion layer can be extended from the central region to the peripheral region by the diffusion region at the bottom of the trench when the circuit element is non-conductive. Thereby, the breakdown voltage of the semiconductor device can be improved.

FIG. 7 shows a cross-sectional view of the main part of this type of semiconductor device 500. As shown in FIG. 7, the semiconductor device 500 includes a central region 98A in which circuit elements are formed and an n-type semiconductor substrate 95 partitioned into a peripheral region 98B that surrounds the central region 98A. Yes.
The semiconductor device 500 is a power MOS (Metal Oxide Semiconductor). An insulating film 88b is formed on a part of the surface of the peripheral region 98B. An n type drift region 84 is formed inside the semiconductor substrate 95. An n ⁺ -type drain region 82 is formed in a range facing the back surface of the semiconductor substrate 95. A p-type body region 94 is formed in a range facing the surface of the semiconductor substrate 95 from the central region 98A to a part of the peripheral region 98B. A main trench 90 extending from the surface of the semiconductor substrate 95 to the drift region 84 through the body region 94 is formed in the center region 98A. The main trench 90 is filled with a gate electrode 89 covered with an insulating material 88a. A drain electrode 96 is formed on the back surface of the semiconductor substrate 95. A body contact region and a source region are formed in a range of the central region 98A facing the surface of the semiconductor substrate 95 and not shown. A source electrode in contact with the source region is formed on the surface of the semiconductor substrate 95 in the central region 98A and in a range not shown. In the central region 90, circuit elements constituting the power MOS are formed.

  In the peripheral region 98B, a plurality of termination trenches 92a to 92c extending from the surface of the semiconductor substrate 95 to the drift region 84 through the body region 94 are formed. The insulating material 88c is filled in the termination trenches 92a to 92c. The termination trenches 92a to 92c go around the peripheral region 98B. P-type diffusion regions 86 and 86a to 86c are formed in a range surrounding the bottom of each of the main trench 90 and the termination trenches 92a to 92c.

According to the semiconductor device 500, since the diffusion regions 86 and 86a to 86c are formed, the depletion layer extends from the central region 98A to the peripheral region 98B when the circuit element is non-conductive. As a result, the breakdown voltage of the semiconductor device 500 can be improved.
Patent Documents 1 to 3 are known as conventional examples of this type of semiconductor device.

JP 2008-103530 A JP 2006-128507 A JP-A-9-238754

  In a trench gate type semiconductor device such as the semiconductor device 500, the body region 94 is usually formed in a range inside the terminal trenches 92a to 92c. Therefore, when forming the body region 94 in the manufacturing process, a part of the surface of the semiconductor substrate 95 is shielded with a photomask or the like to limit the impurity implantation region. However, for example, when impurities are implanted at high acceleration, the impurities may be implanted into the semiconductor substrate 95 through a photomask or the like. As a result, the body region 94 is formed in an unintended range, and the body region 94 reaching the end of the semiconductor substrate 95 may be formed.

  FIG. 8 shows a state where the circuit element is non-conductive when the body region 94a reaching the end of the semiconductor substrate 95 is formed in the semiconductor device 500 shown in FIG. As shown in FIG. 8, in the semiconductor device 500, when the circuit element is non-conductive, the depletion layer 99 extends from the central region 98A to the peripheral region 98B by the diffusion regions 86, 86a to 86c, and the body region outside the diffusion region 86c. Connected to 94a. Since the body region 94a reaches the end portion 95a of the semiconductor device 500, a leak current is generated from the end portion 95a of the semiconductor substrate 95 (reference symbol B), and the breakdown voltage of the semiconductor device 500 is reduced.

  In view of the above problems, the present invention can prevent a decrease in breakdown voltage by preventing generation of a leakage current when non-conducting in a semiconductor device in which a plurality of breakdown voltage holding trenches are formed in a peripheral region. An object of the present invention is to provide a semiconductor device that can be used.

The present invention relates to a semiconductor device including a central region in which circuit elements are formed and a first conductivity type semiconductor substrate that is partitioned into a peripheral region surrounding the outside of the central region.
The semiconductor device of the present invention includes a second conductivity type body region formed in a range facing the surface in the semiconductor substrate. The body region is formed continuously from the central region to the peripheral region.

The semiconductor device of the present invention includes a plurality of first trenches formed in the peripheral region. The first trench extends from the surface of the semiconductor substrate to penetrate the body region.
The semiconductor device of the present invention includes one or a plurality of second trenches formed outside the first trench located on the outermost side in the peripheral region. The second trench extends from the surface of the semiconductor substrate to penetrate the body region.

  In the semiconductor device of the present invention, a diffusion region of the second conductivity type is formed in a range surrounding the bottom of the first trench. The plurality of first trenches are arranged from the central region side toward the outside with an interval where the depletion layer is connected when the circuit element is non-conductive. The distance between the outermost first trench and the second trench adjacent to the first trench is such that the depletion layer is not connected when the circuit element is non-conductive.

  According to the semiconductor device of the present invention, when the circuit element is non-conductive, the depletion layer is connected between the first trenches, while the outermost first trench and the second trench adjacent to the first trench are connected. There is no depletion layer connected to the trench. Since the second trench extends from the surface of the semiconductor substrate to penetrate the body region, the depletion layer does not extend beyond the second trench to the outside of the second trench. For this reason, even when the body region is formed as far as the end portion of the semiconductor device, the body region reaching the end portion of the semiconductor device is not connected to the depletion layer that extends during non-conduction. For this reason, generation | occurrence | production of leak current is suppressed and the pressure | voltage resistant fall of a semiconductor device is prevented. On the other hand, a depletion layer is connected between the first trenches when the circuit element is non-conductive. As a result, the depletion layer extends from the central region to the peripheral region, and high breakdown voltage characteristics are maintained.

  In the semiconductor device of the present invention, it is preferable that a diffusion region of the second conductivity type is formed in a range surrounding the bottom of the second trench. In this case, since the diffusion region is formed in a range surrounding the bottoms of both the first trench and the second trench, the first trench and the second trench can be formed in the same manufacturing process. Therefore, the manufacturing process can be shortened.

  The semiconductor device of the present invention includes a plurality of second trenches, and the plurality of second trenches are arranged from the central region side toward the outside with an interval at which the depletion layer is not connected when the circuit element is non-conductive. Preferably it is. By providing a plurality of second trenches, the occurrence of leakage current is more reliably prevented. Thereby, it is possible to more reliably prevent the breakdown voltage of the semiconductor device from decreasing.

Another aspect of the present invention relates to a semiconductor device including a central region in which circuit elements are formed and a first conductivity type semiconductor substrate partitioned into a peripheral region surrounding the outside of the central region.
A semiconductor device according to another aspect of the present invention includes a body region of a second conductivity type formed in a range facing a surface in a semiconductor substrate. The body region is formed continuously from the central region to the peripheral region.

A semiconductor device according to another aspect of the present invention includes a plurality of first trenches formed in a peripheral region. The first trench extends from the surface of the semiconductor substrate to penetrate the body region.
The semiconductor device according to another aspect of the present invention includes one or a plurality of second trenches formed outside the first trench located on the outermost side in the peripheral region. The second trench extends from the surface of the semiconductor substrate to penetrate the body region.

In the semiconductor device according to another aspect of the present invention, the second conductivity type diffusion region is formed in a range surrounding the bottom of the first trench, and the plurality of first trenches are directed outward from the central region side. The circuit elements are arranged with an interval to which the depletion layer is connected when the circuit element is non-conductive. On the other hand, no diffusion region of the second conductivity type is formed in the range surrounding the bottom of the second trench. The distance between the outermost first trench and the second trench adjacent to the first trench is such that the depletion layer extends beyond the second trench when the circuit element is non-conductive. It is set as the space | interval which is prevented from being connected to the body region outside.

  When the circuit element is non-conductive, the depletion layer extends due to the diffusion region formed at the bottom of the first trench. According to the semiconductor device of another aspect of the present invention, since the diffusion region is not formed at the bottom of the second trench, the depletion layer is prevented from being connected between the first trench and the second trench. The Therefore, it is possible to prevent the depletion layer extending during non-conduction from extending outward beyond the second trench. For this reason, even when the body region is formed even at the end of the semiconductor device, the depletion layer is prevented from being connected to the body region reaching the end of the semiconductor device, and the generation of leakage current is suppressed. Is done. As a result, a decrease in breakdown voltage of the semiconductor device is prevented. On the other hand, since the depletion layer is connected between the first trenches when the circuit element is non-conductive, high breakdown voltage characteristics are maintained.

  According to the present invention, in a semiconductor device in which a plurality of trenches are formed in the peripheral region and a diffusion region is formed in a range surrounding the bottom of the trench, it is possible to prevent a breakdown voltage from being lowered due to a leakage current.

Preferred features of the embodiments described below are listed.
(First Feature) The space between the outermost first trench and the second trench adjacent to the first trench is a depletion layer extending from the central region toward the peripheral region when the circuit element is non-conductive. Is set so as not to reach the diffusion region formed at the bottom of the second trench.
(Second feature) When the diffusion region is not formed at the bottom of the second trench, the distance between the outermost first trench and the second trench adjacent to the first trench is the circuit. The spacing is such that the depletion layer extending from the central region to the peripheral region does not reach the intermediate position in the width direction of the second trench when the element is not conducting.
(Third Feature) A plurality of second trenches are formed outside the first trench.
(4th characteristic) The inside of the 1st trench located in the innermost side is filled with the trench gate electrode coat | covered with the insulating material.
(Fifth Feature) A side diffusion region of the second conductivity type that extends over the body region and the diffusion region is formed in a range facing the side surface of the main trench.

(First embodiment)
FIG. 3 is a plan view of the semiconductor device 100 according to the first embodiment of the present invention. FIG. 3 shows only the region inside the dividing trench 12d described in detail later.
As shown in FIG. 3, four main trenches 10 are formed in the central region 18 </ b> A of the semiconductor device 100. In the peripheral region 18B, three termination trenches 12a to 12c and a dividing trench 12d surrounding the outside of the main trench 10 are formed. The termination trenches 12a to 12c and the dividing trench 12d make a round around the peripheral region 18B.

FIG. 1 is a cross-sectional view taken along the line I-I in FIG. 3 and shows a main part of the semiconductor device 100. FIG. 1 shows a case where a body region reaching the end of the semiconductor device 100 is formed in the peripheral region 18B.
The semiconductor device 100 is a power MOS. The semiconductor device 100 includes an n-type semiconductor substrate 15 that is partitioned into a central region 18A and a peripheral region 18B that surrounds the outside of the central region 18A. An insulating film 8b is formed on the surface of the semiconductor substrate 15 in the peripheral region 18B. An n-type drift region 4 is formed inside the semiconductor substrate 15. An n ⁺ -type drain region 2 is formed in a range facing the back surface of the semiconductor substrate 15. A p-type body region 14 is formed in a range facing the surface of the semiconductor substrate 15 from the central region 18A to the peripheral region 18B. The body region 14 reaches the end 15 a of the semiconductor substrate 15. In the central region 18A, a plurality of main trenches 10 extending from the surface of the semiconductor substrate 15 through the body region 14 to the drift region 4 are formed. The main trench 10 is filled with a gate electrode 9 covered with an insulating material 8a. A drain electrode 16 is formed on the back surface of the semiconductor substrate 15. A body contact region and a source region are formed in a range of the central region 18A facing the surface of the semiconductor substrate 15 and not shown. A source electrode in contact with the source region is formed on the surface of the semiconductor substrate 15 in the central region 18A and in a range not shown. In the center region 10, circuit elements constituting the power MOS are formed.

  In the peripheral region 18B, a plurality of terminal trenches (first trenches) 12a to 12c extending from the surface of the semiconductor substrate 15 through the body region 15a to the drift region 4 are formed. The interior of the termination trenches 12a to 12c is filled with an insulating material 8c. In the peripheral region 18B, a dividing trench (second trench) 12d is formed on the outer side of the outermost termination trench 12c. P-type diffusion regions 6 and 6a to 6d are formed in a range surrounding the bottom of each of the main trench 10, the termination trenches 12a to 12c, and the dividing trench 12d. The termination trenches 12a to 12c are arranged from the center region 18A toward the outside with intervals W2 and W3 to which depletion layers are connected when the circuit element is non-conductive. The interval W1 between the outermost termination trench 12c and the dividing trench 12d is an interval at which the depletion layer is not connected when the circuit element is non-conductive.

  In the semiconductor device 100, three termination trenches 12a to 12c are formed, but the number of termination trenches is not limited. Moreover, the dividing trench 12d is not limited to one. A plurality of dividing trenches may be arranged.

The width W of the depletion layer that extends when the circuit element is non-conducting can be obtained by the following equation.
W = {2ε (V _bi −V) / qN} ^1/2
Here, ε is a dielectric constant, V _bi is a built-in potential, V is a voltage applied to the element (element breakdown voltage), q is a charge amount, and N is a concentration in the drift region. Here, the built-in potential is a physical quantity determined by the concentration of the drift region and the concentration of the diffusion region.
For example, each value such as the concentration of the drift region can be determined from the above formula so that the width W of the depletion layer is about 0.4 μm in a 70V withstand voltage product.

  FIG. 2 shows a state of the depletion layer 19 formed in the semiconductor device 100 when the circuit element is non-conductive. As shown in FIG. 2, when the circuit element is non-conductive, the depletion layer 19 extends from the central region 18A to the peripheral region 18B and is connected to the body region 14 formed between the termination trench 12c and the dividing trench 12d. On the other hand, since the interval between the termination trench 12c and the dividing trench 12d is the interval W1 at which the depletion layer 19 is not connected during non-conduction, the diffusion region 6c formed at the bottom of the termination trench 12c and the bottom of the dividing trench 12d are formed. The depletion layer 19 is prevented from being connected to the diffusion region 6d. For this reason, generation | occurrence | production of leakage current is suppressed by the dividing trench 12d (reference symbol A). As a result, a decrease in the breakdown voltage of the semiconductor device 100 is prevented. On the other hand, in the termination trenches 12a to 12c located inside the termination trench 12d, a depletion layer is connected between adjacent trenches. For this reason, the depletion layer 19 extends from the central region 18A to the peripheral region 18B during non-conduction, and high breakdown voltage characteristics can be maintained.

  In the semiconductor device 100 of the present embodiment, the distance between the outermost termination trench 12d and the dividing trench 12d is such that the depletion layer 19 is formed at the bottom of the dividing trench 12d when the circuit element is non-conductive. The interval is not reached. For this reason, when the semiconductor device 100 is non-conducting, the depletion layer 19 is prevented from exceeding the dividing trench 12d and being connected to the body region 14 outside the dividing trench 12d. As a result, the occurrence of leakage current can be prevented.

A method for forming the trenches 10 and 12a to 12d and the diffusion regions 6 and 6a to 6d will be described below. Note that a conventional method can be used as a method of filling the insulating materials 8a to 8c and a method of forming each electrode group such as the gate electrode 16, and thus detailed description thereof is omitted here.
First, the drain region 2, the body region 14, the source region, and the body contact region are formed in the semiconductor substrate 15. Next, a photomask is formed on the semiconductor substrate 15, and a resist is formed on the photomask. Next, the main trench 10, the termination trenches 12a to 12c, and the dividing trench 12d are patterned. Next, the trenches 10, 12a to 12d are formed by etching according to patterning. Next, impurities such as boron are implanted into the bottoms of the trenches 10 and 12a to 12d to form diffusion regions 6 and 6a to 6d.

  As described above, in the semiconductor device 100, the termination trenches 12a to 12c and the dividing trench 12d can be patterned in the same process, and can be manufactured in the same process. Further, the diffusion regions 6 and 6a to 6d can be formed by the same process. For this reason, a manufacturing process can be shortened.

(Second embodiment)
FIG. 4 shows a cross-sectional view of a main part of a semiconductor device 200 according to the second embodiment of the present invention. In FIG. 4, the member obtained by adding the numeral 20 to the reference numeral in FIG. 1 is the same as the member described in FIG. As shown in FIG. 4, in the semiconductor device 200, unlike the first embodiment, no diffusion region is formed at the bottom of the dividing trench 32d.

  In this embodiment, since the diffusion region is not formed at the bottom of the dividing trench 32d, it is difficult to connect the depletion layer between the termination trench 32c located on the outermost side and the dividing trench 32d. Therefore, even if the interval W4 between the termination trench 32c and the dividing trench 32d is formed at an interval smaller than the interval W1 shown in FIG. 1, the depletion layer at the time of non-conduction exceeds the dividing trench 32d and the outside of the dividing trench 32d. It is possible to prevent the body region 34 from being connected. In addition, since the distance between the termination trench 32c and the dividing trench 32d can be shortened, the semiconductor device 200 can be reduced in size. For this reason, generation | occurrence | production of leak current is suppressed and the pressure | voltage resistant fall of the semiconductor device 200 is prevented. On the other hand, in the termination trenches 32a to 32c, a depletion layer is connected between adjacent trenches. For this reason, the depletion layer extends from the central region 38A to the peripheral region 38B during non-conduction, and high breakdown voltage characteristics can be maintained.

  In the semiconductor device 200 of the present embodiment, the distance between the outermost termination trench 32c and the dividing trench 32d adjacent to the termination trench 32c extends from the central region 38A toward the peripheral region 38B when the circuit element is non-conductive. The spacing is such that the depletion layer does not reach the middle position in the width direction of the second trench. For this reason, when the semiconductor device 200 is non-conductive, the depletion layer is prevented from passing over the dividing trench 32d and being connected to the body region 34 outside the dividing trench 32d. As a result, the occurrence of leakage current can be prevented.

(Third embodiment)
FIG. 5 shows a cross-sectional view of a main part of a semiconductor device 300 according to the third embodiment of the present invention. In FIG. 5, the members obtained by adding 40 to the reference numerals in FIG. 1 are the same as the members described in FIG. As shown in FIG. 5, unlike the first embodiment, the semiconductor device 300 is formed to a position where the depth of the dividing trench 52d is deeper than the depth of the termination trenches 52a to 52c. Since the dividing trench 52d is formed deeply, even if the dividing trench 52d and the termination trench 52c are arranged at a narrow interval, the depletion layer is not easily connected when the circuit element is non-conductive. Therefore, the semiconductor device 300 can be reduced in size.

(Fourth embodiment)
FIG. 6 is a cross-sectional view of a main part of a semiconductor device 400 according to the fourth embodiment of the present invention. In FIG. 6, the members obtained by adding 60 to the reference numerals in FIG. 1 are the same as the members described in FIG. As shown in FIG. 6, in the semiconductor device 400, unlike the first embodiment, the width of the dividing trench 72d is larger than the widths of the other termination trenches 72a to 72c. Even with such a configuration, it is possible to prevent the depletion layer from being connected to the body region 74 outside the dividing trench 72d by the dividing trench 72d. As a result, a decrease in the breakdown voltage of the semiconductor device 400 is prevented.

  In each of the above-described embodiments, only one dividing trench is formed outside the termination trench, but a plurality of dividing trenches may be provided. In particular, when a plurality of trenches are formed simultaneously in the manufacturing process of a semiconductor device, the depth of the outermost trench may be formed shallower than the depths of other trenches. For this reason, if there is only one dividing trench, the depth of the dividing trench may be formed shallower than the depth of other trenches. Therefore, when the circuit element is non-conductive, the depletion layer easily crosses the dividing trench and is easily connected to the body region outside the dividing trench. If a plurality of dividing trenches are formed outside the termination trench, even if the outermost dividing trench is shallow, the dividing trench inside is deeply formed. For this reason, the depletion layer is prevented from being connected to the body region beyond the dividing trench, and generation of leakage current is suppressed.

  Further, in each of the above-described embodiments, the inside of the termination trench is filled with an insulating material, but the inside of the termination trench located at the innermost side may be filled with a trench gate electrode covered with an insulating material. . According to such a configuration, the depletion layer can be spread in the central region and the peripheral region equally, and the peripheral region can be surely depleted.

  In each of the above-described embodiments, the second conductivity type side surface diffusion region may be formed across the diffusion region at the bottom of the main trench and the body region in a range facing the side surface of the main trench. According to such a configuration, when the circuit element is conductive, carriers are supplied from the body region to the diffusion region via the side surface diffusion region, so that the depletion layer extending in the vicinity of the diffusion region is rapidly narrowed. As a result, the on-resistance can be reduced.

As mentioned above, although the Example of this invention was described in detail, these are only illustrations and do not limit a claim. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

1 is a cross-sectional view of a main part of a semiconductor device 100 according to a first embodiment of the present invention. The state of the depletion layer formed in the semiconductor device 100 is shown. 1 is a plan view of a semiconductor device 100. FIG. The principal part sectional drawing of the semiconductor device 200 which is 2nd Example of this invention is shown. The principal part sectional drawing of the semiconductor device 300 which is 3rd Example of this invention is shown. The principal part sectional drawing of the semiconductor device 400 which is 4th Example of this invention is shown. The principal part sectional drawing of the conventional semiconductor device 500 is shown. The state of the depletion layer formed in the semiconductor device 500 is shown.

Explanation of symbols

2, 22, 42, 62, 82: Drain regions 4, 24, 44, 64, 84: Drift regions 6a-6d, 26a-26d, 46a-46d, 66a-66d: Diffusion regions 8b, 28b, 48b, 68b, 88b: Insulating films 8a, 8c, 28a, 28c, 48a, 48c, 68a, 68c, 88a, 88c: Insulating materials 9, 29, 49, 69, 89: Gate electrodes 10, 30, 50, 70, 90: Main trench 12a to 12c, 32a to 32c, 52a to 52c, 72a to 72c: termination trench (first trench)
12d, 32d, 52d, 72d: Dividing trench (second trench)
14, 34, 54, 74, 94, 94a: body regions 15, 35, 55, 75, 95: semiconductor substrates 16, 36, 56, 76, 96: drain electrodes 19, 99: depletion layers 100, 200, 300, 400, 500: Semiconductor device

Claims (4)

A semiconductor device comprising a central region in which circuit elements are formed and a first conductivity type semiconductor substrate partitioned into a peripheral region surrounding the outside of the central region,
A body region of a second conductivity type formed in a range facing the surface in the semiconductor substrate and continuously formed from the central region to the peripheral region;
A plurality of first trenches formed in the peripheral region and extending from the surface of the semiconductor substrate to penetrate the body region;
One or a plurality of second trenches are formed outside the first trench located on the outermost side of the peripheral region and extending from the surface of the semiconductor substrate to penetrate the body region. ,
A diffusion region of the second conductivity type is formed in a range surrounding the bottom of the first trench,
The plurality of first trenches are arranged from the central region side toward the outside with an interval where the depletion layer is connected when the circuit element is non-conductive,
A semiconductor device characterized in that an interval between a first trench located on the outermost side and a second trench adjacent to the first trench is an interval at which a depletion layer is not connected when a circuit element is non-conductive.   2. The semiconductor device according to claim 1, wherein a diffusion region of a second conductivity type is formed in a range surrounding the bottom of the second trench.   A plurality of the second trenches are provided, and the plurality of second trenches are arranged from the central region side toward the outside with a space where a depletion layer is not connected when the circuit element is non-conductive. The semiconductor device according to claim 2. A semiconductor device comprising a central region in which circuit elements are formed and a first conductivity type semiconductor substrate partitioned into a peripheral region surrounding the outside of the central region,
A body region of a second conductivity type formed in a range facing the surface in the semiconductor substrate and continuously formed from the central region to the peripheral region;
A plurality of first trenches formed in the peripheral region and extending from the surface of the semiconductor substrate to penetrate the body region;
One or a plurality of second trenches are formed outside the first trench located on the outermost side of the peripheral region and extending from the surface of the semiconductor substrate to penetrate the body region. ,
A diffusion region of the second conductivity type is formed in a range surrounding the bottom of the first trench,
The plurality of first trenches are arranged from the central region side toward the outside with an interval where the depletion layer is connected when the circuit element is non-conductive,
No diffusion region of the second conductivity type is formed in the area surrounding the bottom of the second trench ,
The distance between the outermost first trench and the second trench adjacent to the first trench is such that the depletion layer extends beyond the second trench when the circuit element is non-conductive. The semiconductor device is characterized in that the interval is prevented from being connected to the body region .

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