JP2014192433A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which has a structure for reducing field concentration, and which inhibits an increase in device size and an increase in manufacturing processes.SOLUTION: A semiconductor device comprises: a first conductivity type semiconductor substrate on which an element region and an outer peripheral region which surrounds the element region are defined on a principal surface; a second conductivity type first semiconductor region formed in the outer peripheral region so as to surround the element region; and a second conductivity type second semiconductor region which is formed at a depth including a bottom of the first semiconductor region and has an impurity concentration lower than an impurity concentration of the first semiconductor region which extends toward an outer periphery of the semiconductor substrate.

Description

  The present invention relates to a semiconductor device in which a structure for improving breakdown voltage is formed.

  In a semiconductor device, a guard ring, a RESURF, or the like is arranged as a structure for improving a breakdown voltage (hereinafter referred to as a “breakdown voltage structure”) on the outer periphery of an element region where a semiconductor element is formed. Thereby, the electric field concentration generated around the element region is relaxed, and the breakdown voltage of the semiconductor device is improved.

  By the way, in the case of a silicon (Si) substrate, the impurity concentration can be adjusted by thermal diffusion by annealing after impurity ion implantation. However, in the case of a silicon carbide (SiC) substrate, impurity diffusion hardly occurs even when heated to a high temperature. For this reason, it is necessary to adjust the concentration only with the ion implantation profile.

  For this reason, various methods have been proposed in order to apply a guard ring structure or a RESURF structure to a SiC substrate semiconductor device. For example, in the RESURF structure, a method has been proposed in which the breakdown voltage is improved by reducing the ratio of the area of the impurity implantation region per unit area toward the end of the chip (see, for example, Patent Document 1).

JP 2000-516767

  However, the depletion layer hardly spreads in the guard ring when reverse bias is applied. For this reason, there is a problem that a depletion layer spreads in the semiconductor film around the guard ring, reach-through occurs, and the breakdown voltage decreases. Further, since the depletion layer does not spread throughout the guard ring, only a part of the guard ring contributes to the breakdown voltage improvement. For this reason, in order to improve the breakdown voltage, it is necessary to arrange a large number of guard rings, which increases the size of the semiconductor device.

  On the other hand, when the RESURF structure is adopted, an ion implantation process for forming the RESURF is necessary. In particular, it is common to provide a concentration distribution in the resurf in order to enhance the effect of relaxing the electric field concentration. For this purpose, it is necessary to perform ion implantation for forming the resurf several times. Thereby, the manufacturing process of a semiconductor device increases.

  In view of the above problems, an object of the present invention is to provide a semiconductor device that has a structure that alleviates electric field concentration and that suppresses an increase in device size and an increase in manufacturing processes.

  According to one aspect of the present invention, the element region and the outer peripheral region surrounding the periphery of the element region are defined as a first conductivity type semiconductor substrate, and the periphery region surrounds the periphery of the element region. It is formed at a depth including the first semiconductor region of the second conductivity type to be formed and the bottom of the first semiconductor region, and is lower than the impurity concentration of the first semiconductor region extending toward the outer periphery of the semiconductor substrate. There is provided a semiconductor device comprising: a second semiconductor region of a second conductivity type having a concentration.

  According to the present invention, it is possible to provide a semiconductor device that has a structure that reduces electric field concentration and that suppresses an increase in device size and an increase in manufacturing processes.

It is a typical sectional view showing the composition of the semiconductor device concerning the embodiment of the present invention. 1 is an overall plan view of a semiconductor device according to an embodiment of the present invention. 1 is a partial plan view of a semiconductor device according to an embodiment of the present invention. It is a top view which shows the example of the resurf structure of related technology. It is sectional drawing which shows the example of the resurf structure of related technology. It is a top view which shows the example of the guard ring structure of related technology. It is sectional drawing which shows the example of the guard ring structure of related technology. It is a one-dimensional calculation model of a pn junction diode. It is a graph which shows the density | concentration profile of the calculation model shown in FIG. It is a graph which shows the relationship between the coordinate obtained using the calculation model shown in FIG. 8, and an electric field. It is a graph which shows the relationship between the coordinate and electric potential which were obtained using the calculation model shown in FIG. It is typical sectional drawing for demonstrating the state of the depletion layer formed in a guard ring. It is the graph which compared the relationship between the electric field and electric potential in the semiconductor device which concerns on embodiment of this invention, and a prior art example. 2 shows an example of the number of ion implantation stages of a semiconductor device according to an embodiment of the present invention. It is typical sectional drawing which shows the structure of the semiconductor device which concerns on the modification of embodiment of this invention.

  Next, an embodiment of the present invention will be described with reference to the drawings. In the following description of the drawings, the same or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the ratio of the thickness of each layer is different from the actual one. Therefore, specific thicknesses and dimensions should be determined in consideration of the following description. Moreover, it is a matter of course that portions having different dimensional relationships and ratios are included between the drawings.

  Further, the embodiments described below exemplify apparatuses and methods for embodying the technical idea of the present invention, and the embodiments of the present invention include the material, shape, structure, arrangement, etc. of the component parts. Is not specified as follows. The embodiment of the present invention can be variously modified within the scope of the claims.

As shown in FIG. 1, a semiconductor device 100 according to an embodiment of the present invention includes a silicon carbide substrate (SiC substrate) 1 and an element region 101 and an outer peripheral region 102 surrounding the element region 101 as a main surface. The first conductive type semiconductor substrate 10 defined, and the second conductive type main junction portion embedded in the upper part of the semiconductor substrate 10 so as to surround the element region 101 in the boundary region between the element region 101 and the outer peripheral region 102. 4 and a second conductivity type second semiconductor region disposed so as to include the guard ring 11 and the bottom portion of the adjacent guard ring 11 as a second conductivity type first semiconductor region disposed in multiple locations in the outer peripheral region 102. The electric field relaxation layer 8 is provided.
The main junction 4 is formed in a boundary region having a certain width including the boundary between the element region 101 and the outer peripheral region 102. Each of the first resurf region 51 to the third resurf region 53 has at least one guard ring 11 that surrounds the periphery of the main joint portion 4 and is embedded in the upper portion of the outer peripheral region 102. Further, a fourth resurf region that does not have the guard ring 11 is formed on the outer peripheral side of the third resurf region. That is, the guard ring 11 is not formed in the outermost resurf region in the resurf region.

  The first conductivity type and the second conductivity type are opposite to each other. That is, if the first conductivity type is n-type, the second conductivity type is p-type, and if the first conductivity type is p-type, the second conductivity type is n-type. Hereinafter, a case where the first conductivity type is n-type and the second conductivity type is p-type will be described as an example.

  A semiconductor substrate 10 of the semiconductor device 100 shown in FIG. 1 has a structure in which a semiconductor layer made of SiC is stacked on a SiC substrate 1. Hereinafter, a case where the semiconductor substrate 10 has a structure in which the low-concentration n-type epitaxial growth film 2 is formed on the high-concentration n-type SiC substrate 1 will be described as an example. A guard ring 11 is selectively embedded in a part of the upper portion of the epitaxial growth film 2.

  FIG. 1 shows an example in which the semiconductor device 100 is a Schottky barrier diode (SBD) in which the Schottky electrode 3 is disposed on the element region 101. That is, a Schottky junction is formed at the interface between the epitaxial growth film 2 and the Schottky electrode 3. When a reverse bias is applied, electric field concentration occurs at the electrode end 31 outside the Schottky electrode 3. For the purpose of electric field relaxation, the main junction 4 is disposed in the semiconductor substrate 10 near the electrode end 31 of the Schottky electrode 3. In order to form the main junction 4, a p-type semiconductor region is formed in the semiconductor substrate 10 by, for example, an ion implantation method. The side surface of the main joint 4 is in contact with the first RESURF region 51 at the outer end 41. The first RESURF region 51 to the fourth RESURF region 54 are arranged to alleviate the electric field concentration generated at the end portion 41 of the main joint portion 4.

  The electric field relaxation layer 8 is formed so as to include the main junction 4 and the bottoms of all adjacent guard rings in order to reduce the electric field concentration generated at the bottom of the guard ring 11. The electric field relaxation layer 8 extends further to the outer peripheral side than the guard ring 11 located at the outermost periphery, and this portion forms a fourth RESURF region 54. The electric field relaxation layer 8 is formed of a p-type semiconductor region that is thinner than the impurity concentration of the guard ring 11.

In the outer peripheral region 102, an oxide film 9 is disposed on the epitaxial growth film 2 up to the chip end 7. A back electrode 16 is disposed on the back surface of the SiC substrate 1.

Hereinafter, the RESURF regions arranged in the outer peripheral region 102 are collectively referred to as “RESURF region 5”. Although FIG. 1 shows an example in which four annular first resurf regions 51 to fourth resurf regions 54 are arranged in the outer peripheral region 102, the number of the resurf regions 5 is not limited to four.

  One of the RESURF regions 5 includes a guard ring 11. In the example shown in FIG. 1, the number of guard rings included in the first resurf region 51 is one, but the number of guard rings included in the second resurf region 52 and the third resurf region 53 is five. The fourth RESURF region includes only the electric field relaxation layer 8 and does not include the guard ring 11.

  The width of the guard ring 11 in the RESURF region 5 is made narrower as the RESURF region 5 has a longer distance from the element region 101. However, the width of the guard ring 11 is substantially the same in the same resurf region 5. Details of the width of the guard ring 11 will be described later.

  FIG. 2 shows a plan view of the entire semiconductor device 100. An outer peripheral region 102 disposed around the element region 101 is a breakdown voltage structure region in which a breakdown voltage structure is disposed. As shown in FIG. 2, the width of the outer peripheral region 102 is d. In addition, illustration of the guard ring 11 is abbreviate | omitted in FIG.

FIG. 3 is an enlarged plan view of a part of the upper right portion of FIG. Resurf regions 51 to 54 are formed so as to surround the main joint 4. A plurality of guard rings having different widths are formed around the main joint portion 4, and a fourth resurf region 54 formed of the electric field relaxation layer 8 is formed on the outer periphery of the outermost guard ring 11. ing.

  Here, an example in which the related art RESURF structure or guard ring structure is employed as the breakdown voltage structure for the SBD in which the element region 101 and the outer peripheral region 102 are defined as in the semiconductor device 100 shown in FIG. 3 will be described. In other words, an outer peripheral region 102 is disposed so as to surround the element region 101 where the Schottky electrode 3 is disposed and in which a breakdown voltage structure such as a RESURF structure or a guard ring structure for improving the breakdown voltage of the SBD is formed.

  An example in which the RESURF structure is adopted as the pressure-resistant structure is shown in FIGS. 4 and 5, and an example in which the guard ring structure is adopted is shown in FIGS. In any of the examples employing the RESURF structure or the guard ring structure, the semiconductor substrate 10 has a structure in which the epitaxial growth film 2 is formed on the SiC substrate 1, and the Schottky electrode 3 is disposed on the epitaxial growth film 2. A Schottky junction is formed at the interface between the epitaxial growth film 2 and the Schottky electrode 3. The reverse bias V is applied between the Schottky electrode 3 and the back electrode 16 so that the back electrode 16 has a positive potential.

  When reverse bias is applied, electric field concentration occurs at the electrode end 31 of the Schottky electrode 3. For the purpose of electric field relaxation, a p-type semiconductor region is formed in the semiconductor substrate 10 in the vicinity of the electrode end 31 of the Schottky electrode 3 by the ion implantation method, and the main junction 4 is formed.

  In the example employing the RESURF structure, as shown in FIGS. 4 and 5, the first RESURF region 51 a to the fourth RESURF region 54 a are concentrically continuous along the main surface in the outer peripheral region 102 outside the main joint 4. Are arranged. On the other hand, in the example employing the guard ring structure, as shown in FIGS. 6 and 7, a plurality of guard rings 11 a are concentrically separated from each other along the main surface in the outer peripheral region 102 outside the main joint portion 4. Has been placed.

At the time of reverse bias, a depletion layer spreads around the pn junction. The magnitude of the electric field in this depletion layer is maximum at the pn junction. Such a depletion layer / electric field / voltage relationship is generally represented by the Poisson equation shown in the following equation (1):

∇ ² φ (x, y, z) = ρ (x, y, z) / ε (1)

In equation (1), φ (x, y, z) is the potential at coordinates (x, y, z), ρ (x, y, z) is the electric field density at coordinates (x, y, z), and ε is the dielectric Rate.

  8 to 11 show a one-dimensional calculation model and calculation results. The calculation model shown in FIG. 8 is a one-dimensional representation of a pn junction diode, and also shows an electric circuit in a state where a reverse bias V is applied. At both ends of the pn junction diode, a back electrode 16 and a Schottky electrode 3 are respectively formed on the back surface of the SiC substrate 1 and the p-type semiconductor layer 17 on the surface of the n-type epitaxial growth film 2.

In the one-dimensional model shown in FIG. 8, the Poisson equation is also simplified as shown in equation (2):

∂ ² / ∂x ² (φ (x)) = ρ (x) / ε = eN (x) / ε (2)

Here, the impurity concentration of the depletion layer = the charge density, and the impurity concentration is a constant value in the depth direction, and calculation is performed as a step junction.

The impurity concentration of the n-type SiC substrate 1 was 1 × 10 ¹⁸ cm ⁻³ , the thickness of the n-type epitaxial growth film 2 was t1, and the impurity concentration was 8.5 × 10 ¹⁵ cm ⁻³ . A p-type semiconductor layer 17 having a depth t2 and a concentration of 1 × 10 ¹⁷ cm ⁻³ is formed on the surface of the epitaxial growth film 2. Here, the film thickness t1 was 12 μm, and the depth t2 was 0.8 μm. FIG. 9 shows an impurity concentration profile of the pn junction diode shown in FIG. 9 indicates the position in the direction perpendicular to the pn junction, and the origin is the boundary between the SiC substrate 1 and the epitaxially grown film 2. In FIG. 9, the value at the SiC substrate 1 is indicated by a one-dot chain line A, the value at the epitaxial growth film 2 is indicated by a solid line B, and the value at the p-type semiconductor layer 17 is indicated by a broken line C (the same applies hereinafter).
In the pn junction diode to which the reverse bias is applied, the electric field is maximum at the pn junction as shown in FIG. When the impurity concentration is high, the depletion layer does not spread so much, and the potential difference to be distributed is small. When the impurity concentration is low, the depletion layer spreads, so that the potential difference to be distributed is large. A design that can increase the applied voltage when the maximum electric field is the same is a high withstand voltage design.

  The p-type semiconductor layer 17 connected to the Schottky electrode 3 is entirely depleted. For this reason, as shown in FIG. 10, the depletion layer reaches the Schottky electrode 3 (reach-through), and an electric field of about 1 MV / cm is generated at the interface of the Schottky electrode 3. Further, since the entire n-type region of the epitaxial growth film 2 is also depleted, the depletion layer reaches through to the SiC substrate 1 and an electric field of about 0.65 MV / cm is generated at the interface between the epitaxial growth film 2 and the SiC substrate 1. doing.

  Note that the voltage drop can be estimated by comparing the areas of the n-type epitaxial growth film region and the p-type semiconductor layer region in FIG. As shown in FIG. 11, most of the voltage drop occurs in the epitaxial growth film 2 and almost no voltage drop occurs in the SiC substrate 1. The p-type semiconductor layer 17 having a thickness of 0.8 μm is all depleted and an electric field is also present in the electrodes, whereas the width of the depletion layer of the SiC substrate 1 is 0.05 μm, and an electric field is not present in the undepleted portion. There is no.

As described above, in the one-dimensional model, when a reverse bias is applied to the pn junction, depletion layers are formed at both ends of the junction, and the electric field is highest at the junction. In addition, an electric field is generated when depleted, but if it is not depleted, there is no electric field, and it can be understood that the electric field can be suppressed if the impurity concentration is 1 × 10 ¹⁸ cm ⁻³ or more.

  Here, the guard ring structure shown in FIGS. 6 and 7 will be described. Since the interface between the main junction 4 and the epitaxial growth film 2 is a pn junction, a depletion layer is generated at the interface between the main junction 4 and the epitaxial growth film 2 when a reverse bias is applied.

  When the main junction 4 is completely depleted when a reverse bias is applied, an electric field is generated at the interface of the Schottky electrode 3, for example, as shown in FIG. The electric field generation of the electrode 3 seems to be no problem in the one-dimensional model. However, since FIG. 10 is a calculation result regarding the one-dimensional model, it does not correspond to an end such as the electrode end 31.

  If a depletion layer is present at the electrode end 31, an abrupt potential gradient at the electrode end 31 and an electric field several times greater than that at a location other than the electrode end 31 of the electrode 3 are generated, and the breakdown voltage decreases. In order to prevent electric field concentration at the electrode end 31, a main junction 4 made of a high-concentration p-type semiconductor and having a thickness sufficient to prevent complete depletion is required.

For example, if the maximum concentration of the p-type impurity in the main junction 4 is about 1.4 × 10 ¹⁸ cm ⁻³ , the main junction 4 is hardly depleted. For this reason, the electric field of the electrode end 31 is zero. When the guard ring structure is employed, the p-type impurity concentration can be made the same between the guard ring 11a and the main junction portion 4. For this reason, the guard ring 11 a can be formed simultaneously with the main joint 4. In this case, the injection depth of the guard ring 11a is the same as the depth of the main joint 4.

  By forming the high-concentration main junction 4, the electric field concentration at the electrode end 31 of the Schottky electrode 3 is almost eliminated, but the electric field is concentrated at the outer end 41 of the main junction 4. For this reason, it is necessary to alleviate the electric field concentration at the end 41 of the main joint 4. Below, the method of relieving the electric field concentration of the edge part 41 with a guard ring is demonstrated.

  The depletion layer formed around the pn junction is thin when the impurity concentration is high and thick when the impurity concentration is low. For example, a depletion layer extends in the n-type epitaxial growth film region around the main junction 4 and the guard ring 11, and the depletion layer extending from the guard ring 11 reaches the adjacent guard ring 11.

  Here, the function of the guard ring 11a will be described in more detail with reference to FIG. In the pn junction 21 on the low potential side of each guard ring 11a, the p layer has a higher potential and no depletion layer is formed, so that no electric field is generated. There is no potential difference in the guard ring that is not depleted. On the other hand, since the n layer has a higher potential in the high potential side pn junction 20 of each guard ring 11a, the depletion layer spreads in the n-type epitaxial growth film 2, and the depletion layers are sequentially connected toward the high potential side guard ring 11a. However, the potential difference from the back electrode 16 gradually decreases.

  However, since a depletion layer spreads greatly in the epitaxial growth film 2, reach through is likely to occur in the epitaxial growth film 2. For this reason, there is a problem that the withstand voltage is lower than that of the RESURF structure.

  Further, as described above, the spread of the depletion layer in the guard ring 11a is very small, and there is no potential difference in the non-depleted portion in the guard ring 11a. For this reason, when the guard ring 11a is used in a pressure-resistant structure, the width d of the outer peripheral region 102 of the chip becomes wide because it is necessary to arrange a large number of guard rings 11a, which also causes an increase in chip size. .

  Next, the RESURF structure shown in FIGS. 4 and 5 will be described. When the RESURF structure is adopted as the breakdown voltage structure, the p-type semiconductor region of the outer peripheral region 102 is divided into the main junction 4 and the RESURF region 5a. As in the case of the guard ring structure, the RESURF region 5a is arranged in order to reduce the electric field concentration at the end portion 41 of the main joint portion 4. Further, in order to alleviate the electric field concentration of the main junction 4, the depth of the RESURF region 5 a needs to be the same as the depth of the main junction 4 as in the guard ring structure. When the RESURF structure is used, the implantation concentration is set so that the depletion layer spreads moderately inside the RESURF region 5a, so that the p-type semiconductor region is continuous from the main junction 4 to the end of the RESURF region 5a.

  4 and 5 will be described in more detail. The resurf region 5a is divided into four regions from a first resurf region 51a to a fourth resurf region 54a. The first resurf region 51a is the portion with the highest impurity concentration in the resurf region 5a, and the fourth resurf region 54 is the portion with the lowest concentration in the resurf region 5a.

The concentration of the RESURF region 5a is doped with a p-type impurity, for example, as expressed in the following formulas (3) to (5):

N2 = N1 × 0.75 (3)
N3 = N1 × 0.5 (4)
N4 = N1 × 0.25 (5)

Here, N1 is the impurity concentration of the first resurf region 51a, N2 is the impurity concentration of the second resurf region 52a, N3 is the impurity concentration of the third resurf region 53a, and N4 is the impurity concentration of the fourth resurf region 54a.

  In the RESURF region 5a, since the depletion layer spreads over the entire RESURF region, the width d of the outer peripheral region 102 can be reduced, and the chip size can be reduced as compared with the guard ring structure. In addition, since the depletion layer spreads inside the resurf region 5a, the spread of the depletion layer in the epitaxial growth film 2 is suppressed. For this reason, reach-through is unlikely to occur in the epitaxially grown film 2, and an element design with a higher breakdown voltage is possible as compared with the guard ring structure.

  By the way, in the case of a Si substrate, the impurity concentration can be adjusted by thermal diffusion by heating at about 900 ° C. after performing ion implantation by appropriately adjusting the implantation area. However, in the case of a SiC substrate, impurity diffusion hardly occurs even when heated to a high temperature. For this reason, it is necessary to adjust the concentration only with the ion implantation profile.

  When the resurf structure is employed in the SiC substrate 1 that cannot use the thermal diffusion of impurities, it is necessary to perform ion implantation of the high concentration main junction 4 and ion implantation of the low concentration resurf region 5 in separate steps. When the resurf region 5 is composed of a plurality of regions having different impurity concentrations for optimizing the withstand voltage structure, a plurality of ion implantations are required to form the resurf region 5. Thereby, the width of the outer peripheral region can be further reduced, but there is a problem that the number of ion implantations further increases.

In the related art guard ring structure, when a reverse bias is applied, the depletion layer spreading from each guard ring to the high potential side contacts the adjacent guard ring, and the guard rings are connected by the depletion layer, thereby concentrating the electric field. Alleviated. At this time, since the depletion layer hardly expands in the guard ring, it is necessary to extend the depletion layer long in the epitaxial growth film in the direction in which the guard ring on the high potential side is arranged. At this time, a depletion layer spreads in the epitaxial growth film also in the direction of the SiC substrate, and reach-through is likely to occur. For this reason, the guard ring structure of the related art has a lower withstand voltage than the RESURF structure.
In general, such a guard ring structure is formed with a relatively high impurity concentration in order to ensure the withstand voltage performance of the semiconductor element. For this reason, when a high voltage is applied to the semiconductor element, there are very few depletion layers extending in the guard ring, so that problems such as an increase in chip size and a strong electric field are likely to occur at the bottom end of the guard ring. There is a problem.

  However, in the semiconductor device 100 shown in FIG. 1 according to the present invention, the electric field relaxation layer 8 having an impurity concentration lower than that of the guard ring 11 is disposed so as to include the bottom portion of the adjacent guard ring 11, and the RESURF regions 51 to 54. Is forming. In other words, the electric field relaxation layer 8 having an impurity concentration lower than that of the guard ring 11 is disposed at the bottom end of the guard ring where a strong electric field is likely to be generated in the guard ring structure, thereby mitigating the electric field concentration at that location. Further, since the impurity concentration of the electric field relaxation layer 8 is lower than that of the guard ring 11, a depletion layer also extends in the electric field relaxation layer 8, and the width d of the outer peripheral region 102 is narrower than that of the related art guard ring structure. be able to. Thereby, an increase in chip size can be suppressed.

  Furthermore, in the semiconductor device 100 according to the present invention, the width of the guard ring 11 included in the RESURF region 5 is narrower as the RESURF region 5 farther from the element region 101. For this reason, unlike the RESURF structure of the related art, it is not necessary to form a plurality of regions having different impurity concentrations in the RESURF region. For this reason, an increase in the number of ion implantations can be suppressed.

The width of the guard ring 11 and the gap between the guard rings 11 in the second resurf region 52 to the third resurf region 53 are preferably defined so as to satisfy the following relationship. That is, the width D _X of the guard ring 11 in the Xth RESURF region and the gap W _X between the adjacent guard rings 11 satisfy the relationship of the following expressions (6) and (7):

D _X = P × ND _X / ND1 (6)
W _X = P−D _X (7)

Here, X is an integer of 2 or more. P is the arrangement pitch of the guard rings 11, ND _X is the spatial modulation concentration of the X-th resurf region 5 from the element region 101, and ND 1 is the spatial modulation concentration of the first resurf region 51 closest to the element region 101. For example, the arrangement pitch P is set to 2.5 μm, and the width and gap of the guard ring 11 of the semiconductor device 100 shown in FIG. 1 are set as follows. That is, the width D ₁ of the guard ring 11 in the first RESURF region 51 is set to 2.5 μm. The width D ₂ of the guard ring 11 in the second RESURF region 52 is 1.875 μm, and the gap W ₂ between the guard rings 11 is 0.625 μm. The width D ₃ of the third resurf region 53 is 1.25 μm, and the gap W ₃ between the guard rings 11 is 1.25 μm.

By arranging the electric field relaxation layer 8 so as to define the width D _X of the guard ring 11 and the gap W _X between the adjacent guard rings 11 and to include the bottom of the adjacent guard rings 11 as described above. The main joint 4 and the guard ring 11 are electrically short-circuited with each other. Therefore, the spatial modulation density similar to the RESURF structure of the related art shown in FIGS. 4 and 5 can be set. Thereby, it is possible to realize a breakdown voltage equivalent to the RESURF structure of the related art with the equivalent width d of the outer peripheral region 102 while suppressing the number of ion implantations.

FIG. 13 shows the relationship between the electric field and the potential at the outer periphery when the electric field relaxation layer 8 is provided and when it is not. FIG. 13A shows the relationship between the electric field and the potential at the outer periphery of the semiconductor device 100 according to the embodiment of the present invention. FIG. 13B shows the relationship between the electric field and the potential in the outer peripheral portion of the conventional example that does not include the electric field relaxation layer 8.
Comparing the two figures, it can be seen that both potentials have risen to 1.5 kV. In this case, in the conventional example of (b), the maximum electric field value is 1.6 MV / cm, whereas in the semiconductor device 100 according to the embodiment of the present invention of (a), the maximum electric field value is 1. 5 MV / cm, which is lower than the conventional example. In addition, the electric field in the region of the main junction 4 is about 1.0 MV / cm in the conventional example, whereas in the semiconductor device 100 according to the embodiment of the present invention, the electric field is about 0.5 MV / cm. The semiconductor device 100 according to the embodiment is lower.
Further, in the first resurf region to the fourth resurf region (spatial modulation unit), the semiconductor device 100 according to the embodiment of the present invention has less electric field concentration than the conventional example because the amplitude of the electric field value is small. You can see that it is suppressed. Thus, in the semiconductor device 100 according to the embodiment of the present invention, the electric field relaxation layer 8 is disposed so as to include the bottoms of the adjacent guard rings 11, so that the withstand voltage is higher than that of the conventional example. Recognize.

The breakdown voltage structure formed in the outer peripheral region 102 of the semiconductor device 100 according to the embodiment of the present invention can be applied to other semiconductor devices that require a similar breakdown voltage structure. For example, a diode with an MPS (Merged PiN Schottoky) structure with a Schottky junction and a pn junction, or JBS (Junction-Barrier)
It can be applied to a diode with a Shottky structure and is a metal-oxide-semiconductor MOS-FET.
It can also be applied to pressure-resistant structures such as Field-Effect-Transistor.

  As described above, in the semiconductor device 100, the number of ion implantations can be significantly reduced as compared with the RESURF structure of the related art. This effect is significant when manufacturing the high-quality semiconductor device by making the outer peripheral region 102 smaller and setting the impurity concentration of the RESURF region more finely.

  In the above example, the RESURF area is divided into four parts, the first RESURF area 51 to the fourth RESURF area 54, but the RESURF area may be further finely divided. By finely dividing the RESURF region, the area of the RESURF region can be reduced. Alternatively, by dividing the RESURF region more finely without changing the area of the RESURF region, it is possible to absorb manufacturing variations such as ion implantation amount, epitaxial concentration and thickness.

<Modification>
FIG. 15 shows a modification according to the embodiment of the present invention. Compared to the embodiment of the present invention, the only difference is that the guard ring 11 does not reach the surface of the semiconductor substrate 10, and the other configuration is the same as that of the embodiment of the present invention.

In the case of a silicon carbide (SiC) substrate, impurity diffusion hardly occurs even when heated to a high temperature. Therefore, as shown in FIG. 1, when forming the guard ring 11 having a predetermined depth from the surface of the semiconductor substrate 10, it is generally formed by implanting ions in multiple stages. FIG. 14 shows an example, in which the vertical axis represents the impurity concentration (cm ⁻³ ) and the horizontal axis represents the depth (μm) from the surface of the silicon carbide (SiC) substrate.
In FIG. 14, the number of implantation stages when the guard ring 11 is formed by a p-type semiconductor layer having a depth of 0.1 μm to 0.8 μm from the surface of the semiconductor substrate 10 and an average impurity concentration of 1 × 10 ¹⁸ cm ^−3. It is shown. If the impurity concentration of the n-type epitaxial growth film 2 is 8.5 × 10 ¹⁵ cm ⁻³ , the pn junction of the guard ring 11 exists at a depth of 1.2 μm. Four mountain-shaped graphs having apex at a position slightly higher than the impurity concentration of 1 × 10 ¹⁸ cm ⁻³ are shown, and p-type is obtained by implanting a total of four stages in the depth direction with different implantation energies. It can be seen that the semiconductor layer (guard ring 11) is formed.

  On the other hand, in the modification according to the embodiment of the present invention shown in FIG. 15, the guard ring 11 does not reach the surface of the semiconductor substrate 10, and the p-type semiconductor layer is between the guard ring 11 and the surface of the semiconductor substrate 10. Is not formed. For this reason, when forming the guard ring 11, the number of ion implantation stages can be reduced. For example, in the embodiment according to the present invention shown in FIG. 1, a total of four stages of ion implantation are performed, whereas in the modification shown in FIG. 15, ion implantation is not necessary on the surface side of the semiconductor substrate 10. Therefore, it is possible to omit the two-stage implantation on the side close to the surface of the semiconductor substrate 10 and to perform only the two-stage implantation on the deep side. That is, a total of two stages of injection can be performed.

(Other embodiments)
As described above, the present invention has been described according to the embodiments. However, it should not be understood that the descriptions and drawings constituting a part of this disclosure limit the present invention. From this disclosure, various alternative embodiments, examples and operational techniques will be apparent to those skilled in the art.

  For example, although the example in which the pitch of the guard ring 11 is substantially the same over the entire surface of the outer peripheral region 102 has been described above, the pitch of the guard ring 11 may be changed for each RESURF region. Further, the case where the SiC substrate 1 is an n-type substrate has been described as an example, but a p-type substrate is used for the SiC substrate 1, and an n-type semiconductor is used for the main junction 4, the guard ring 11, and the electric field relaxation layer 8. The present invention can also be applied to the case where the semiconductor device 100 is configured.

  As described above, the present invention naturally includes various embodiments not described herein. Therefore, the technical scope of the present invention is defined only by the invention specifying matters according to the scope of claims reasonable from the above description.

DESCRIPTION OF SYMBOLS 1 ... SiC substrate 2 ... Epitaxial growth film 3 ... Schottky electrode 4 ... Main junction 5 ... RESURF region 7 ... Chip edge 8 ... Electric field relaxation layer 9 ... Oxide film 10 ... Semiconductor substrate 11 ... Guard ring 16 ... Back electrode 17 ... p Type semiconductor layer 20 ... High potential side pn junction 21 ... Low potential side pn junction 31 ... Electrode end 41 ... End portion 51 ... First resurf region 52 ... Second resurf region 53 ... Third resurf region 54 ... Fourth resurf region 100 ... Semiconductor device 101 ... Element region 102 ... Outer peripheral region

Claims (6)

A semiconductor substrate of a first conductivity type in which an outer peripheral region surrounding the element region and the periphery of the element region is defined as a main surface;
A first semiconductor region of a second conductivity type formed in the outer peripheral region so as to surround the periphery of the element region;
A second conductivity type second semiconductor region formed at a depth including the bottom of the first semiconductor region and having a concentration lower than the impurity concentration of the first semiconductor region extending toward the outer periphery of the semiconductor substrate;
A semiconductor device comprising:   A plurality of the first semiconductor regions are formed, and an end portion on the outer peripheral side of the second semiconductor region is formed at a position closer to the outer peripheral end of the semiconductor substrate than the first semiconductor region. The semiconductor device according to claim 1. 3. The semiconductor device according to claim 1, wherein a plurality of the first semiconductor regions are formed, and a width of the first semiconductor region decreases toward an outer periphery of the semiconductor substrate. 4. The device according to claim 1, wherein a plurality of the first semiconductor regions are formed, and an interval between the adjacent first semiconductor regions increases toward the outer periphery of the semiconductor substrate. Semiconductor device.   The second semiconductor region includes a first region and a second region, and a plurality of the first semiconductor regions are formed in the first region and the second region, and the first semiconductor region is formed in each region. The semiconductor device according to claim 1, wherein the intervals between the semiconductor regions are substantially the same. 6. The semiconductor device according to claim 1, wherein the first semiconductor region does not reach a main surface of the semiconductor substrate.