JP5101985B2 - Junction barrier Schottky diode - Google Patents

Description

  The present invention relates to a high breakdown voltage semiconductor rectifier using silicon carbide as a base material, and more particularly to a junction barrier Schottky diode.

  In the semiconductor power element, the on-resistance and the withstand voltage have a trade-off relationship defined by the band gap of the substrate material. Therefore, in order to exceed the performance of a silicon element widely used as a power element, it is effective to use a substrate material having a band gap larger than that of silicon. In particular, silicon carbide (SiC) has characteristics such as a sufficiently large band gap of about three times that of silicon, easy formation of p-type and n-type conductivity types, and formation of an oxide film by thermal oxidation. For this reason, there is a possibility that a high-performance switching element or diode can be realized, and it has attracted much attention.

  In particular, diodes have a lower on-resistance and larger capacity than switching elements. In addition, unlike a Si diode, an SiC diode, which can be a Schottky barrier diode (hereinafter abbreviated as SBD (Schottky Barrier Diode)), can produce a high breakdown voltage of 3 kV or more, so that not only conduction loss but also switching loss is reduced. It is possible. However, SBD has a problem in that the leakage current is large because the Schottky interface is exposed to a high electric field during reverse bias.

  On the other hand, a structure called a junction barrier Schottky diode (hereinafter abbreviated as JBS (Junction Barrier Schottky Diode)) has been proposed as a structure capable of relaxing the electric field at the Schottky interface and reducing the leakage current. This is a structure having both a pn junction region and a Schottky junction region on the anode side. At the time of reverse bias, the depletion layer extends from the pn junction region, and the electric field in the Schottky junction region can be relaxed. This structure is illustrated in FIG. In FIG. 11, 3 indicates an n − drift layer, 4 indicates an n + cathode region (substrate), 5 indicates a cathode electrode, and 6 indicates an anode electrode. Reference numeral 1 constituting the pn junction indicates a region having a constant concentration in the p + region, and 2 indicates a region having a concentration profile in the p + region. While JBS can reduce the leakage current, the on-current is reduced because the area of the Schottky diode region that operates at a low voltage is small. That is, when the leakage current is reduced, the on-current is reduced, and it can be said that these are in a trade-off relationship. As a means for improving this trade-off, it is effective to make the pn junction part a trench type and to optimize the depth, angle and interval of the pn junction part. FIG. 12 shows a cross-sectional structure diagram of a trench type JBS. A p + region 1 is formed at the bottom and side wall of trench 7. An example of a trench type JBS is disclosed in US Pat. No. 5,262,669 (Patent Document 1). In FIG. 12, the same reference numerals as those in FIG. 11 denote the same parts.

US Patent 5262669

  However, since the trench type JBS can generally form a pn junction for electric field relaxation by low energy ion implantation, the profile of ion implantation becomes steep, the electric field concentrates at the pn junction at the trench corner, and the breakdown voltage is reduced. There was a difficulty of lowering.

  The essence of the present invention is that, in the pn junction region of the JBS structure, the inclination of the pn junction at the side of the p-type region is steeper than the slope of the pn junction at the bottom of the p-type region. . Note that the inclination of the junction forming the pn junction is important, not the position of the pn junction itself in the semiconductor layer. Also, the thickness of the p-type region where the impurity concentration present at the bottom of the p-type region forming the pn junction is not constant is larger than the thickness of the p-type region where the impurity concentration present at the side of the p-type region is not constant. In many cases, however, the inclination of the junction forming the pn junction is important in the gist of the invention.

An example of a specific form of the present invention is as follows.
That is, as described above, the first main form is alternately arranged on the surface of the substrate having the first conductivity type made of silicon carbide on the drift layer (silicon carbide layer) of the first conductivity type and on the surface of the drift layer. In a junction barrier Schottky diode having a schottky and a pn junction region and having an external contact as an anode and a cathode, the side portion of the p-type region is compared with the inclination of the pn junction at the bottom of the p-type region. This is characterized in that the inclination of the pn junction is steeper. In this case, in addition, in this example, the thickness of the p-type region in which the impurity concentration present at the bottom of the p-type region forming the pn junction is not constant, but the impurity concentration present in the side portion of the p-type region is not constant. Thicker than the thickness of the p-type region.

  The second main form is that, in the first form, a trench is formed in the drift layer, and a p-type region of a pn junction is formed in the trench. This form is practically the most useful form in order to make the inclination of the pn junction steep.

  The third main form is the junction main Schottky diode in the first and second main forms, wherein the concentration of the region sandwiched between the p regions of the drift layer forming the pn junction is higher than that of the drift layer. It is expensive.

  In the fourth embodiment, in the first to third embodiments, the slope of the pn junction at the side of the p-type region is steeper than the slope of the pn junction at the bottom of the p-type region. It is a form.

  The present invention can secure a high breakdown voltage of a pn junction in JBS and can secure a large on-current. That is, more specifically, by applying the present invention, the trade-off relationship between the leakage current and the on-current can be improved, and a large on-current can be secured at a low leakage current.

  As described above, in the present invention, in the pn junction region of the JBS structure, since the inclination of the pn junction at the bottom of the p-type region is made gentle, the electric field concentrates at the corner of the p-type region and the breakdown voltage decreases. Can be suppressed. On the other hand, since the pn junction on the side of the p-type region is steep, that is, the slope of the pn junction on the side of the p-type region is steep, it does not function as an electric field relaxation layer or a current path. The p-type region having an impurity concentration can be narrowed, and the trade-off between leakage current and on-current can be improved. Hereinafter, the present invention will be described more specifically in accordance with embodiments of the present invention.

  FIG. 1 shows a cross-sectional structure diagram of a trench type JBS according to a first embodiment of the present invention. FIG. 2 shows a plan view of this embodiment. In FIG. 1, the reference numerals 1 to 6 indicate the same parts as those shown in FIG. That is, reference numeral 1 denotes a region having a constant impurity concentration in the p + region, 2 denotes a region having an impurity concentration profile in the p + region, 3 denotes an n − drift layer (n-SiC layer), 4 denotes Denotes an n + cathode region (n + SiC region), 5 denotes a cathode electrode, and 6 denotes an anode electrode. In the general description, the p-type region is used to form the pn junction. In the embodiment, the p-type region has an impurity concentration of so-called p +. For this reason, in the following examples, these p-type regions will be referred to as p + regions.

  1 is a cross-sectional view taken along line AA in FIG. A pn junction region is formed at the interface between the n − drift layer 3 and the p + region 2 provided therein. A junction barrier is formed at the interface between the n − drift layer 3 and the anode electrode 6 on the upper surface of the region sandwiched between these pn junction regions.

  In FIG. 1, the inclination of the pn junction constituted by the p + region 2 at the bottom of the trench is gentler than the inclination of the pn junction constituted by the p + region at the trench side wall, so that an electric field is applied to the trench corner portion. It is possible to prevent the breakdown voltage from being reduced due to the concentration.

  On the other hand, since the width w1 of the p + region at the trench side wall is steep, the electric field at the Schottky interface can be effectively relaxed while ensuring a sufficient current path. This is because if the pn junction at the trench side wall portion is gentle, the low-concentration p region that does not function as a current path nor an electric field relaxation layer becomes wide.

  In the case of this example, the p + region 2 has the width (w1) of the region 2 having the impurity concentration profile on the side wall side of the trench 7 and the width (w2) of the region 2 having the impurity concentration profile on the bottom side of the trench 7. ) It is thinner. That is, the relationship of width w1 (side wall side of trench 7) <width w2 (bottom side of trench 7) is satisfied. However, as described above, the inclination of the junction forming the pn junction is the basis of the present invention.

  The planar configuration of the junction barrier Schottky diode may be a pattern in which p-type regions as shown in FIG. 2 are arranged in a line or a dot pattern as shown in FIG. In the case of FIG. 3, FIG. 1 corresponds to a cross-sectional view along the line BB. Of course, in these embodiments, the basic configuration of the present invention is the same. 1 and 2 is a termination region provided in the periphery of the element. The termination region is provided in the peripheral portion of the element to reduce the electric field, and includes, for example, a JTE (Junction Termination Extension) structure and a FLR (Field Limiting Ring) structure. As for this configuration itself, such a conventional one is sufficient, and it is not directly related to the essence of the present invention. Therefore, further explanation is omitted. In the cross-sectional view, only the main part of the diode is shown, and the peripheral part including the termination region is omitted. 2 and 3, the same reference numerals as those in FIG. 1 denote the same parts.

  Next, the manufacturing method concerning a present Example is demonstrated using (d) from (a) of FIG. Also in FIG. 4, only the main part of the diode is shown, and the peripheral part including the above-described termination region is omitted. In this embodiment, a withstand voltage of 3.3 kV is assumed.

A SiC substrate 11 having an n-SiC epitaxial layer formed on a SiCn + substrate is prepared. As the impurity concentration of the substrate, a range of about 1 × 10 ¹⁸ cm ⁻³ to 1 × 10 ¹⁹ cm ⁻³ is frequently used. As the main surface of the SiC substrate, the (0001) plane and the (000-1) plane are frequently used, and the (11-20) plane may be used in some cases. The present invention can achieve the effect regardless of the selection of these main surfaces of the SiC substrate.

The specifications of the n-epitaxial layer 3 on the SiC substrate are as follows: the thickness is 5 μm to 30 μm, the impurity concentration is the same conductivity type as the substrate, and the range is about 1 × 10 ¹⁵ cm ⁻³ to 2 × 10 ¹⁶ cm ^−3. Is frequently used. Further, it is preferably about 1 × 10 ¹⁵ cm ^{−3 to} 3 × 10 ¹⁵ cm ⁻³ .

First, a termination region around the element is formed in the SiC substrate 11. This termination region is not shown in FIG. The impurity concentration in the termination region is generally about 1 × 10 ¹⁶ cm ^{−3 to} 5 × 10 ¹⁷ cm ⁻³ and is lower than the other regions.

  Next, a trench 7 is formed on the epitaxial layer 3 by usual lithography and dry etching (FIG. 4A). The depth of the trench is about 0.5 μm to 2.0 μm. Since SiC is a chemically stable material and requires a large amount of power for dry etching, a hard mask such as SiO 2 or SiN is desirable for the mask 8. The interval between adjacent pn junctions is about 2 μm to 20 μm. Of course, this interval is determined by the characteristics required of the finished device.

  Using the dry etching hard mask 8 as it is, the first p + region 1 and the second p + region 2 are formed in the trench 7 by ion implantation. Of the P + region 1 and the P + region 2, the bottom 12 of the trench 7 is formed by vertical ion implantation 14 (FIG. 4C), and the side 13 of the trench is formed by oblique ion implantation 15 (FIG. 4 (FIG. 4). b)). Al or boron is used as the p-type dopant. Of these, the trench side portion 13 can make the impurity profile of the p-type region steep by implanting oblique ion implantation from the low energy side. This is because, by damaging the crystal lattice by low energy implantation, it is possible to suppress the phenomenon of channeling in which ions pass through the crystal lattice and enter deeply in the subsequent high energy implantation. In the sense of damaging the crystal lattice, it is also effective to implant an inert gas element such as Ar, which is not related to electrical conduction, in advance. According to such ion implantation, the width of the pn junction can be reduced. Furthermore, the inclination of the pn junction can be made steep.

It can be considered that damaging the crystal lattice affects the electrical characteristics of the device. However, since the (11-20) plane which is generally the plane orientation of the trench sidewall is easily recovered by defect recovery annealing, there is no problem. As the implantation conditions, for example, the dopant is Al, the implantation angle is 30 degrees, 20 keV, 2 × 10 ¹³ cm ⁻² , 50 keV, 7 × 10 ¹³ cm ⁻² , 100 keV, 1.2 × 10 ¹⁴ cm ⁻² , By implanting in the order of 150 keV and 1 × 10 ¹⁴ cm ⁻² , the width of the region 1 having a constant impurity concentration in the p + region is 0.15 μm, and the region 2 having the impurity concentration profile in the p + region is formed. The width can be about 0.2 μm.

In the trench side portion, in general, the width of the region 1 having a constant impurity concentration in the p + region is:
The width of the region 2 having an impurity concentration profile in the p + region is about 0.1 μm to about 0.3 μm.

On the other hand, the bottom of the trench can be implanted with several kinds of energy, and the profile of the p region can be made gentle by decreasing the dose as the energy increases. It is also effective to inject in order from higher energy. As the implantation conditions, for example, the dopant is Al and the implantation angle is vertical. (1) 20 keV, 2 × 10 ¹³ cm ⁻² , (2) 50 keV, 7 × 10 ¹³ cm ⁻² , 100 keV, (3) 1. Five stages of ion implantation were performed in the order of 2 × 10 ¹⁴ cm ⁻² , (4) 150 keV, 8 × 10 ¹³ cm ⁻² , (5) 200 keV, 4 × 10 ¹³ cm ⁻² . Thus, the width of the region 1 having a constant impurity concentration in the p + region can be set to 0.2 μm, and the width of the region 2 having the impurity concentration profile in the p + region can be set to about 0.6 μm.

At the bottom of the trench, the width of the region 1 having a constant impurity concentration in the p + region is generally
The width of the region 2 having an impurity concentration profile in the p + region is 0.1 μm to 0.5 μm, and is about 0.3 μm to 0.8 μm.

  Thus, after forming the P + region for forming the pn junction, the ohmic contact 5 on the back surface of the semiconductor substrate and the Schottky electrode (Schottky contact) 6 on the surface are formed. Thus, the junction barrier Schottky diode of the present invention is completed (FIG. 4D).

  Next, the effects of the invention will be exemplified. FIG. 5 is a simulation result showing the relationship between the width (w2) of the region having an impurity concentration profile in the p + region at the bottom of the trench and the breakdown voltage. The horizontal axis represents the width (w2) of the region having an impurity concentration profile in the p + region at the bottom of the trench, and the vertical axis represents the breakdown voltage of the pn junction. From this result, the breakdown voltage is higher as the width of the region having the impurity concentration profile in the p + region at the bottom of the trench is wider. Specifically, if the width is about 0.3 μm, a sufficient breakdown voltage of 3.3 kV can be achieved. Recognize. This is because the electric field concentration at the trench corner can be alleviated by making the inclination of the pn junction at the bottom of the trench gentle. The withstand voltage of 3.3 kV is the withstand voltage assumed in this example as described above.

  On the other hand, FIG. 6 shows an example of the relationship between the width (w1) of the region having the impurity profile in the p + region formed on the side of the trench and the electric field strength at the Schottky interface. The horizontal axis represents the width (w1) of the region having the impurity concentration profile in the p + region, and the vertical axis represents the electric field at the Schottky interface.

  In this example, the interval between the p + regions is 3 μm. It can be seen that the electric field at the Schottky interface is smaller as the width (w1) of the region having the impurity concentration profile in the p + region formed in the trench side portion is narrower. This is presumably because the width of the low-concentration p + region, which has a small effect as an electric field relaxation layer at the Schottky interface, is narrowed.

  Thus, in the present invention, of the p + region 1 and the p + region 2, the width of the region 2 having the impurity concentration profile is thicker at the bottom than the side wall of the trench 7. Is understood to be important. That is, the relationship of width w1 (side wall side of the trench 7) <width w2 (bottom side of the trench 7) is essential.

  Next, application examples of the present invention will be illustrated. FIG. 7 shows a circuit diagram when this embodiment is applied to an inverter circuit. FIG. 7 shows an example of a three-phase inverter circuit. Any diode according to the present invention is applied to the diodes 21 to 26 in this circuit. In FIG. 7, Si-IGBT (Insulated Gate Bipolar Transistor) is shown as the switching element, but SiC-MOSFET (Metal Oxide Semiconductor Field Effect Transistor), SiC-JFET (Junction Field Effect Transistor), or the like may be used. The present invention is particularly effective because a high withstand voltage and a large current are required for inverters for railways and the like. In addition, since the inverter circuit configuration itself is a usual one, detailed description is omitted.

  FIG. 8 is a sectional structural view of a second embodiment according to the present invention. The cross section of the figure is similar to the example of FIG. The difference of this embodiment from the first embodiment is that the impurity concentration of the n-type region 9 sandwiched between the p + -type regions 2 is higher than that of the drift layer. By making the impurity concentration of the n-type region 9 sandwiched between the p + -type regions 2 higher than that of the drift layer 3, the width (w1) of the region having the impurity concentration profile of the p + -type region on the side of the trench is substantially reduced. Can be made narrower.

  FIG. 9 schematically shows this state. The horizontal axis represents depth, and the vertical axis represents impurity concentration. The vertical axis is a logarithmic scale. A curve p is a profile of impurity concentration in the drift layer 3. On the other hand, the straight line n1 is the impurity concentration of the drift layer 3. In this example, the p-type impurity concentration and the n-type impurity concentration coincide at the position of the depth a. Since the vertical axis is a logarithmic scale, it can be considered that a pn junction is formed between the position a and the position c. Here, as in the second embodiment, assuming that the impurity concentration of the n-type region 9 is higher than that of the drift layer 3 and is a straight line n2, the position where the p-type impurity concentration and the n-type impurity concentration coincide is the depth b. It becomes the position. Therefore, in this case, it can be considered that a pn junction is formed approximately between the position b and the position c. The width of the region having the impurity concentration profile of the p + -type region can be substantially narrowed.

  In this example, since the spread of the depletion layer from the p region in the ON state is also reduced, there is an effect that the current path is widened and the ON current can be increased.

In the manufacturing method of the second embodiment, the n-type region 9 having a higher concentration than the drift layer is formed by ion implantation before the trench 7 is formed in the manufacturing method of the first embodiment. This is the same as the manufacturing method of the first embodiment. If the concentration of the n region 9 is increased too much, the electric field relaxation effect at the Schottky interface may be reduced. Therefore, the impurity concentration is preferably about half to one digit higher than that of the drift layer 3. As the impurity concentration in this region,
A range of about 2 × 10 ¹⁵ cm ⁻³ to 8 × 10 ¹⁶ cm ⁻³ is frequently used. Further, in the pn junction at the trench corner, the breakdown voltage may drop if the impurity concentration in the n-type region is high. Therefore, the n-type layer having a higher impurity concentration than the drift layer 3 is shallower than the pn junction at the bottom of the trench. It is desirable to be in the area.

  FIG. 10 is a sectional structural view of a third embodiment according to the present invention. The difference of this embodiment from the second embodiment is that no trench is formed. If a trench is not formed, high energy is required to form the p-type region, and the pn junction on the side of the p + region becomes loose. However, by increasing the concentration of the surface layer portion of the epitaxial layer, the width of the pn junction at the side portion of the p + region can be made narrower. It is also easy to make the pn junction steeper. Thus, the effect of the present invention can also be obtained in the form of this example.

1 is a sectional structural view of a first embodiment of an element according to the present invention. 1 is a plan structural view of a first embodiment of an element according to the present invention; 1 is a plan structural view of a first embodiment of an element according to the present invention; It is explanatory drawing of the manufacturing process of the 1st Example of the element by this invention. FIG. 3 is a characteristic diagram of the first embodiment of the device according to the present invention. FIG. 3 is a characteristic diagram of the first embodiment of the device according to the present invention. It is a circuit diagram at the time of applying the 1st Example of the element by this invention to an inverter circuit. FIG. 3 is a cross-sectional structural view of a second embodiment of the device according to the present invention. It is a density | concentration profile figure of 2nd Example of the element by this invention. FIG. 6 is a sectional structural view of a third embodiment of the device according to the present invention. FIG. 2 is a cross-sectional structure diagram of a conventional planar type JBS. It is a cross-sectional structure diagram of a usual trench type JBS.

Explanation of symbols

1: p + type region having a constant concentration, 2: p + type region having a concentration profile, 3: n − type drift layer, 4: n + type cathode layer, 5: cathode Electrode: 6: anode electrode, 7: trench, 8: hard mask, 9: n-type surface layer, 10: termination region, 11: SiC substrate, 12: bottom of trench 7, 13: side of trench 7, 14: Vertical ion implantation, 15: oblique ion implantation, 21-26: diode.

Claims (1)

On the substrate surface having the first conductivity type made of silicon carbide having (0001) or (000-1) as the main surface, the first conductivity type drift layer of silicon carbide,
Schottky junctions and pn junctions alternately arranged on the drift layer surface;
In junction barrier Schottky diodes with external contacts as anode and cathode,
A p-type region in which the slope of a pn junction included in a p-type region having a non-constant impurity concentration present on the side of the p-type region forming the pn junction is not constant in the bottom of the p-type region Is steeper than the slope of the pn junction included in
A p-type region forming the pn junction is disposed in a trench formed in the drift layer surface;
The impurity present at the bottom of the p-type region at the side and bottom of the trench is only one of Al and B,
A junction barrier Schottky diode characterized in that a concentration of a region sandwiched between p-type regions forming a pn junction in the drift layer is higher than that of a drift layer existing therebelow .

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