JP5310291B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a power semiconductor device used for a power conversion device or the like. More specifically, it relates to a diode.

  Power diodes are widely used for recirculation of inverter circuits or converter circuits. At the time of reverse recovery from a state where forward current flows through the diode to a reverse bias blocking state, it is necessary to sweep out excess carriers accumulated inside. When the amount of internally stored carriers is large, there is a merit that the forward voltage in the forward energization state decreases, but at the time of reverse recovery, the amount of carriers swept out increases and reverse recovery loss increases, resulting in a demerit. Such forward voltage and reverse recovery loss are said to have a trade-off relationship. In order to adjust this trade-off relationship to the optimum relationship, crystal defects are generated by electron beam irradiation or light ion irradiation to the semiconductor substrate, or heavy metal such as platinum is diffused to generate band gap levels. By doing so, the carrier lifetime is shortened to promote the disappearance of excess carriers. This is said to be the effect of introducing a lifetime killer. According to this introduction, the amount of accumulated carriers in the forward energization state is reduced and excessive carrier disappearance at the time of reverse recovery is promoted, so that the forward voltage increases but the reverse recovery loss is reduced. The introduction of the lifetime killer is common in the manufacturing process of the power diode, but it causes an increase in process cost. Therefore, it is preferable not to introduce it if possible. In particular, when platinum is diffused as a lifetime killer, the forward voltage decreases at a high temperature, and the temperature characteristics of the forward voltage are negative. This phenomenon is caused by the temperature dependence of the band gap level of the recombination center introduced by platinum and the carrier capture cross section of the platinum killer. Thus, when the temperature dependence of the forward voltage is negative, when a diode is used in parallel, a positive feedback that more current is concentrated on an element having a higher junction temperature is applied, and a specific element is easily destroyed. The problem occurs. Therefore, when a plurality of elements are used in parallel, a positive temperature characteristic to which negative feedback is applied is desirable. In general, crystal defects are generated by irradiating a silicon semiconductor substrate with an electron beam, and the carrier lifetime is reduced by recombination centers due to the defects. Since the electron beam is highly transmissive, crystal defects are generated at a uniform density in the depth direction of the silicon semiconductor substrate. This is in contrast to the platinum killer which is easily segregated and introduced into the surface anode side. As a result, the amount of accumulated carriers on the anode side is relatively larger in the diode irradiated with the electron beam than in the diode introduced with the platinum killer. Therefore, the reverse recovery waveform becomes hard. That is, the reverse recovery current quickly returns to zero, and a high surge reverse voltage is likely to occur due to the parasitic inductance component in the application circuit. A similar problem occurs when the switching frequency is increased. As a result, the device is easily destroyed by the generated reverse surge voltage. Moreover, since it becomes easy to oscillate at the time of reverse recovery, it also causes noise. Furthermore, the diode in which the lifetime killer is introduced has a delayed current rise in voltage-current characteristics compared to the non-killer diode in which the lifetime killer is not introduced. Therefore, even if the forward voltage is the same at the rated current, the diode in which the lifetime killer is introduced has a high forward voltage in the region below the rated current. The diode is not always used at the rated current, and is used below the rated current for most of the period. Therefore, if the rise of the current is slow, the forward voltage in the low current region increases and the loss increases.

  In order to suppress the carrier accumulation amount on the anode side for the purpose of softening the reverse recovery waveform, it is preferable to introduce a lifetime killer that easily segregates on the anode side due to platinum diffusion or the like as described above. Lowering the amount of impurities in the layer is more effective. However, in that case, if the amount of impurities in the anode p layer is too low, the anode p layer tends to be depleted when a reverse bias is applied to the diode, the depletion layer reaches the anode electrode, and the reverse breakdown voltage decreases. There is a problem that it becomes easy. To solve this problem, the anode side has a structure having both a PN junction region and a high breakdown voltage Schottky junction region using a wide band gap semiconductor. In the normal operation region, the Schottky junction region mainly works, and a surge current flows. In some cases, a diode having a structure for operating the PN junction region to protect the element is known. This diode has a structure that achieves both a low impurity concentration, a low concentration, and a high breakdown voltage in the anode p layer, and is called MPS (Merged Pin and Schottky Diode) (Non-patent Document 1). In the diode having the MPS structure, a depletion layer extends from the PN junction region at the time of reverse bias, and the Schottky junction region is not exposed to a high electric field, so that a leakage current from the Schottky junction can be suppressed. However, in the MPS structure diode, if an attempt is made to achieve the reduction of accumulated carriers so as not to require the lifetime killer by simply reducing the injection and concentration of the anode p layer, the ohmic contact of the anode electrode cannot be obtained. Since there is a problem that the contact resistance is increased, a structure for reducing the accumulated carriers by using a lifetime killer in the PN junction region together with the Schottky junction is actually used.

  Next, the problem of element destruction of the reflux diode will be described. During forward energization, excess carriers are also accumulated in the periphery of the element outside the active portion through which the main current flows. As shown in the cross-sectional view of the peripheral portion of the conventional diode in FIG. 8, these excess carriers are indicated by arrows from the surface anode electrode 1 and the end portion 3 of the anode p layer 2 that are the closest current paths during reverse recovery. It is withdrawn intensively from the indicated location (concentration of reverse recovery current). Also, since the end portion 3 of the anode p layer 2 has a high electric field strength, a large Joule heat is generated by the current x electric field product. Therefore, the end 3 of the anode p layer 2 is easily broken during the reverse recovery operation of the diode, and becomes a bottleneck for the diode breakdown resistance. In order to prevent such destruction at the anode p layer end 3, the distance between the anode p layer end 3 and the anode electrode contact 5 is set with an insulating film (oxide film) 4 interposed, as shown in FIG. By separating, the carrier is less likely to concentrate on the end portion 3 of the anode p layer, and a region having a high electric field strength (anode p layer end portion 3) and a region having a high current density (location indicated by an arrow) are separated. Measures are taken to reduce the generation of Joule heat.

  With regard to the technology for suppressing the reverse recovery current of the freewheeling diode, many patent documents related to a structure in which a region having a Schottky contact interface is provided on the surface of the anode side of the PN junction diode to limit minority carrier injection have been published It is a well-known technique.

  Further, by forming an n-type barrier layer (implantation suppression layer) having a higher impurity concentration than the n-type drift layer between the p-type anode region and the n-type drift layer, the p-type anode region is changed to the n-type drift layer. There is a literature on improving the reverse recovery characteristics by limiting the amount of injected holes and reducing the amount of carriers accumulated in the n-type drift layer when energized. Patent Document 1).

Furthermore, with respect to the problem that device breakdown occurs due to the concentration of reverse recovery current at the end of the anode p layer, the fourth reference example and FIG. By adopting a structure in which the n ⁺ layer on the back surface side is arranged inside the direction parallel to the surface, carriers accumulated in the peripheral portion outside the anode p layer are reduced, and the reverse at the end of the anode p layer A structure for suppressing concentration of recovery current is shown (Patent Document 2).

Proceedings of ISPSD 2006, 305, “2nd Generation SiC Schottky Diode: A new benchmark in SiC device ruggedness”

JP 2004-186413 A Japanese Patent No. 4031371

  However, as described above, in the conventional diode shown in FIG. 9 for preventing destruction at the end of the anode p layer, the anode p of the separation portion between the anode p layer end 3 and the anode electrode contact 5 is used. Since the current density is low in the layer 2 portion, the effective active area through which the main current flows is reduced, leading to an increase in the forward voltage. Particularly, since the non-killer diode has a long carrier diffusion length, the structure of the anode p layer end 3 as in the conventional diode shown in FIG. 9 reduces the accumulated carriers in the peripheral portion outside the anode p layer 2. Needs to further increase the separation distance between the anode p-layer end 3 and the anode electrode contact 5, and further increases the forward voltage. For this reason, when a conventional diode having the above-described isolation portion in the anode p layer is manufactured as a non-killer diode, a new structure that does not increase the forward voltage is required.

Further, a structure in which an n ⁺ layer (corresponding to an n-type carrier injection suppressing layer) is formed under the anode p layer as disclosed in Patent Document 1 to suppress the injection of holes from the anode p layer is a substrate. forming a plurality of trenches from the surface, the n ⁺ layer provided between the underlying anode p layer to the mesa substrate portion sandwiched between the trenches, is that preventing the decrease of breakdown voltage by promoting the depletion of the n ⁺ layer. However, in this structure, in the reverse blocking state, the depth of the trench having the conductor film embedded via the insulating film penetrates the barrier layer (injection suppression layer) and reaches the n ⁻ base layer. There is a new problem that the electric field concentrates on the bottom of the trench and the breakdown voltage tends to decrease. Even when the depth of the trench is made shallow without penetrating the barrier layer, the depletion layer does not easily extend through the barrier layer, and the breakdown voltage is also lowered. If the depth of the groove can be perfectly matched to the junction between the barrier layer and the base layer, it is most preferable in terms of both breakdown voltage and reverse recovery characteristics. Matching is extremely difficult and not easy.

  The present invention has been made in view of the above-described points. The object of the present invention is to reduce the carrier injection amount from the anode p layer without reducing the reverse breakdown voltage and without introducing a lifetime killer. An object of the present invention is to provide a semiconductor device and a method of manufacturing the same that can suppress and further improve the reverse recovery breakdown resistance of the semiconductor device without increasing the forward voltage.

  As shown in the cross-sectional view of the main part of the surface structure of the anode layer in FIG. 2, the semiconductor device of the present invention has the anode p layer 11 and the n-type carrier injection suppressing layer 12 below the anode p layer 11 sandwiched by the first recess 17a. It is characterized by having a surface structure 29 provided on the first protruding semiconductor portion 13a that repeats at a pitch of. Further, a conductor layer 16 such as polycrystalline silicon is buried in the first recess 17a via a dielectric film such as an oxide film 15. The anode electrode 14 covering the surface structure 29 is in contact with the surface of the anode p layer 11. The lowest end surface of the n-type carrier injection suppressing layer 12 provided under the anode p layer 11 and having a function of suppressing the injection of holes from the anode p layer 11 to the n-type drift layer 18 is the first protrusion It is characterized in that it is flush with the bottom surface of the first recess 17a provided between the semiconductor portions 13a. The conductor layer 16 has a function of promoting depletion of the n-type carrier injection suppressing layer 12 when a reverse bias is applied to the element. By providing a surface structure 29 composed of the repeated first protruding semiconductor portion 13a, the thermal oxide film 15 formed in the first recess 17a sandwiched between the first protruding semiconductor portion 13a, the conductor layer 16, and the like. Even if the n-type carrier injection suppressing layer 12 has a higher impurity concentration than the n-type drift layer 18, it has a function of reducing the electric field strength in the n-type carrier injection suppressing layer 12 when a reverse bias is applied. A decrease can be prevented. In addition, since the semiconductor device having the surface structure 29 described above is used, depletion of the anode p layer 11 at the time of reverse bias application is suppressed, so that complete depletion is prevented even when the anode p layer 11 has a low impurity concentration. It is possible to prevent a decrease in breakdown voltage due to punch through to the anode electrode 14 of the depletion layer.

  As shown in FIG. 3, which is a cross-sectional view showing a state where a reverse bias is applied to the repeated first protruding semiconductor portion 13a according to the semiconductor device of the present invention, the n-type carrier injection suppressing layer 12 is generated by depletion. The negative space charge for compensating the positive space charge is generated not only by depletion of the anode p layer 11 but also in the conductor layer 16 via the thermal oxide film 15. As a result, the required expansion width of the depletion layer in the anode p layer 11 is small, and punch-through can be prevented. For the above reasons, according to the semiconductor device including the surface structure 29 composed of the conductor layer 16 with the first protruding semiconductor portion 13a and the thermal oxide film 15 interposed therebetween, the reverse breakdown voltage is not lowered and A semiconductor device can be obtained in which the amount of hole injection from the anode is reduced without introducing a lifetime killer and the reverse recovery breakdown resistance is improved.

A method for suppressing the injection of holes from the anode p layer by forming an n ⁺ layer (corresponding to an n-type carrier injection suppressing layer) under the anode p layer as described above is also disclosed in Patent Document 1. In the structure disclosed in Patent Document 1, a plurality of trenches are formed from the substrate surface, an anode p layer and an n ⁺ layer are provided in a mesa substrate portion sandwiched between the trenches, and the n ⁺ layer is depleted. It is promoted to prevent a decrease in pressure resistance. However, this structure has a new problem that the electric field concentrates at the bottom of the trench in the reverse blocking state and the breakdown voltage is likely to be lowered. On the other hand, in the semiconductor device and the manufacturing method thereof according to the present invention, electric field concentration at the time of reverse blocking can be prevented, and a decrease in breakdown voltage can be avoided.

Further, preferably, in the semiconductor device of the present invention, a region where the back surface n-type cathode layer 25 is in contact with the cathode electrode 26 is limited to the active portion 30. By this limitation, it is possible to suppress the electron injection into the peripheral breakdown voltage structure portion 32 of the element and to reduce the accumulated carrier concentration of the peripheral breakdown voltage structure portion 32. It is effective to reduce the accumulated carrier concentration by reducing the thickness of the n-type cathode layer 25 to reduce the total impurity amount, and in this case, the back surface (n-type cathode layer) 25) The effect of scratches on the side, strain stress during assembly, etc. reaches the tip of the depletion layer at the time of reverse bias, and the withstand voltage may decrease. In order to obtain a sufficient reverse breakdown voltage, an n-type buffer layer 24 deeper than the n ⁺ -type cathode layer 25 and having a lower concentration than the cathode layer 25 (higher concentration than the n-type drift layer 18) is formed on the entire back surface. Thus, it is desirable to make the tip of the depletion layer difficult to approach the n-type cathode layer 25. Such a thick and low concentration n-type buffer layer 24 can be formed by irradiation with hydrogen ions or the like. In the case of a conventional structure that suppresses the amount of carriers accumulated in the peripheral breakdown voltage structure of the element only by the effect of the lifetime killer function that segregates on the surface anode side, such as platinum, the width is set so that the active part is not affected by the lifetime killer. Ineffective regions (regions in which the anode p layer is not in contact with the anode electrode and the current does not flow effectively) are required. On the other hand, when the backside cathode layer 25 is limited to only the active portion 30 according to the present invention, as shown in the sectional view of the peripheral breakdown voltage structure portion 32 of the diode in FIG. As a result of the effect of suppressing the carrier injection, the carrier accumulation amount in the peripheral breakdown voltage structure portion 32 of the element can be suppressed in the 33 invalid region on the narrower surface anode side, and the forward voltage rise of the diode can be further suppressed. it can.

  That is, according to the first aspect of the present invention, the first concave portion and the first concave portion are formed in the active portion through which the main current flows on one main surface side of the first conductive type semiconductor substrate. A first protrusion-like semiconductor portion having a first protrusion-like semiconductor portion sandwiched between the first protrusion-like semiconductor portion and a first protrusion-like semiconductor portion embedded in an insulating film. A first conductivity type carrier injection suppressing layer having a lower end surface flush with the first recess, and a second conductivity type semiconductor layer in contact with the upper surface of the carrier injection suppressing layer, and in ohmic contact with the surface of the surface structure The object of the present invention is achieved by providing a semiconductor device having the first main electrode (anode electrode).

  According to the second aspect of the present invention, from the first conductivity type semiconductor substrate provided at a position corresponding to the active portion on the other main surface side of the first conductivity type semiconductor substrate. A first conductive semiconductor layer having a higher concentration than that of the first conductive semiconductor substrate, the first conductive semiconductor layer having a high concentration and deeper than the first conductive semiconductor layer on the entire surface of the other main surface. 2. The semiconductor device according to claim 1, further comprising a second main electrode (cathode electrode) having a first conductivity type buffer layer having a lower concentration than the first layer and in ohmic contact with the surface of the first conductivity type semiconductor layer. It can be.

According to the third aspect of the present invention, a peripheral pressure-resistant structure portion is provided on the outer periphery of the active portion via an intermediate region, and the intermediate region sandwiches the second recess and the second recess. A second protruding semiconductor portion that repeats at a predetermined pitch, and the second recess has a conductor layer embedded via an insulating film, and the lower end surface is flush with the second recess. The second protruding semiconductor portion having a first conductivity type carrier injection suppressing layer and a second conductivity type semiconductor layer in contact with the upper surface of the carrier injection suppressing layer is connected to the first protruding semiconductor portion as an extension portion, and The peripheral breakdown voltage structure includes a third recess having a conductor layer embedded via an insulating film, and a first conductivity type carrier injection suppression layer sandwiching the third recess and flushing the third recess with the lower end surface that having a second conductivity type semiconductor layer in contact with the upper surface of the carrier injection inhibiting layer and It is preferable that the semiconductor device according to claim 1, wherein the appended claims comprising a three protruding semiconductor portion.

According to the invention of claim 4, the surface structure has a predetermined pattern pitch sandwiching the dielectric film by selective epitaxial growth on the one main surface using the dielectric film as a mask, The first conductivity type carrier injection suppressing layer and the second conductivity type semiconductor layer are deposited and formed in this order, and then the dielectric film is removed to form the first recess, and the first recess sandwiching the first recess 2. The method of manufacturing a semiconductor device according to claim 1, further comprising a step of forming a protruding semiconductor portion and a step of forming a conductor layer in the first recess through an insulating film. Is desirable.

  According to the invention of claim 5, the first conductivity type dopant or the second conductivity type dopant to which the first conductivity type carrier injection suppressing layer and the second conductivity type semiconductor layer respectively correspond. The method of manufacturing a semiconductor device according to claim 4, further comprising a step of sequentially depositing and forming by selective epitaxial growth.

According to the invention of claim 6, after the semiconductor single crystal layer to which the first conductivity type dopant is added is grown, the second conductivity type is formed to a predetermined depth in the semiconductor single crystal layer. a method of manufacturing a semiconductor device of the dopant ions implanted in the upper layer by the second conductive semiconductor layer and the scope of the claim 5 of the appended claims to form the first conductivity type carrier injection inhibiting layer of the lower layer .

  According to a seventh aspect of the present invention, the semiconductor single crystal layer formed by the selective epitaxial growth is formed thicker than the thickness of the dielectric film mask, and thereafter, based on the thickness of the dielectric film mask. The method of manufacturing a semiconductor device according to claim 4, which is polished and removed.

  According to the invention of claim 8, after forming the anode electrode on the one main surface, the other main surface side is ground to a required thickness, and hydrogen from the other main surface is obtained. The first conductivity type buffer layer is formed on the entire surface by ion implantation, and the first conductivity type semiconductor layer is formed on the other main surface corresponding to the active portion of the one main surface by selective ion implantation. A method of manufacturing a semiconductor device according to claim 2.

  According to the present invention, the amount of carrier injection from the anode p layer is suppressed without introducing a lifetime killer without reducing the reverse breakdown voltage, and further, the reverse recovery breakdown resistance of the semiconductor device can be increased without increasing the forward voltage. A semiconductor device that can be improved and a manufacturing method thereof can be provided.

It is principal part sectional drawing of the semiconductor substrate for every main manufacturing processes of the diode concerning this invention (the 1). It is principal part sectional drawing of the semiconductor substrate for every main manufacturing processes of the diode concerning this invention (the 2). It is principal part sectional drawing of the semiconductor substrate for every main manufacturing processes of the diode concerning this invention (the 3). It is principal part sectional drawing of the semiconductor substrate for every main manufacturing processes of the diode concerning this invention (the 4). It is principal part sectional drawing of the semiconductor substrate for every main manufacturing processes of the diode concerning this invention (the 5). It is principal part sectional drawing which shows the surface structure of the diode concerning this invention. It is an expanded sectional view of the surface structure for demonstrating the charge compensation by the conductor layer at the time of reverse bias of the diode concerning this invention. FIG. 5 is a schematic cross-sectional view of the periphery of a diode for explaining the flow of electrons and holes when the n ⁺ -type cathode layer according to the present invention is disposed so as to correspond only to an active portion. It is an accumulation carrier distribution figure in the forward direction energization state of the diode concerning the present invention. It is a comparison figure of peripheral part carrier concentration distribution in the forward direction electricity supply state of the diode (a) concerning this invention, and the conventional diode (b). It is a voltage-current characteristic comparison figure of this invention and the conventional diode. It is sectional drawing of the peripheral part of the diode which shows the extraction concentration location of the accumulation | storage carrier from the anode at the time of the reverse recovery in the past with the arrow. It is sectional drawing of the peripheral part of the conventional diode which has the isolation structure between the anode p layer edge part and an anode electrode contact, and has the same carrier extraction concentration part as the arrow shown by the arrow.

  Hereinafter, embodiments of a semiconductor device and a method for manufacturing the same according to the present invention will be described in detail with reference to the drawings. The present invention is not limited to the description of the examples described below unless it exceeds the gist.

Hereinafter, in the embodiments to be described, a diode is used as the semiconductor device of the present invention. As shown in FIG. 4 (however, the surface structure on the anode side according to the present invention is simplified and omitted, and is shown as a structure of only the anode layer), holes are formed from the anode p layer to the n-type drift layer in the energized state. By being injected and electrons are injected from the back cathode layer into the n-type drift layer, the n-type drift layer is in a high injection state. However, when the impurity concentration of the surface anode p layer is low and the impurity concentration of the n-type carrier injection suppression layer (not shown in FIG. 4) on the surface side is high, hole injection from the anode layer is suppressed. In that case, the holes and electron storage carriers in the active portion 30 have a distribution in which the carrier amount on the anode side is suppressed, as shown in the carrier distribution diagram in the depth direction of FIG. When the high-concentration n ⁺ layer is limitedly disposed as the back surface cathode layer 25 so that only the active portion 30 through which the main current flows is in ohmic contact with the cathode electrode 26 (FIG. 4), The carrier distribution in the corresponding n-type drift layer is high, and the carrier concentration in the n-type drift layer corresponding to the peripheral breakdown voltage structure portion 32 is relatively low.

FIG. 6 shows a diode in which the end of the anode p layer and the anode electrode contact are separated, and an n ⁺ layer serving as a conventional cathode layer is formed on the entire back surface (FIG. 6B). ) And an anode-cathode of each of the diodes (FIG. 6 (a)) in which the n ⁺ layer serving as the backside cathode layer is provided only in the active portion when energized in the forward direction. The hole concentration distribution in the periphery of the device is also shown. However, the separation width between the anode p layer end of the conventional diode shown in FIG. 9 and the anode electrode contact is adjusted so that both forward voltages at the rated current are the same. 6 (a) and 6 (b), the hole concentration is the highest in the vicinity of the n ⁺ layer indicated by hatching, the hole concentration decreases in the direction of the upper anode p layer, and the hole concentration also in the peripheral direction. It shows that it falls. The concentration decreases for each curve indicating the concentration distribution. Accordingly, it is shown that the density decrease increases as the number of curves increases with reference to the high density portion indicated by hatching. From the hole concentration distribution in the peripheral portion shown in FIGS. 6 (a) and 6 (b), although both (a) and (b) have the same forward voltage, the element of the diode (a) according to the present invention. The hole concentration in the peripheral portion is dramatically reduced as compared with (b). At the time of reverse recovery, the potential of the anode electrode is made lower than the potential of the cathode electrode, so that the accumulated carriers begin to be discharged, and the reverse voltage recovery of the diode proceeds in accordance with the amount of discharged carriers. However, since the amount of accumulated carriers in the peripheral portion is originally small, the hole current drawn from the end portion of the anode p layer is small and Joule heat generation is small. For this reason, destruction by generated heat is prevented. That is, the semiconductor device of the present invention does not rely only on the separation structure between the anode p layer end portion and the anode electrode contact in the surface anode layer, but also suppresses the amount of hole injection from the surface anode p layer and the effective area of the back surface cathode layer. By limiting, it is possible to suppress the amount of accumulated carriers in the peripheral portions of the front surface and the back surface in a well-balanced manner, and to avoid increasing the forward voltage unnecessarily.

  When a reverse bias is applied to the diode according to the present invention, the depletion layer begins to extend from the pn junction between the anode p layer and the n-type carrier injection suppressing layer. Further, the side wall of the n-type carrier injection suppressing layer is formed by a surface structure formed by a repetitive protruding semiconductor portion and a conductor layer embedded through a dielectric film in a recess sandwiched between the repetitive protruding semiconductor portions. Since the depletion layer also extends, the electric field strength inside the n-type carrier injection suppressing layer is reduced. On the other hand, depletion of the anode p layer is suppressed by charge compensation by the conductor layer. When the reverse bias is increased, the n-type carrier injection suppressing layer is completely depleted and the depletion layer extends the n-type drift layer, so that a high breakdown voltage can be achieved.

Creation of 1200V FWD (Reflux Diode) FIGS. 1-1 to 1-5 are a cross-sectional view and a perspective view of a main part sequentially showing main manufacturing steps of a free-wheeling diode rated at 1200V according to the present invention. Description will be made in the order of main manufacturing steps. An initial oxide film 21 having a thickness of 2 μm is formed using the FZ-n type silicon semiconductor substrate 20 having a specific resistance of 60 Ωcm as a material (FIG. 1-1A). By patterning / etching the active portion 30, parallel stripe-like initial oxide films 21 having a width of 2 μm and a pitch of 4 μm and openings 22 having the same width and the same pitch are formed alternately on the initial oxide film 21 (FIG. 1-1 (b). )). The initial oxide film pattern of the peripheral breakdown voltage structure 32 surrounding the active portion 30 is a parallel stripe pattern having an opening width of 2 μm and a predetermined width determined by the breakdown voltage design. An intermediate region 31 is provided between the active portion 30 and the peripheral voltage withstanding structure portion 32. The intermediate region 31 has a pattern in which an opening pattern having a width of 1.5 μm and a pitch of 4 μm and an initial oxide film pattern having a width of 2.5 μm and a pitch of 4 μm are alternately repeated. Further, the intermediate region 31 further includes an opening connecting portion 23 having a pattern for cutting the initial oxide film 21 having a width of 2.5 μm at a right angle and connecting the openings 22 having a width of 1.5 μm to each other. (Fig. 1-2 (c)). The opening connecting portion 23 connects the anode p layer 11 also in a direction perpendicular to the stripe, thereby contacting the anode electrode 14 serving as a route from which accumulated carriers in the peripheral voltage withstanding structure portion 32 are concentrated and pulled out during reverse recovery. This is because the distance between the outermost peripheral portion of the anode p layer 11 and the maximum electric field region which is the outermost peripheral end portion of the anode p layer is separated. This separation structure has the same concept as the conventional separation structure described with reference to FIG. In Example 1, a diode having such a structure can be formed to improve reverse recovery tolerance.

Next, a single crystal silicon layer is grown in the opening 22 by selective epitaxial (hereinafter referred to as epi) growth. At 1000 ° C., hydrogen, trichlorosilane, phosphine (PH ₃ ), and hydrogen chloride are supplied, and the silicon crystal is not grown on the oxide film 21 but is grown only on the exposed surface of the silicon semiconductor substrate in the opening 22. . After growing the n-type epi layer (n-type carrier injection suppressing layer 12) having a thickness of 1 μm, the dopant gas is switched from phosphine (PH ₃ ) to diborane (B ₂ H ₆ ) until the height exceeds the oxide film 21 thickness. A p-type epi layer (anode p layer 11) is further grown (FIG. 1-2 (d)). Excess silicon crystals on the surface are polished by CMP (chemical mechanical polishing apparatus) using the oxide film 21 as a stopper (FIG. 1-3E). The oxide film 21 is entirely removed by hydrofluoric acid, and then a thermal oxide film 15 having a thickness of 0.1 μm is formed by dry oxidation (FIG. 1-3 (f)). Polycrystalline silicon 16 having a film thickness of 0.5 μm is deposited by CVD (FIG. 1-3 (g)). The excess polycrystalline silicon 16 deposited on the thermal oxide film 15 on the anode p layer 11 is removed again by surface polishing (FIG. 1-3 (h)). A thermal oxide film 15 having a thickness of 0.1 μm functions as a polishing stopper. After removing the 0.1 μm-thick thermal oxide film 15 with hydrofluoric acid (FIGS. 1-4 (i)), an anode electrode 14 having a thickness of 5 μm is formed on the substrate surface by Al—Si sputtering. The anode electrode 14 is also in contact with the anode p layer 11 and the polycrystalline silicon conductor layer 16 (FIGS. 1-4 (j)). By patterning / etching, the Al—Si sputtered metal deposited in the intermediate region 31 with the peripheral breakdown voltage structure 32 is removed as shown in FIG. By adopting such a configuration, it is possible to prevent the drawn carriers from concentrating on the end portion of the anode p layer 11 where the electric field strength is maximized. Since the opening width of the intermediate region 31 is 1.5 μm, which is narrower than 2 μm of the opening width of the active portion 30, the n-type carrier injection suppressing layer 12 in the intermediate region 31 has a function of further reducing the electric field strength. By providing the intermediate region 31 having such a configuration and function, the electric field strength at the point of the intermediate region 31 where the drawn carriers are particularly likely to concentrate can be effectively suppressed.

Next, the back surface of the silicon semiconductor substrate 20 is ground so that the thickness of the silicon semiconductor substrate 20 is 130 μm. The back surface is spin-etched with a mixed acid containing hydrofluoric acid and nitric acid as main components, and the damaged layer is removed by mechanical grinding. After applying / baking a protective resist on the surface of the semiconductor substrate, hydrogen ions having a dose of 1 × 10 ¹⁴ cm ⁻² are implanted from the back surface to form the n-type buffer layer 24 (FIG. 1-4 (k)). . The resist is left on the outer peripheral portion on the back side corresponding to the peripheral pressure-resistant structure portion 32 located outside the region of the anode electrode contact on the front side by the back side patterning by the double side alignment, and the dose amount is 1 × 10 ¹⁵ cm at the center portion. ^-2 phosphorus ions are implanted to form the n ⁺ -type cathode layer 25, and then the resist is incinerated / peeled. By annealing at 380 ° C. for 1 hour in a nitrogen atmosphere, the donor concentration of hydrogen is increased to increase the donor concentration of the buffer layer 25, and at the same time, the phosphorus atoms implanted into the back surface are electrically activated (FIGS. 1-5 ( l)). The n ⁺ type cathode layer 25 into which phosphorus atoms are introduced becomes a high concentration cathode layer. Since the n ⁺ -type cathode layer 25 has a high concentration, the contact resistance with the cathode electrode 26 is low. Further, since the junction is shallow, the total amount of impurities is suppressed, and the amount of electrons injected from the n ⁺ -type cathode layer 25 is effectively suppressed. Polyimide is applied as a passivation layer 27 on the surface (one main surface) side of the semiconductor substrate, and the anode electrode pad is exposed by patterning / etching. The cathode electrode 26 made of a three-layer metal film such as Ti / Ni / Au is deposited on the back surface, and the wafer process is completed.

The high concentration n ⁺ -type cathode layer 25 is in ohmic contact with the cathode electrode 26. The n-type buffer layer 24 has a doping concentration higher than that of the drift layer 18 but lower than that of the n ⁺ -type cathode layer 25 and is in Schottky contact with the cathode electrode 26 (FIG. 1-5 (m)). When the silicon semiconductor substrate 20 after the above manufacturing process is diced, the diode chip according to the present invention is completed.

  Although the diode chip of the present invention thus manufactured is non-killer, the carrier injection amount from the anode can be suppressed and the reverse recovery loss can be suppressed to a satisfactory level. Further, because of the non-killer, the current rises quickly, the forward voltage at a low current during actual use is reduced, and the conduction loss is low.

FIG. 7 is a voltage-current characteristic comparison diagram between the diode manufactured in Example 1 of the present invention and a conventional diode. The rated current density is 450 A / cm ² , and the forward voltage at that time is 1.85V. The non-killer diode according to the present invention has a fast current rise and a low forward voltage in a low current region. Further, in the diode according to the present invention, since the amount of carriers injected from the backside cathode at the chip periphery is kept low, the accumulated carrier density at the chip periphery is low. For this reason, as shown in FIG. 6, the current concentration at the end of the anode layer during reverse recovery is relaxed, and the breakdown resistance is improved. For example, in the conventional diode, the hole concentration at the end of the anode p layer is 7 × 10 ¹⁶ cm ⁻³ , whereas in the diode according to the present invention, the hole concentration is as low as 1 × 10 ¹⁶ cm ⁻³ . This indicates that the amount of accumulated carriers in the diode according to the present invention is dramatically reduced.

  According to the semiconductor device of the present invention, hole injection from the anode layer in the active portion can be reduced, and the introduction of a lifetime killer is unnecessary, so that the manufacturing cost is reduced. In contrast to the conventional MPS type diode using a platinum killer, the present invention can make the temperature characteristics positive and reduce the possibility of destruction during parallel operation. Further, since it is a non-killer, the forward voltage at a low current can be reduced, and conduction loss under actual use conditions is reduced. Further, the region where the back surface cathode layer is in contact with the back surface cathode electrode is limited to the active portion, and electron injection into the peripheral portion of the device is suppressed, and the accumulated carrier concentration in the peripheral portion is dramatically reduced. For this reason, current concentration at the end of the anode p layer during reverse recovery is suppressed, and the breakdown resistance can be improved without increasing the forward voltage.

DESCRIPTION OF SYMBOLS 1, 14 Anode electrode 2, 11 Anode p layer 3 End part of anode p layer 4 Insulating film 5 Contact of anode electrode 12 Injection | pouring suppression layer 13a 1st protrusion semiconductor part 13b 2nd protrusion semiconductor part 13c 3rd protrusion semiconductor Portion 15 Thermal oxide film 16 Conductor layer 17a First recess 17b Second recess 17c Third recess 18 n-type drift layer 20 Semiconductor substrate 21 Initial oxide film 22 Opening 23 Opening connection 24 n-type buffer layer 25 n ⁺ type cathode Layer 26 Cathode electrode 27 Passivation layer 30 Active portion 31 Intermediate region 32 Peripheral breakdown voltage structure portion

Claims (8)

A surface structure having, on one main surface side of the first conductivity type semiconductor substrate, an active portion through which a main current flows has a first recess and a first protruding semiconductor portion that repeats at a predetermined pitch across the first recess. The first recess has a conductor layer embedded via an insulating film, and the first projecting semiconductor portion has a first conductivity type carrier that is flush with the first recess. A semiconductor device comprising an injection suppression layer and a second conductive semiconductor layer in contact with the upper surface of the carrier injection suppression layer, and having a first main electrode in ohmic contact with the surface of the surface structure. A first conductivity type semiconductor layer having a higher concentration than the first conductivity type semiconductor substrate provided at a position corresponding to the active portion on the other main surface side of the first conductivity type semiconductor substrate, and the other main surface A first conductivity type buffer layer having a higher concentration than the first conductivity type semiconductor substrate and a lower concentration than the first conductivity type semiconductor layer. The semiconductor device according to claim 1, further comprising a second main electrode that is in ohmic contact with the surface of the first conductivity type semiconductor layer. A peripheral pressure-resistant structure portion is provided on the outer periphery of the active portion via an intermediate region, and the intermediate region has a second recess and a second protruding semiconductor portion that repeats at a predetermined pitch across the second recess. The second recess has a conductor layer embedded via an insulating film, and the first conductivity type carrier injection suppressing layer and the upper surface of the carrier injection suppressing layer are flush with the second recess. The second protruding semiconductor portion having a second conductivity type semiconductor layer in contact with the first protruding semiconductor portion is connected to the first protruding semiconductor portion as an extension portion, and the peripheral breakdown voltage structure portion is embedded through an insulating film. a third recess having a layer, sandwiching the third recess, said third recess and the first conductivity type carrier injection inhibiting layer for the lower end surface flush with the second conductivity type semiconductor layer in contact with the upper surface of the carrier injection inhibiting layer characterized in that it comprises a third protruding semiconductor portions that have a preparative Motomeko first semiconductor device according. The first conductive type carrier injection suppressing layer and the second conductive type semiconductor have a predetermined pattern pitch with the surface structure sandwiching the dielectric film by selective epitaxial growth on the one main surface using the dielectric film as a mask. is deposited on a layer in this order, then the form of the dielectric film as the first recess is removed, a step of forming the first projecting semiconductor portions sandwiching said first recess, said first recess A method for manufacturing a semiconductor device according to claim 1, further comprising: forming a conductor layer through an insulating film. The first conductive type carrier injection suppressing layer and the second conductive type semiconductor layer are sequentially deposited by selective epitaxial growth to which the corresponding first conductive type dopant or second conductive type dopant is added. A method for manufacturing a semiconductor device according to claim 4. After growing the semiconductor single crystal layer obtained by adding the first conductivity type dopant, the semiconductor single crystal layer and the second conductivity type in the upper layer of the second conductivity type dopant ions are implanted to a predetermined depth in the semiconductor layer the method according to claim 5, wherein the forming the first conductivity type carrier injection inhibiting layer of the lower layer and. 5. The semiconductor single crystal layer formed by the selective epitaxial growth is formed to be thicker than a thickness of the dielectric film mask, and is then polished and removed based on the thickness of the dielectric film mask. Semiconductor device manufacturing method. After forming the anode electrode on the one main surface, the other main surface side is ground to a required thickness, and a first conductivity type buffer layer is formed on the entire surface by hydrogen ion implantation from the other main surface, 3. The method of manufacturing a semiconductor device according to claim 2, wherein a first conductivity type semiconductor layer is formed by selective ion implantation on the other main surface corresponding to an active portion of one main surface.

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