CN104347730A - Semiconductor device and method of manufacture - Google Patents

Semiconductor device and method of manufacture Download PDF

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Publication number
CN104347730A
CN104347730A CN201310317313.5A CN201310317313A CN104347730A CN 104347730 A CN104347730 A CN 104347730A CN 201310317313 A CN201310317313 A CN 201310317313A CN 104347730 A CN104347730 A CN 104347730A
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type
well region
surface
region
type well
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CN201310317313.5A
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Chinese (zh)
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姬亚东
陈闽
方绍明
陈志聪
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北大方正集团有限公司
深圳方正微电子有限公司
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Publication of CN104347730A publication Critical patent/CN104347730A/en

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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/6609Diodes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861Diodes

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises an N-type substrate and an epitaxial layer arranged at the surface of the N-type substrate, wherein the epitaxial layer comprises a groove, a metal layer covering the surface of the groove, an insulation layer covering the surface of the epitaxial layer except the groove, and a first P-type well region which is arranged within the surface of the epitaxial layer and surrounds the groove, the first P-type well region separates the metal layer from the epitaxial layer, and the first P-type well region and a contact region of the metal layer realize ohmic contact. According to the semiconductor device and the manufacturing method thereof, a reverse direction leakage current of the device can be effectively reduced.

Description

半导体器件及制造方法 Semiconductor device and method of manufacture

技术领域 FIELD

[0001] 本发明涉及半导体领域,尤其涉及一种半导体器件及制造方法。 [0001] The present invention relates to the field of semiconductors, and more particularly to a semiconductor device manufacturing method.

背景技术 Background technique

[0002]目前,常用的二极管通常包括PN结二极管和肖特基势鱼二极管(SchottkyBarrier D1de,缩写成SBD)等。 [0002] Currently, conventional diode typically comprises a PN junction diode and a Schottky diode fish (SchottkyBarrier D1de, abbreviated as SBD) and the like. 其中,SBD与PN结二极管利用P型半导体与N型半导体接触形成PN结的结构原理不同,SBD采用的是金属与半导体接触形成的肖特基结的结构原理。 Wherein, SBD and PN junction diode P-type semiconductor and N-type semiconductor contact forming a PN junction structure different principles, SBD structure principle is used in a metal-semiconductor contact with a Schottky junction is formed.

[0003] 相对于PN结二极管来说,SBD具备低功耗、反向恢复时间短,正向导通压降低等优点。 [0003] PN junction diode with respect to it, the SBD with low power consumption, short reverse recovery time, the forward voltage drop and the like. 但与此同时,上述两种结构的二极管的反向性能均不理想,尤其是器件的反向漏电流较大,从而导致器件性能的降低。 At the same time, the performance of the two reverse diode structure is not ideal, especially in large reverse leakage current of the device, leading to reduced device performance. 因此,如何有效减小二极管的反向漏电流成为亟待解决的问题。 Therefore, how to reduce the reverse leakage current of the diode becomes a problem to be solved.

发明内容 SUMMARY

[0004] 本发明提供一种半导体器件及制造方法,用于解决现有二极管的反向漏电流较大的问题。 [0004] The present invention provides a semiconductor device and a manufacturing method for solving the problems of the prior large reverse leakage current of the diode.

[0005] 本发明的第一个方面是提供一种半导体器件,包括:N型衬底、位于所述N型衬底表面上的外延层,所述外延层包括凹槽; [0005] The first aspect of the present invention is to provide a semiconductor device, comprising: N type substrate, said epitaxial layer located on the surface of the N-type substrate, said epitaxial layer comprises a recess;

[0006] 覆盖所述凹槽表面的金属层; [0006] covering the surface of the groove of the metal layer;

[0007] 覆盖除所述凹槽之外的所述外延层表面的绝缘层; [0007] The insulating layer covering the surface other than the recess of said epitaxial layer;

[0008] 位于所述外延层表面内,且包围所述凹槽的第一P型阱区,所述第一P型阱区隔离所述金属层和所述外延层; [0008] positioned in the inner surface of the epitaxial layer and surrounding the first P-type well region of the groove, the first P-type well region isolated from the metal layer and the epitaxial layer;

[0009] 其中,所述第一P型阱区和所述金属层的接触区域形成欧姆接触。 [0009] wherein the first P-type well region and the contact region of the ohmic contact metal layer is formed.

[0010] 本发明的另一个方面是提供一种半导体器件制造方法,包括: [0010] Another aspect of the present invention is to provide a semiconductor device manufacturing method, comprising:

[0011] 在N型衬底的外延层的表面上形成绝缘层; [0011] The insulating layer is formed on the surface of the N-type epitaxial layer of the substrate;

[0012] 通过刻蚀,去除预设区域内的所述绝缘层,以露出所述外延层的表面,形成窗口; [0012] By etching, removing the insulating layer in the predetermined region, to expose a surface of the epitaxial layer, forming a window;

[0013] 向所述窗口第一次注入P型杂质,并进行驱入,以形成位于所述外延层表面内的第一P型阱区,所述第一P型阱区对应的区域包含且大于所述窗口对应的区域; [0013] window is first injected into the P-type impurity, and drive-in to form a first P-type well region located in the surface of the epitaxial layer, the first P-type well region corresponding to the region including and larger than the region corresponding to said window;

[0014] 根据预设的刻蚀深度,刻蚀所述窗口对应的区域,以在所述外延层的表面形成凹槽; [0014] according to a predetermined etching depth, etching the region corresponding to the window, to the surface of the epitaxial layer, forming a groove;

[0015] 在所述凹槽的表面上,淀积金属层,以覆盖所述凹槽的表面; [0015] On the surface of the groove, the deposited metal layer to cover the surface of the groove;

[0016] 其中,所述第一P型阱区隔离所述金属层和所述外延层。 [0016] wherein the first P-type well region isolated from the metal layer and the epitaxial layer.

[0017] 本发明提供的半导体器件及制造方法,通过在外延层设置凹槽,并在所述外延层表面内形成包围所述凹槽的P型阱区,且所述P型阱区隔离覆盖在所述凹槽表面的金属层和所述外延层的技术方案,有效减小器件的反向漏电流。 [0017] Semiconductor device and manufacturing method of the present invention provides, by providing a groove in the epitaxial layer, and forming a groove surrounding the P-type well region in a surface of the epitaxial layer and the P-type isolation well region covered the recess in the metal layer and the surface aspect of the epitaxial layer to effectively reduce the reverse leakage current of the device.

附图说明 BRIEF DESCRIPTION

[0018] 图1为本发明实施例一提供的一种半导体器件的剖面示意图; [0018] FIG. 1 is a cross-sectional diagram of a semiconductor device according to a first embodiment of the present invention;

[0019] 图2为本发明实施例二提供的另一种半导体器件的剖面示意图; [0019] FIG. 2 is another cross-sectional view of the semiconductor device according to a second embodiment of the present invention, a schematic diagram;

[0020] 图3为本发明实施例三提供的一种半导体器件制作方法的流程示意图; [0020] FIG. 3 is a schematic flow of the method for fabricating a semiconductor device according to a third embodiment of the present invention;

[0021] 图4-图7为本发明实施例三执行过程中半导体器件的剖面示意图; [0021] FIGS. 4-7 are cross-sectional process three execution example schematic diagram of the semiconductor device of the present embodiment of the invention;

[0022] 图8为本发明实施例四提供的另一种半导体器件的制作方法的流程示意图; [0022] Figure 8 a schematic diagram of another process of the manufacturing method of a semiconductor device according to a fourth embodiment of the present invention;

[0023] 图9为本发明实施例五提供的又一种半导体器件制作方法的流程示意图。 [0023] Figure 9 a schematic flowchart of a further method for fabricating a semiconductor device according to a fifth embodiment of the present invention.

具体实施方式 Detailed ways

[0024] 为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述。 [0024] The object of the present invention, technical solutions, and advantages of the embodiments more clearly, the following embodiments of the present invention in the accompanying drawings, the technical solutions in the embodiments of the present invention will be clearly and fully described. 为了方便说明,放大或者缩小了不同层和区域的尺寸,所以图中所示大小和比例并不一定代表实际尺寸,也不反映尺寸的比例关系。 For convenience of explanation, and enlarged or reduced size of the regions of different layers, so the size and proportions shown in the figures do not necessarily represent the actual size, the size does not reflect the proportional relationship.

[0025] 图1为本发明实施例一提供的一种半导体器件的剖面示意图,如图1所示,所述器件包括:N型衬底11、位于所述N型衬底表面上的外延层12,所述外延层包括凹槽; [0025] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention, shown in Figure 1, the device comprising: N type substrate 11, an epitaxial layer on the substrate surface of said N-type 12, the epitaxial layer comprises a recess;

[0026] 覆盖所述凹槽表面的金属层13 ; [0026] covering the surface of the recess of the metal layer 13;

[0027] 覆盖除所述凹槽之外的外延层12表面的绝缘层14 ; [0027] surface of the insulating cover layer 14 other than the recess 12 of the epitaxial layer;

[0028] 位于外延层12表面内且包围所述凹槽的第一P型阱区15,第一P型阱区15隔离金属层13和外延层12,第一P型阱区15与金属层13的接触区域形成欧姆接触; [0028] epitaxial layer on the inner surface of the recess 12 and surrounding the first P-type well region 15, a first P-type well region 15 and the epitaxial layer 13, a barrier metal layer 12, a first P-type well region 15 and the metal layer contact region 13 is formed in ohmic contact;

[0029] 其中,N型衬底11和外延层12可以为半导体元素,例如单晶硅、多晶硅或非晶结构的硅或硅锗(SiGe),也可以为混合的半导体结构,例如碳化硅、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓、合金半导体或其组合。 [0029] where, N-type epitaxial layer 12 and substrate 11 may be a semiconductor element, such as monocrystalline silicon, polycrystalline silicon or amorphous silicon or silicon germanium structure (SiGe), or may be a mixed structure of a semiconductor such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide alloy semiconductor, or combinations thereof. 本实施例在此不对其进行限制。 The present embodiment is not be limited in this.

[0030] 具体的,金属层13的材料可以为金、银、铝、钼或钥,具体材料的选择可根据实际情况而定。 [0030] Specifically, the material of the metal layer 13 may be gold, silver, aluminum, molybdenum, or key, selection of a particular material may be determined according to the actual situation. 绝缘层14的材料包括二氧化硅。 Material of the insulating layer 14 comprises silicon dioxide.

[0031] 可以理解,在本实施例提供的半导体器件中,第一P型阱区15位于外延层12表面内,包围所述凹槽,且隔离金属层13和外延层12之间的接触,避免金属与半导体的直接接触。 [0031] It will be appreciated, in the present embodiment provides a semiconductor device, the first P-type well region 15 located within the surface of the epitaxial layer 12 surrounding the recess, the contact between the spacer 12 and the metal layer 13 and the epitaxial layer, to avoid direct contact of the metal with the semiconductor. 具体的,第一P型阱区15与金属层13的接触区域形成欧姆接触,第一P型阱区15与外延层12的接触区域形成PN结,以使当该半导体器件被施加反向压降时,第一P型阱区15与外延层12接触形成的PN结反向截止,从而形成耗尽区,并且,随着反向压降的增大,所述耗尽区的宽度逐渐增大,有效阻止反向漏电流,从而有效减小器件的反向漏电流,并使所述器件能够承受较大的反向电压。 Specifically, the first P-type well region 15 is formed in ohmic contact with the contact region of the metal layer 13, a first P-type well region 15 form a PN junction and a contact region of the epitaxial layer 12, so that when the reverse voltage is applied to the semiconductor device when reduced, the contact 15 and the first P-type well region formed in the epitaxial layer 12 reverse blocking PN junction, thereby forming a depletion region, and, with increasing reverse voltage drop, the gradually increasing width of the depletion region large, effectively prevent reverse leakage current, thereby effectively reducing the reverse leakage current of the device, and the device can withstand large reverse voltage.

[0032] 在本实施例的一种实施方式中,所述器件还可以包括: [0032] In one embodiment of the present embodiment, the device may further comprise:

[0033] 位于外延层12表面内和第一P型阱区15内,且处于所述凹槽下方的第二P型阱区16,第二P型阱区16的宽度大于所述凹槽的宽度,第一P型阱区15的宽度大于第二P型阱区16的宽度,第一P型阱区15的杂质浓度小于第二P型阱区16的杂质浓度; [0033] positioned within the inner surface of the epitaxial layer 12 and the first P-type well region 15, and in a second P type well region 16 below the groove width of the second P-type well region 16 is greater than the groove width, the width of the first P-type well region 15 is greater than the width of the second P-type well region 16, a first P-type well region 15 is smaller than the impurity concentration of the impurity concentration of the second P-type well region 16;

[0034] 具体的,第二P型阱区16和金属层13的接触区域形成欧姆接触。 [0034] Specifically, the second P type well region 16 and the contact region of the metal layer 13 forms an ohmic contact. 通常的,杂质浓度高的半导体有利于形成更好的欧姆接触,可以理解,由于第二P型阱区16的杂质浓度大于第一P型阱区15的杂质浓度,因此,通过第二P型阱区的设置,能够通过其与金属层13形成更好的欧姆接触,从而有效降低金属与半导体之间的正向导通电阻,提高器件的正向特性。 Typically, the high impurity concentration semiconductor favor the formation of a better ohmic contact can be appreciated, since the impurity concentration of the second P type well 16 of the first region is greater than the impurity concentration of the P-type well region 15. Therefore, the second P-type the well region is provided, through which the metal layer 13 is formed a better ohmic contact, thus effectively reducing the forward conduction resistance between the metal and the semiconductor, to improve the characteristics of the device forward.

[0035] 本实施例提供的半导体器件,通过在外延层设置凹槽,并在所述外延层表面内形成包围所述凹槽的P型阱区,且所述P型阱区隔离覆盖在所述凹槽表面的金属层和所述外延层的技术方案,有效减小器件的反向漏电流。 [0035] The semiconductor device according to this embodiment, a groove is formed to surround the P-type well region is provided by the inner surface of the epitaxial layer a groove in the epitaxial layer, and the, and the P-type well region in the insulation blanket technical Solution metal layer and the epitaxial layer surface of said recess, effectively reduce the reverse leakage current of the device.

[0036] 图2为本发明实施例二提供的另一种半导体器件的剖面示意图,如图2所示,根据实施例一所述的半导体器件,金属层13还覆盖绝缘层14的上表面和靠近所述凹槽的侧面;所述器件还可以包括: [0036] FIG. 2 is a schematic cross-sectional view of another semiconductor device according to a second embodiment of the invention, as shown, a semiconductor device according to the embodiment, the metal layer 13 also covers the upper surface of the insulating layer 2 and 14 close to the sides of the recess; the device may further comprise:

[0037] 位于第一P型阱区15内的N型区域17,N型区域17围绕所述凹槽的侧面,且与金属层13和绝缘层14均接触; [0037] N-type region of the first P-type well region 15, 17, N-type region 17 surrounds the side surface of the recess, and 14 are in contact with the metal layer 13 and the insulating layer;

[0038] 其中,N型区域17未与外延层12接触,且N型区域17的深度小于所述凹槽的深度。 [0038] where, the N-type region 17 is not in contact with the epitaxial layer 12, N-type region 17 and the depth less than the depth of the groove.

[0039] 可以理解,根据本实施方式提供的半导体器件,当所述半导体器件被施加正向压降时,即在金属层13上施加一个正向电压时,第一P型区域15中位于绝缘层14下方且靠近绝缘层14的区域发生反型,从而在N型区域17和外延层12之间形成导电沟道,实现正向导通;并且,第一P型区域15或第二P型区域16,与外延层12形成的PN结也正向导通,从而使器件实现较大的正向电流。 [0039] It will be appreciated, providing the semiconductor device according to the present embodiment, when the forward voltage is applied to the semiconductor device, i.e., applied to the metal layer 13 when a positive voltage, the insulation 15 is located a first P-type region layer 14 and adjacent to the region below the insulating layer 14 of the inversion occurs, thereby forming a conducting channel between the N-type regions 17 and the epitaxial layer 12, to achieve positive conduction; and, a first P-type region 15 or the second P-type region 16, the PN junction formed in the epitaxial layer 12 is also conducting, enabling the device to achieve a greater forward current.

[0040] 具体的,在本实施方式中,所述器件还可以包括:位于金属层13与绝缘层14之间的多晶硅层18。 [0040] Specifically, in the present embodiment, the device may further comprise: a polysilicon layer 18 located between the insulating layer 13 and the metal layer 14.

[0041] 通过本实施例提供的半导体器件,能够在有效减小器件反向漏电流的同时,有效改善器件的正向特性,提高器件的性能。 [0041] The semiconductor device provided by the present embodiment, it is possible while effectively reducing the reverse leakage current of the device, improve the forward characteristics of the device, improve the performance of the device.

[0042] 图3为本发明实施例三提供的一种半导体器件制作方法的流程示意图,为了对本实施例中的方法进行清楚系统的描述,图4-图7为实施例三执行过程中半导体器件的剖面示意图,如图3所示,所述方法包括以下步骤: [0042] FIG. 3 is a schematic flowchart of method for manufacturing a semiconductor device according to a third embodiment of the present invention, in order to perform a clear description of the system of the present embodiment of the method, 4-7 is performed during three embodiments of a semiconductor device the cross-sectional schematic view, shown in Figure 3, the method comprising the steps of:

[0043] 301、在N型衬底的外延层的表面上形成绝缘层。 [0043] 301, the insulating layer is formed on the surface of the N-type epitaxial layer of the substrate.

[0044] 具体地,执行301之后的所述半导体器件的剖面示意图如图4所示,其中,所述N型衬底用标号11表示,所述外延层用标号12表示,所述绝缘层用标号14表示。 [0044] In particular, the cross-sectional performed after the semiconductor device 301 shown in Figure 4 a schematic view, wherein the N-type substrate is indicated by reference numeral 11, the reference numeral 12 denotes an epitaxial layer, said insulating layer numeral 14.

[0045] 302、通过刻蚀,去除预设区域内的绝缘层,以露出外延层的表面,形成窗口。 [0045] 302 by etching, removing the insulating layer in a predetermined area, to expose the surface of the epitaxial layer, forming a window.

[0046] 具体地,执行302之后的所述半导体器件的剖面示意图如图5所示。 [0046] In particular, the cross-sectional performed after the semiconductor device 302 is schematically shown in FIG.

[0047] 303、向所述窗口第一次注入P型杂质,并进行驱入,以形成位于所述外延层表面内的第一P型阱区,所述第一P型阱区对应的区域包含且大于所述窗口对应的区域。 [0047] 303, the first window to the implanted P-type impurity, and drive-in to form a first P-type well region located in the surface of the epitaxial layer, the first P-type well region corresponding to the region It includes and is larger than the region corresponding to the window.

[0048] 具体地,执行303之后的所述半导体器件的剖面示意图如图6所示,其中,所述第一 P型讲区用标号15表不。 [0048] In particular, the cross-sectional performed after the semiconductor device 303 As shown in Figure 6, wherein the first P-type region with the reference numeral 15 speaks table is not.

[0049] 304、根据预设的刻蚀深度,刻蚀所述窗口对应的区域,以在所述外延层的表面形成凹槽。 [0049] 304, according to a predetermined etching depth, etching the region corresponding to the window, to the surface of the epitaxial layer is formed in the recess.

[0050] 具体地,执行304之后的所述半导体器件的剖面示意图如图7所示。 [0050] In particular, the cross-sectional performed after the semiconductor device 304 is schematically shown in Fig.

[0051] 305、在所述凹槽的表面上,淀积金属层,以覆盖所述凹槽的表面。 [0051] 305, on the surface of the groove, the deposited metal layer to cover the surface of the groove.

[0052] 其中,所述第一P型阱区隔离所述金属层和所述外延层。 [0052] wherein the first P-type well region isolated from the metal layer and the epitaxial layer.

[0053] 具体地,执行305之后的所述半导体器件的剖面示意图如图1所示,其中,所述金属层用标号13表不。 [0053] In particular, the cross-sectional performed after the semiconductor device 305 shown in Figure 1., wherein the metal layer with no reference numeral 13 table.

[0054] 在实际应用中,所述金属层的覆盖范围可以包括但不限于所述凹槽表面,也可为所述凹槽和所述绝缘层的表面,图中给出的只是一种具体的实施方式而并未对其进行限制。 [0054] In practical applications, coverage of the metal layer may include but are not limited to the groove surface, the groove may be a surface of the insulating layer and, FIG given only one specific embodiments and not to limit it.

[0055] 本实施例提供的半导体器件,通过在外延层设置凹槽,并在所述外延层表面内形成包围所述凹槽的P型阱区,且所述P型阱区隔离覆盖在所述凹槽表面的金属层和所述外延层的技术方案,有效减小器件的反向漏电流。 [0055] The semiconductor device according to this embodiment, a groove is formed to surround the P-type well region is provided by the inner surface of the epitaxial layer a groove in the epitaxial layer, and the, and the P-type well region in the insulation blanket technical Solution metal layer and the epitaxial layer surface of said recess, effectively reduce the reverse leakage current of the device.

[0056] 图8为本发明实施例四提供的另一种半导体器件的制作方法的流程示意图,如图8所示,根据实施例二所述的半导体器件制作方法,为了提高该半导体器件的正向特性,在本实施例一种可实施的方式中,在304之后,所述方法还可以包括: [0056] Figure 8 a schematic flow diagram of another method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. As shown, the method for fabricating a semiconductor device according to the second embodiment, in order to improve the positive semiconductor device 8 the characteristics, in an embodiment of the present embodiment, after 304, the method may further comprise:

[0057] 801、向所述凹槽第二次注入P型杂质,并进行驱入,以形成位于所述第一P型阱区内且处于所述凹槽下方的第二P型阱区。 [0057] 801, is injected into the recess second P-type impurity, and drive-in to form the second P type well region located in the first P-type well region and is located below the groove.

[0058] 具体的,第一次注入P型杂质的能量大于第二次注入P型杂质的能量,且第一次注入P型杂质的杂质剂量小于第二次注入P型杂质的杂质剂量,并且,所述第二P型阱区对应的区域包含且大于所述凹槽对应的区域,所述第一P型阱区对应的区域包含且大于所述第二 P型阱区对应的区域。 Energy [0058] Specifically, the first implant energy is greater than the P-type second impurity implanted P-type impurities, and the first dose of impurity implanted P-type impurity is less than the second dose of impurity implanted P-type impurities, and the second P type well region comprises a region corresponding to the groove and greater than the corresponding region of the first P-type well region comprises a region corresponding to and larger than the second P type well region corresponding to the region.

[0059] 本实施例提供的方法,通过形成第二P型阱区,能够使其与金属层形成更好的欧姆接触,从而有效降低金属与半导体之间的正向导通电阻,提高器件的正向特性。 [0059] The method provided in the present embodiment, by forming the second P-type well region, it is possible to form a better ohmic contact with the metal layer, thus effectively reducing the forward conduction resistance between the metal and the semiconductor, to improve the device's positive the characteristics.

[0060] 图9为本发明实施例五提供的又一种半导体器件制作方法的流程示意图,如图9所示,根据上述任一实施例所述的半导体器件制作方法,为了进一步提高半导体器件的正向特性,在304之前,还可以包括: [0060] FIG. 9 yet another schematic flow chart of the method for fabricating a semiconductor device according to a fifth embodiment of the invention, shown in Figure 9, the production method of a semiconductor device according to any preceding embodiment, in order to further improve a semiconductor device forward characteristics, before 304, it may also include:

[0061] 901、向所述窗口注入N型杂质,并进行驱入,以形成位于所述第一P型阱区内的N型阱区,所述第一P型阱区对应的区域包含且大于所述N型阱区对应的区域,所述N型阱区对应的区域包含且大于所述窗口对应的区域; [0061] 901, the window is injected into the N-type impurity, and drive-in to form P-type in the first well region of the N-type well region, said first region corresponding to the P-type well region and containing N-type well region is larger than the corresponding region of the N-type well region and containing the region corresponding to the window is larger than the corresponding region;

[0062] 则相应的,304具体包括: [0062] the corresponding 304 comprises:

[0063] 902、以大于所述N型阱区的深度的所述刻蚀深度,刻蚀所述窗口对应的区域,以去除所述N型阱区中位于所述窗口下方的区域,保留所述N型阱区中位于所述绝缘层下方的区域; The etch depth, etching the region corresponding to the depth of the window [0063] 902, greater than the N-type well region, to remove the N-type well region located below the window region, reservations said N-type well region located in the region below the insulating layer;

[0064] 相应的,305具体包括: [0064] Accordingly, 305 comprises:

[0065] 903、在所述凹槽的表面上、所述绝缘层的上表面和靠近所述凹槽的侧面上,淀积金属层,以覆盖所述凹槽的表面、及所述绝缘层的上表面和靠近所述凹槽的侧面。 [0065] 903, on the surface of the groove, the upper surface of the insulating layer near the upper and side surfaces of the groove, the deposited metal layer to cover the surface of the groove, and the insulating layer near the upper surface and side surfaces of the groove.

[0066] 可选的,在本实施方式中,在302之前,还可以包括: [0066] Alternatively, in the present embodiment, prior to 302, may further comprise:

[0067] 904、在所述绝缘层的表面上形成多晶硅层,并光刻所述多晶硅层,以露出所述区域内所述绝缘层的表面。 [0067] 904, is formed on the surface of the insulating layer is a polysilicon layer, and patterning said polysilicon layer to expose the surface of the insulating layer in the region.

[0068] 通过上述实施方式,能够在有效减小器件反向漏电流的同时,有效改善器件的正向特性,提高器件的性能。 [0068] By the above-described embodiment, it is possible while effectively reducing the reverse leakage current of the device, improve the forward characteristics of the device, improve the performance of the device.

[0069] 需要说明的是,依次执行步骤301、904、302、303、901、902、801、903之后,可以得到如图2所示的半导体器件。 [0069] Incidentally, after 301,904,302,303,901,902,801,903 can be obtained by sequentially performing the steps of the semiconductor device shown in FIG. 2. 具体的,本实施例中各结构的标号与前述实施例中各结构的标号对应。 Specifically, each of the foregoing embodiments with reference numerals corresponding to the structure of each component in the embodiment of the present embodiment.

[0070] 本实施例提供的半导体器件,能够在有效减小器件反向漏电流的同时,有效改善器件的正向特性,提高器件的性能。 [0070] The present semiconductor device according to an embodiment, it is possible while effectively reducing the reverse leakage current of the device, improve the forward characteristics of the device, improve the performance of the device.

[0071] 所属领域的技术人员可以清楚地了解到,为描述的方便和简洁,前述各实施例中器件的具体制作方法,可以参考上述方法实施例中的对应过程。 [0071] Those skilled in the art may clearly understand that, for convenience and brevity of description, specific examples device manufacturing method in the foregoing embodiments, may refer to the corresponding process in the above method embodiments.

[0072] 最后应说明的是:以上各实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述各实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分或者全部技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的范围。 [0072] Finally, it should be noted that: the above embodiments only describe the technical solutions in embodiments of the present invention, rather than limiting;. Although the embodiments of the present invention has been described in detail, those of ordinary skill in the art should appreciated: it still may be made to the technical solutions described embodiments modifications, or to some or all of the technical features equivalents; as such modifications or replacements do not cause the essence of corresponding technical solutions to depart from embodiments of the present invention range of technical solutions.

Claims (10)

1.一种半导体器件,其特征在于,包括:N型衬底、位于所述N型衬底表面上的外延层,所述外延层包括凹槽; 覆盖所述凹槽表面的金属层; 覆盖除所述凹槽之外的所述外延层表面的绝缘层; 位于所述外延层表面内,且包围所述凹槽的第一P型阱区,所述第一P型阱区隔离所述金属层和所述外延层; 其中,所述第一P型阱区和所述金属层的接触区域形成欧姆接触。 1. A semiconductor device, characterized by comprising: N type substrate, said epitaxial layer located on the surface of the N-type substrate, said epitaxial layer comprises a recess; a metal layer covering the surface of the groove; covering the surface of the insulating layer of the epitaxial layers other than the recess; located within the surface of the epitaxial layer and surrounding the first P-type well region of the groove, the first P-type well region isolated from the metal layer and the epitaxial layer; wherein the first P-type well region and the contact region of the ohmic contact metal layer is formed.
2.根据权利要求1所述的器件,其特征在于,所述器件还包括: 位于所述外延层表面内和所述第一P型阱区内,且处于所述凹槽下方的第二P型阱区,所述第二P型阱区的宽度大于所述凹槽的宽度,所述第一P型阱区的宽度大于所述第二P型阱区的宽度,所述第一P型阱区的杂质浓度小于所述第二P型阱区的杂质浓度; 其中,所述第二P型阱区和所述金属层的接触区域形成欧姆接触。 2. The device according to claim 1, wherein said device further comprises: in said epitaxial layer and the inner surface of the first P-type well region, and in a second groove below the P type well region, said second P-type well region width greater than a width of the groove width of the first P-type well region is greater than a width of the second P-type well region, a first P-type the impurity concentration of the well region is smaller than the impurity concentration of the second P-type well region; wherein the second P type well region and the contact region of the ohmic contact metal layer is formed.
3.根据权利要求1或2所述的器件,其特征在于,所述金属层还覆盖所述绝缘层的上表面和靠近所述凹槽的侧面;所述器件还包括: 位于所述第一P型阱区内的N型区域,所述N型区域围绕所述凹槽的侧面,且与所述金属层和所述绝缘层均接触; 其中,所述N型区域未与所述外延层接触,且所述N型区域的深度小于所述凹槽的深度。 3. The device of claim 1 or claim 2, wherein the metal layer further covers the upper surface of the insulating layer near the side surface and the recess; said device further comprising: in the first N-type region of the P-type well region, the N-type region around the side surface of the recess, and are in contact with the metal layer and the insulating layer; wherein the N-type epitaxial layer and said region is not contacting the N-type region and a depth less than the depth of the groove.
4.根据权利要求3所述的器件,其特征在于,所述器件还包括:位于所述金属层与所述绝缘层之间的多晶硅层。 4. The device of claim 3, wherein said device further comprises: a polysilicon layer located between the metal layer and the insulating layer.
5.根据权利要求1所述的器件,其特征在于,所述N型衬底为饱和掺杂的N型单晶硅; 所述外延层为掺杂浓度低于所述N型衬底的掺杂浓度的N型单晶硅。 5. The device according to claim 1, wherein said substrate is a saturated N-type doped N-type silicon single crystal; the epitaxial layer is lower than the doping concentration of doped N-type substrate heteroaryl N-type silicon single crystal concentration.
6.一种半导体器件制造方法,其特征在于,包括: 在N型衬底的外延层的表面上形成绝缘层; 通过刻蚀,去除预设区域内的所述绝缘层,以露出所述外延层的表面,形成窗口; 向所述窗口第一次注入P型杂质,并进行驱入,以形成位于所述外延层表面内的第一P型阱区,所述第一P型阱区对应的区域包含且大于所述窗口对应的区域; 根据预设的刻蚀深度,刻蚀所述窗口对应的区域,以在所述外延层的表面形成凹槽; 在所述凹槽的表面上,淀积金属层,以覆盖所述凹槽的表面; 其中,所述第一P型阱区隔离所述金属层和所述外延层。 A semiconductor device manufacturing method, comprising: forming an insulating layer on the substrate surface of the N-type epitaxial layer; by etching, removing the insulating layer in the predetermined area, to expose the epitaxial the surface layer form a window; P-type impurities implanted to the first window, and drive-in to form a first P-type well region located in the surface of the epitaxial layer, the first P-type well region corresponding to and larger than the area of ​​the region including the corresponding window; according to a predetermined etching depth, etching the region corresponding to the window, to the surface of the epitaxial layer, forming a groove; on the surface of the groove, depositing a metal layer to cover the surface of the groove; wherein the first P-type well region isolated from the metal layer and the epitaxial layer.
7.根据权利要求6所述的方法,其特征在于,所述根据预设的刻蚀深度,刻蚀所述窗口对应的区域,以在所述外延层的表面形成凹槽之后,还包括: 向所述凹槽第二次注入P型杂质,并进行驱入,以形成位于所述第一P型阱区内且处于所述凹槽下方的第二P型阱区; 其中,第一次注入P型杂质的能量大于第二次注入P型杂质的能量,第一次注入P型杂质的杂质剂量小于第二次注入P型杂质的杂质剂量,所述第二P型阱区对应的区域包含且大于所述凹槽对应的区域,所述第一P型阱区对应的区域包含且大于所述第二P型阱区对应的区域。 7. The method according to claim 6, wherein, according to said predetermined etching depth, etching the region corresponding to the window, after forming the recess to the surface of the epitaxial layer, further comprising: injecting into said groove second P-type impurity, and drive-in to form the second P type well region located in the first P-type well region and is located below said groove; wherein the first P-type impurity implantation region energy greater than the energy of the second P-type impurity is implanted, the first dose of impurity implanted P-type impurity is less than the second dose of impurity implanted P-type impurities, the second P type well region corresponding includes and is larger than a region corresponding to the recess, the first P-type well region comprises a region corresponding to and larger than the second P type well region corresponding to the region.
8.根据权利要求6或7所述的方法,其特征在于,所述根据预设的刻蚀深度,刻蚀所述窗口对应的区域之前,还包括: 向所述窗口注入N型杂质,并进行驱入,以形成位于所述第一P型阱区内的N型阱区,所述第一P型阱区对应的区域包含且大于所述N型阱区对应的区域,所述N型阱区对应的区域包含且大于所述窗口对应的区域; 所述根据预设的刻蚀深度,刻蚀所述窗口对应的区域,具体包括: 以大于所述N型阱区的深度的所述刻蚀深度,刻蚀所述窗口对应的区域,以去除所述N型阱区中位于所述窗口下方的区域,保留所述N型阱区中位于所述绝缘层下方的区域;所述在所述凹槽的表面上,淀积金属层,以覆盖所述凹槽的表面,具体包括: 在所述凹槽的表面上、所述绝缘层的上表面和靠近所述凹槽的侧面上,淀积金属层,以覆盖所述凹槽的表面、及所述绝缘层的上表 8. The method of claim 6 or claim 7, wherein, according to said predetermined etching depth, before etching the region corresponding to said window, further comprising: an N-type impurity implanted to the window, and for drive-in to form P-type in the first well region of the N-type well region, a first P-type well region and larger than a region corresponding to the region comprising the N-type well region corresponding to the N-type well region corresponding to the region including the region and is larger than the corresponding window; preset according to the etching depth, etching the region corresponding to the window, comprises: a depth greater than the N-type well region etch depth, etching the region corresponding to the window, to remove the N-type well region located below the window area, a reserved area in the N-type well region located below the insulating layer; in the the upper surface of the groove, the deposited metal layer to cover the surface of the recess, comprises: a recess on the surface, close to the upper surface and side surface of the recess of the insulating layer , deposited metal layer to cover the surface of the groove, and the insulating layer on the table 和靠近所述凹槽的侧面。 And side surfaces adjacent to the recess.
9.根据权利要求8所述的方法,其特征在于,所述通过刻蚀,去除预设区域内的所述绝缘层之前,还包括: 在所述绝缘层的表面上形成多晶硅层; 光刻所述多晶硅层,以露出所述区域内所述绝缘层的表面; 所述在所述凹槽的表面上,淀积金属层,以覆盖所述凹槽的表面,具体包括: 在所述凹槽的表面上、所述多晶硅层的上表面和靠近所述凹槽的侧面上,淀积金属层,以覆盖所述凹槽的表面、及所述多晶硅层的上表面和靠近所述凹槽的侧面。 9. The method according to previous claim 8, wherein said etching by removing the insulating layer in the preset region, further comprising: forming a polysilicon layer on a surface of the insulating layer; lithography said polysilicon layer to expose the surface of the insulating layer within said region; on the surface of the groove, the deposited metal layer to cover the surface of the recess, comprises: in said recess the upper surface of the groove, an upper surface of said polysilicon layer near the side grooves and the deposited metal layer to cover the surface of the groove, and the upper surface of said polysilicon layer near the recess and side.
10.根据权利要求8所述的方法,其特征在于,所述N型杂质为砷;所述P型杂质为硼。 10. The method according to claim 8, wherein said N-type impurity is arsenic; the P-type impurity is boron.
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