CN104347730A - Semiconductor device and method of manufacture - Google Patents

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. The semiconductor device comprises an N-type substrate and an epitaxial layer arranged at the surface of the N-type substrate, wherein the epitaxial layer comprises a groove, a metal layer covering the surface of the groove, an insulation layer covering the surface of the epitaxial layer except the groove, and a first P-type well region which is arranged within the surface of the epitaxial layer and surrounds the groove, the first P-type well region separates the metal layer from the epitaxial layer, and the first P-type well region and a contact region of the metal layer realize ohmic contact. According to the semiconductor device and the manufacturing method thereof, a reverse direction leakage current of the device can be effectively reduced.

Description

Semiconductor device and method of manufacture

FIELD

[0001] The present invention relates to the field of semiconductors, and more particularly to a semiconductor device manufacturing method.

Background technique

[0002] Currently, conventional diode typically comprises a PN junction diode and a Schottky diode fish (SchottkyBarrier D1de, abbreviated as SBD) and the like. Wherein, SBD and PN junction diode P-type semiconductor and N-type semiconductor contact forming a PN junction structure different principles, SBD structure principle is used in a metal-semiconductor contact with a Schottky junction is formed.

[0003] PN junction diode with respect to it, the SBD with low power consumption, short reverse recovery time, the forward voltage drop and the like. At the same time, the performance of the two reverse diode structure is not ideal, especially in large reverse leakage current of the device, leading to reduced device performance. Therefore, how to reduce the reverse leakage current of the diode becomes a problem to be solved.

SUMMARY

[0004] The present invention provides a semiconductor device and a manufacturing method for solving the problems of the prior large reverse leakage current of the diode.

[0005] The first aspect of the present invention is to provide a semiconductor device, comprising: N type substrate, said epitaxial layer located on the surface of the N-type substrate, said epitaxial layer comprises a recess;

[0006] covering the surface of the groove of the metal layer;

[0007] The insulating layer covering the surface other than the recess of said epitaxial layer;

[0008] positioned in the inner surface of the epitaxial layer and surrounding the first P-type well region of the groove, the first P-type well region isolated from the metal layer and the epitaxial layer;

[0009] wherein the first P-type well region and the contact region of the ohmic contact metal layer is formed.

[0010] Another aspect of the present invention is to provide a semiconductor device manufacturing method, comprising:

[0011] The insulating layer is formed on the surface of the N-type epitaxial layer of the substrate;

[0012] By etching, removing the insulating layer in the predetermined region, to expose a surface of the epitaxial layer, forming a window;

[0013] window is first injected into the P-type impurity, and drive-in to form a first P-type well region located in the surface of the epitaxial layer, the first P-type well region corresponding to the region including and larger than the region corresponding to said window;

[0014] according to a predetermined etching depth, etching the region corresponding to the window, to the surface of the epitaxial layer, forming a groove;

[0015] On the surface of the groove, the deposited metal layer to cover the surface of the groove;

[0016] wherein the first P-type well region isolated from the metal layer and the epitaxial layer.

[0017] Semiconductor device and manufacturing method of the present invention provides, by providing a groove in the epitaxial layer, and forming a groove surrounding the P-type well region in a surface of the epitaxial layer and the P-type isolation well region covered the recess in the metal layer and the surface aspect of the epitaxial layer to effectively reduce the reverse leakage current of the device.

BRIEF DESCRIPTION

[0018] FIG. 1 is a cross-sectional diagram of a semiconductor device according to a first embodiment of the present invention;

[0019] FIG. 2 is another cross-sectional view of the semiconductor device according to a second embodiment of the present invention, a schematic diagram;

[0020] FIG. 3 is a schematic flow of the method for fabricating a semiconductor device according to a third embodiment of the present invention;

[0021] FIGS. 4-7 are cross-sectional process three execution example schematic diagram of the semiconductor device of the present embodiment of the invention;

[0022] Figure 8 a schematic diagram of another process of the manufacturing method of a semiconductor device according to a fourth embodiment of the present invention;

[0023] Figure 9 a schematic flowchart of a further method for fabricating a semiconductor device according to a fifth embodiment of the present invention.

Detailed ways

[0024] The object of the present invention, technical solutions, and advantages of the embodiments more clearly, the following embodiments of the present invention in the accompanying drawings, the technical solutions in the embodiments of the present invention will be clearly and fully described. For convenience of explanation, and enlarged or reduced size of the regions of different layers, so the size and proportions shown in the figures do not necessarily represent the actual size, the size does not reflect the proportional relationship.

[0025] FIG. 1 is a schematic cross-sectional view of a semiconductor device according to a first embodiment of the present invention, shown in Figure 1, the device comprising: N type substrate 11, an epitaxial layer on the substrate surface of said N-type 12, the epitaxial layer comprises a recess;

[0026] covering the surface of the recess of the metal layer 13;

[0027] surface of the insulating cover layer 14 other than the recess 12 of the epitaxial layer;

[0028] epitaxial layer on the inner surface of the recess 12 and surrounding the first P-type well region 15, a first P-type well region 15 and the epitaxial layer 13, a barrier metal layer 12, a first P-type well region 15 and the metal layer contact region 13 is formed in ohmic contact;

[0029] where, N-type epitaxial layer 12 and substrate 11 may be a semiconductor element, such as monocrystalline silicon, polycrystalline silicon or amorphous silicon or silicon germanium structure (SiGe), or may be a mixed structure of a semiconductor such as silicon carbide, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide alloy semiconductor, or combinations thereof. The present embodiment is not be limited in this.

[0030] Specifically, the material of the metal layer 13 may be gold, silver, aluminum, molybdenum, or key, selection of a particular material may be determined according to the actual situation. Material of the insulating layer 14 comprises silicon dioxide.

[0031] It will be appreciated, in the present embodiment provides a semiconductor device, the first P-type well region 15 located within the surface of the epitaxial layer 12 surrounding the recess, the contact between the spacer 12 and the metal layer 13 and the epitaxial layer, to avoid direct contact of the metal with the semiconductor. Specifically, the first P-type well region 15 is formed in ohmic contact with the contact region of the metal layer 13, a first P-type well region 15 form a PN junction and a contact region of the epitaxial layer 12, so that when the reverse voltage is applied to the semiconductor device when reduced, the contact 15 and the first P-type well region formed in the epitaxial layer 12 reverse blocking PN junction, thereby forming a depletion region, and, with increasing reverse voltage drop, the gradually increasing width of the depletion region large, effectively prevent reverse leakage current, thereby effectively reducing the reverse leakage current of the device, and the device can withstand large reverse voltage.

[0032] In one embodiment of the present embodiment, the device may further comprise:

[0033] positioned within the inner surface of the epitaxial layer 12 and the first P-type well region 15, and in a second P type well region 16 below the groove width of the second P-type well region 16 is greater than the groove width, the width of the first P-type well region 15 is greater than the width of the second P-type well region 16, a first P-type well region 15 is smaller than the impurity concentration of the impurity concentration of the second P-type well region 16;

[0034] Specifically, the second P type well region 16 and the contact region of the metal layer 13 forms an ohmic contact. Typically, the high impurity concentration semiconductor favor the formation of a better ohmic contact can be appreciated, since the impurity concentration of the second P type well 16 of the first region is greater than the impurity concentration of the P-type well region 15. Therefore, the second P-type the well region is provided, through which the metal layer 13 is formed a better ohmic contact, thus effectively reducing the forward conduction resistance between the metal and the semiconductor, to improve the characteristics of the device forward.

[0035] The semiconductor device according to this embodiment, a groove is formed to surround the P-type well region is provided by the inner surface of the epitaxial layer a groove in the epitaxial layer, and the, and the P-type well region in the insulation blanket technical Solution metal layer and the epitaxial layer surface of said recess, effectively reduce the reverse leakage current of the device.

[0036] FIG. 2 is a schematic cross-sectional view of another semiconductor device according to a second embodiment of the invention, as shown, a semiconductor device according to the embodiment, the metal layer 13 also covers the upper surface of the insulating layer 2 and 14 close to the sides of the recess; the device may further comprise:

[0037] N-type region of the first P-type well region 15, 17, N-type region 17 surrounds the side surface of the recess, and 14 are in contact with the metal layer 13 and the insulating layer;

[0038] where, the N-type region 17 is not in contact with the epitaxial layer 12, N-type region 17 and the depth less than the depth of the groove.

[0039] It will be appreciated, providing the semiconductor device according to the present embodiment, when the forward voltage is applied to the semiconductor device, i.e., applied to the metal layer 13 when a positive voltage, the insulation 15 is located a first P-type region layer 14 and adjacent to the region below the insulating layer 14 of the inversion occurs, thereby forming a conducting channel between the N-type regions 17 and the epitaxial layer 12, to achieve positive conduction; and, a first P-type region 15 or the second P-type region 16, the PN junction formed in the epitaxial layer 12 is also conducting, enabling the device to achieve a greater forward current.

[0040] Specifically, in the present embodiment, the device may further comprise: a polysilicon layer 18 located between the insulating layer 13 and the metal layer 14.

[0041] The semiconductor device provided by the present embodiment, it is possible while effectively reducing the reverse leakage current of the device, improve the forward characteristics of the device, improve the performance of the device.

[0042] FIG. 3 is a schematic flowchart of method for manufacturing a semiconductor device according to a third embodiment of the present invention, in order to perform a clear description of the system of the present embodiment of the method, 4-7 is performed during three embodiments of a semiconductor device the cross-sectional schematic view, shown in Figure 3, the method comprising the steps of:

[0043] 301, the insulating layer is formed on the surface of the N-type epitaxial layer of the substrate.

[0044] In particular, the cross-sectional performed after the semiconductor device 301 shown in Figure 4 a schematic view, wherein the N-type substrate is indicated by reference numeral 11, the reference numeral 12 denotes an epitaxial layer, said insulating layer numeral 14.

[0045] 302 by etching, removing the insulating layer in a predetermined area, to expose the surface of the epitaxial layer, forming a window.

[0046] In particular, the cross-sectional performed after the semiconductor device 302 is schematically shown in FIG.

[0047] 303, the first window to the implanted P-type impurity, and drive-in to form a first P-type well region located in the surface of the epitaxial layer, the first P-type well region corresponding to the region It includes and is larger than the region corresponding to the window.

[0048] In particular, the cross-sectional performed after the semiconductor device 303 As shown in Figure 6, wherein the first P-type region with the reference numeral 15 speaks table is not.

[0049] 304, according to a predetermined etching depth, etching the region corresponding to the window, to the surface of the epitaxial layer is formed in the recess.

[0050] In particular, the cross-sectional performed after the semiconductor device 304 is schematically shown in Fig.

[0051] 305, on the surface of the groove, the deposited metal layer to cover the surface of the groove.

[0052] wherein the first P-type well region isolated from the metal layer and the epitaxial layer.

[0053] In particular, the cross-sectional performed after the semiconductor device 305 shown in Figure 1., wherein the metal layer with no reference numeral 13 table.

[0054] In practical applications, coverage of the metal layer may include but are not limited to the groove surface, the groove may be a surface of the insulating layer and, FIG given only one specific embodiments and not to limit it.

[0055] The semiconductor device according to this embodiment, a groove is formed to surround the P-type well region is provided by the inner surface of the epitaxial layer a groove in the epitaxial layer, and the, and the P-type well region in the insulation blanket technical Solution metal layer and the epitaxial layer surface of said recess, effectively reduce the reverse leakage current of the device.

[0056] Figure 8 a schematic flow diagram of another method for manufacturing a semiconductor device according to a fourth embodiment of the present invention. As shown, the method for fabricating a semiconductor device according to the second embodiment, in order to improve the positive semiconductor device 8 the characteristics, in an embodiment of the present embodiment, after 304, the method may further comprise:

[0057] 801, is injected into the recess second P-type impurity, and drive-in to form the second P type well region located in the first P-type well region and is located below the groove.

Energy [0058] Specifically, the first implant energy is greater than the P-type second impurity implanted P-type impurities, and the first dose of impurity implanted P-type impurity is less than the second dose of impurity implanted P-type impurities, and the second P type well region comprises a region corresponding to the groove and greater than the corresponding region of the first P-type well region comprises a region corresponding to and larger than the second P type well region corresponding to the region.

[0059] The method provided in the present embodiment, by forming the second P-type well region, it is possible to form a better ohmic contact with the metal layer, thus effectively reducing the forward conduction resistance between the metal and the semiconductor, to improve the device's positive the characteristics.

[0060] FIG. 9 yet another schematic flow chart of the method for fabricating a semiconductor device according to a fifth embodiment of the invention, shown in Figure 9, the production method of a semiconductor device according to any preceding embodiment, in order to further improve a semiconductor device forward characteristics, before 304, it may also include:

[0061] 901, the window is injected into the N-type impurity, and drive-in to form P-type in the first well region of the N-type well region, said first region corresponding to the P-type well region and containing N-type well region is larger than the corresponding region of the N-type well region and containing the region corresponding to the window is larger than the corresponding region;

[0062] the corresponding 304 comprises:

The etch depth, etching the region corresponding to the depth of the window [0063] 902, greater than the N-type well region, to remove the N-type well region located below the window region, reservations said N-type well region located in the region below the insulating layer;

[0064] Accordingly, 305 comprises:

[0065] 903, on the surface of the groove, the upper surface of the insulating layer near the upper and side surfaces of the groove, the deposited metal layer to cover the surface of the groove, and the insulating layer near the upper surface and side surfaces of the groove.

[0066] Alternatively, in the present embodiment, prior to 302, may further comprise:

[0067] 904, is formed on the surface of the insulating layer is a polysilicon layer, and patterning said polysilicon layer to expose the surface of the insulating layer in the region.

[0068] By the above-described embodiment, it is possible while effectively reducing the reverse leakage current of the device, improve the forward characteristics of the device, improve the performance of the device.

[0069] Incidentally, after 301,904,302,303,901,902,801,903 can be obtained by sequentially performing the steps of the semiconductor device shown in FIG. 2. Specifically, each of the foregoing embodiments with reference numerals corresponding to the structure of each component in the embodiment of the present embodiment.

[0070] The present semiconductor device according to an embodiment, it is possible while effectively reducing the reverse leakage current of the device, improve the forward characteristics of the device, improve the performance of the device.

[0071] Those skilled in the art may clearly understand that, for convenience and brevity of description, specific examples device manufacturing method in the foregoing embodiments, may refer to the corresponding process in the above method embodiments.

[0072] Finally, it should be noted that: the above embodiments only describe the technical solutions in embodiments of the present invention, rather than limiting;. Although the embodiments of the present invention has been described in detail, those of ordinary skill in the art should appreciated: it still may be made to the technical solutions described embodiments modifications, or to some or all of the technical features equivalents; as such modifications or replacements do not cause the essence of corresponding technical solutions to depart from embodiments of the present invention range of technical solutions.

Claims (10)

1. A semiconductor device, characterized by comprising: N type substrate, said epitaxial layer located on the surface of the N-type substrate, said epitaxial layer comprises a recess; a metal layer covering the surface of the groove; covering the surface of the insulating layer of the epitaxial layers other than the recess; located within the surface of the epitaxial layer and surrounding the first P-type well region of the groove, the first P-type well region isolated from the metal layer and the epitaxial layer; wherein the first P-type well region and the contact region of the ohmic contact metal layer is formed.

2. The device according to claim 1, wherein said device further comprises: in said epitaxial layer and the inner surface of the first P-type well region, and in a second groove below the P type well region, said second P-type well region width greater than a width of the groove width of the first P-type well region is greater than a width of the second P-type well region, a first P-type the impurity concentration of the well region is smaller than the impurity concentration of the second P-type well region; wherein the second P type well region and the contact region of the ohmic contact metal layer is formed.

3. The device of claim 1 or claim 2, wherein the metal layer further covers the upper surface of the insulating layer near the side surface and the recess; said device further comprising: in the first N-type region of the P-type well region, the N-type region around the side surface of the recess, and are in contact with the metal layer and the insulating layer; wherein the N-type epitaxial layer and said region is not contacting the N-type region and a depth less than the depth of the groove.

4. The device of claim 3, wherein said device further comprises: a polysilicon layer located between the metal layer and the insulating layer.

5. The device according to claim 1, wherein said substrate is a saturated N-type doped N-type silicon single crystal; the epitaxial layer is lower than the doping concentration of doped N-type substrate heteroaryl N-type silicon single crystal concentration.

A semiconductor device manufacturing method, comprising: forming an insulating layer on the substrate surface of the N-type epitaxial layer; by etching, removing the insulating layer in the predetermined area, to expose the epitaxial the surface layer form a window; P-type impurities implanted to the first window, and drive-in to form a first P-type well region located in the surface of the epitaxial layer, the first P-type well region corresponding to and larger than the area of ​​the region including the corresponding window; according to a predetermined etching depth, etching the region corresponding to the window, to the surface of the epitaxial layer, forming a groove; on the surface of the groove, depositing a metal layer to cover the surface of the groove; wherein the first P-type well region isolated from the metal layer and the epitaxial layer.

7. The method according to claim 6, wherein, according to said predetermined etching depth, etching the region corresponding to the window, after forming the recess to the surface of the epitaxial layer, further comprising: injecting into said groove second P-type impurity, and drive-in to form the second P type well region located in the first P-type well region and is located below said groove; wherein the first P-type impurity implantation region energy greater than the energy of the second P-type impurity is implanted, the first dose of impurity implanted P-type impurity is less than the second dose of impurity implanted P-type impurities, the second P type well region corresponding includes and is larger than a region corresponding to the recess, the first P-type well region comprises a region corresponding to and larger than the second P type well region corresponding to the region.

8. The method of claim 6 or claim 7, wherein, according to said predetermined etching depth, before etching the region corresponding to said window, further comprising: an N-type impurity implanted to the window, and for drive-in to form P-type in the first well region of the N-type well region, a first P-type well region and larger than a region corresponding to the region comprising the N-type well region corresponding to the N-type well region corresponding to the region including the region and is larger than the corresponding window; preset according to the etching depth, etching the region corresponding to the window, comprises: a depth greater than the N-type well region etch depth, etching the region corresponding to the window, to remove the N-type well region located below the window area, a reserved area in the N-type well region located below the insulating layer; in the the upper surface of the groove, the deposited metal layer to cover the surface of the recess, comprises: a recess on the surface, close to the upper surface and side surface of the recess of the insulating layer , deposited metal layer to cover the surface of the groove, and the insulating layer on the table And side surfaces adjacent to the recess.

9. The method according to previous claim 8, wherein said etching by removing the insulating layer in the preset region, further comprising: forming a polysilicon layer on a surface of the insulating layer; lithography said polysilicon layer to expose the surface of the insulating layer within said region; on the surface of the groove, the deposited metal layer to cover the surface of the recess, comprises: in said recess the upper surface of the groove, an upper surface of said polysilicon layer near the side grooves and the deposited metal layer to cover the surface of the groove, and the upper surface of said polysilicon layer near the recess and side.

10. The method according to claim 8, wherein said N-type impurity is arsenic; the P-type impurity is boron.