JP2022163582A - Semiconductor device and method for manufacturing the same - Google Patents

Abstract

To provide a technology capable of reducing a size of a peripheral region while ensuring a withstand voltage of the peripheral region.SOLUTION: A semiconductor apparatus (10, 100) includes a semiconductor substrate (12), an upper electrode (70), and a lower electrode (72). The semiconductor substrate has an element region (60) and a peripheral region (62) arranged around the element region, when the semiconductor substrate is observed from above. The peripheral region has: an n type drift region (34) exposed on an upper surface of the semiconductor substrate; and a plurality of withstand voltage retention regions (42), each of which is a circle around the element region, exposed on the upper surface of the semiconductor substrate, and separated from each other by a drift region. The plurality of withstand voltage retention regions have a plurality of first withstand voltage retention regions (42a) and a plurality of second withstand voltage retention regions (42b) having a p type impurity concentration lower than that of the plurality of first withstand voltage retention regions. The first withstand voltage retention region and the second withstand voltage retention region are alternately arranged.SELECTED DRAWING: Figure 2

Description

The technology disclosed in this specification relates to a semiconductor device and a manufacturing method thereof.

Patent Document 1 discloses a semiconductor device having a semiconductor substrate, an upper electrode, and a lower electrode. This semiconductor substrate has an element region and a peripheral region. The element region is arranged in the central portion of the semiconductor substrate when viewed from above, and has an element that allows a current to flow between the upper electrode and the lower electrode. The peripheral region is arranged around the element region. The peripheral region has an n-type drift region and a plurality of p-type breakdown voltage holding regions. Each breakdown voltage holding region circles around the element region, is exposed on the upper surface of the semiconductor substrate, and is separated from each other by a drift region.

When the semiconductor device is turned off, a depletion layer spreads in the drift region from the element region toward the peripheral region (that is, from the central portion to the outer peripheral side of the semiconductor substrate). When the depletion layer extending into the peripheral region reaches the innermost breakdown voltage holding region, the depletion layer extends further outward from the breakdown voltage holding region. In this manner, the depletion layer extends to the outer peripheral side while passing through a plurality of breakdown voltage holding regions. Thereby, the breakdown voltage of the semiconductor device is maintained.

JP 2016-92168 A

Each breakdown voltage holding region in Patent Document 1 has the same p-type impurity concentration. Here, if the p-type impurity concentration of the breakdown voltage holding region is increased in order to secure the breakdown voltage of the peripheral region, the width of the depletion layer that spreads over the drift region in the peripheral region becomes large. When the depletion layer reaches the outer peripheral edge of the semiconductor substrate, an electric field is applied to the outer peripheral edge and the breakdown voltage is lowered. In this case, in order to secure a sufficient breakdown voltage, it is necessary to secure a large width of the peripheral region (the distance from the outer edge of the element region to the outer peripheral edge of the semiconductor substrate), which increases the size of the semiconductor device. . On the other hand, if the p-type impurity concentration of the breakdown voltage holding region is lowered, the width of the depletion layer that spreads in the drift region in the peripheral region is reduced, and the breakdown voltage of the peripheral region is lowered. This specification provides a technique capable of reducing the size of the peripheral region while ensuring the breakdown voltage of the peripheral region.

A semiconductor device (10, 100) disclosed in this specification includes a semiconductor substrate (12), an upper electrode (70) in contact with the upper surface of the semiconductor substrate, and a lower electrode (72) in contact with the lower surface of the semiconductor substrate. I have. The semiconductor substrate comprises an element region (60) overlapping a contact surface between the upper electrode and the semiconductor substrate when viewed from above, and a peripheral region (62) disposed around the element region. )have. The element region has an element through which current can flow between the upper electrode and the lower electrode. The peripheral region includes an n-type drift region (34) exposed on the upper surface of the semiconductor substrate, each loops around the element region, is exposed on the upper surface of the semiconductor substrate, and is exposed on the upper surface of the semiconductor substrate. It has a plurality of breakdown voltage holding regions (42) separated from each other by drift regions. The plurality of breakdown voltage holding regions include a plurality of first breakdown voltage holding regions (42a) and a plurality of second breakdown voltage holding regions (42b) having a p-type impurity concentration lower than that of the plurality of first breakdown voltage holding regions. there is The first breakdown voltage holding regions and the second breakdown voltage holding regions are alternately arranged.

In the above semiconductor device, the first breakdown voltage holding regions and the second breakdown voltage holding regions having a lower p-type impurity concentration than the first breakdown voltage holding regions are alternately arranged in the peripheral region. By arranging the second breakdown voltage holding region having a relatively low p-type impurity concentration, the spread of the depletion layer to the drift region in the peripheral region is suppressed as a whole. As a result, the width of the peripheral region can be reduced compared to the conventional art. On the other hand, since the p-type impurity concentration of the first breakdown voltage holding region is relatively high, the breakdown voltage of the peripheral region can be ensured by arranging the first breakdown voltage holding region. Thus, in this semiconductor device, by alternately arranging the first breakdown voltage holding region and the second breakdown voltage holding region, the balance between the spread of the depletion layer in the drift region and the breakdown voltage of the peripheral region is appropriately controlled. be able to. Therefore, in this semiconductor device, the size of the peripheral region can be reduced while ensuring the withstand voltage of the peripheral region.

A method of manufacturing a semiconductor device disclosed in the present specification is a semiconductor substrate having an n-type drift region (34) and a first p-type region (80) disposed on the drift region. By etching, a plurality of annular grooves (84) extending concentrically when the upper surface of the first p-type region is viewed from above are formed so that each of the annular grooves penetrates the first p-type region to form the drift region. forming an n-type region (86) covering the inner surfaces of the plurality of annular grooves by epitaxial growth; and adding more p-type impurities to the inside of the plurality of annular grooves than the first p-type region. forming a lightly doped second p-type region (88) by epitaxial growth.

In this manufacturing method, each of the plurality of annular first p-type regions separated by the annular grooves can function as a breakdown voltage holding region having a high p-type impurity concentration. Each of the type regions can function as a breakdown voltage holding region with a low p-type impurity concentration.

FIG. 2 is a plan view of the semiconductor device of Example 1; Sectional drawing in the II-II line of FIG. FIG. 3 is a diagram showing the potential distribution in the cross section of FIG. 2 when the semiconductor device is off; 4A and 4B are diagrams for explaining a manufacturing process of the semiconductor device of Embodiment 1; FIG. 4A and 4B are diagrams for explaining a manufacturing process of the semiconductor device of Embodiment 1; FIG. 4A and 4B are diagrams for explaining a manufacturing process of the semiconductor device of Embodiment 1; FIG. 4A and 4B are diagrams for explaining a manufacturing process of the semiconductor device of Embodiment 1; FIG. 4A and 4B are diagrams for explaining a manufacturing process of the semiconductor device of Embodiment 1; FIG. FIG. 3 is a cross-sectional view corresponding to FIG. 2 of the semiconductor device of Example 2; 4A to 4C are diagrams for explaining a manufacturing process of a semiconductor device according to a second embodiment; FIG.

The technical elements disclosed in this specification are listed below. Each of the following technical elements is independently useful.

In an example configuration disclosed in this specification, the width of the first breakdown voltage holding region may increase from the upper surface of the semiconductor substrate toward the lower side, and the width of the second breakdown voltage holding region may be: It may become narrower from the upper surface of the semiconductor substrate toward the lower side.

In one configuration disclosed in this specification, the semiconductor substrate may be made of gallium nitride.

In one example of the manufacturing method disclosed in this specification, in the step of forming the plurality of annular grooves, etching is performed so that the width of each of the annular grooves becomes narrower from the upper surface of the semiconductor substrate toward the lower side. may

In the above configuration, the width of the formed annular groove increases toward the upper surface of the semiconductor substrate. Therefore, when the n-type region and the second p-type region are epitaxially grown in the annular groove in the subsequent step, the inner surface of the annular groove can be suitably coated with the n-type region, and the inside of the annular groove can be covered with the second p-type region. It can be preferably filled in the mold area. Therefore, formation of voids inside the second p-type region or the like can be suppressed.

In one example of the manufacturing method disclosed in this specification, the semiconductor substrate may be made of gallium nitride.

Gallium nitride is difficult to form a p-type region by ion implantation. Therefore, the manufacturing method disclosed in this specification is particularly useful when manufacturing a semiconductor device using a semiconductor substrate made of gallium nitride.

(Example 1)
The semiconductor device 10 of Example 1 shown in FIGS. 1 and 2 is a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). The semiconductor device 10 includes a semiconductor substrate 12, electrodes, an insulating layer, and the like. As shown in FIG. 1, the semiconductor substrate 12 has an element region 60 and a peripheral region 62 . The element region 60 is a region that functions as an element (that is, through which a main current flows) and is arranged in the central portion of the semiconductor substrate 12 . The peripheral region 62 is arranged around the element region 60 . The peripheral region 62 is a region between the element region 60 and the outer peripheral edge 12c of the semiconductor substrate 12. As shown in FIG. In FIG. 1, the electrodes and insulating layers on the upper surface 12a of the semiconductor substrate 12 are omitted for the sake of clarity. Also, illustration of the structure in the element region 60 is omitted. Hereinafter, one direction parallel to the upper surface 12a of the semiconductor substrate 12 is called the x direction, the direction parallel to the upper surface 12a and perpendicular to the x direction is called the y direction, and the thickness direction of the semiconductor substrate 12 is called the z direction. The semiconductor substrate 12 is made of GaN (gallium nitride). However, the material of the semiconductor substrate 12 is not particularly limited, and for example, other semiconductor materials such as SiC (silicon carbide) and Si (silicon) may be employed.

As shown in FIG. 2, a gate insulating film 24 and a peripheral insulating film 46 are arranged on the upper surface 12a of the semiconductor substrate 12 . The gate insulating film 24 partially covers the upper surface 12 a of the semiconductor substrate 12 within the element region 60 . The peripheral insulating film 46 covers substantially the entire upper surface 12 a of the semiconductor substrate 12 in the peripheral region 62 and covers a part of the element region 60 to cover the upper surface 12 a of the semiconductor substrate 12 .

An upper electrode 70 is arranged on the upper surface 12 a of the semiconductor substrate 12 . The upper electrode 70 is in contact with part of the upper surface 12 a of the semiconductor substrate 12 within the element region 60 . The upper electrode 70 is in contact with the upper surface 12a of the semiconductor substrate 12 at a portion where the gate insulating film 24 and the peripheral insulating film 46 are not provided. The upper electrode 70 functions as a source electrode. A gate electrode 26 is arranged on the upper surface of the gate insulating film 24 . The gate electrode 26 faces the upper surface 12a of the semiconductor substrate 12 with the gate insulating film 24 interposed therebetween. The gate electrode 26 faces a body region 32 (described later) in a range in contact with the gate insulating film 24 via the gate insulating film 24 . A lower electrode 72 is arranged on the lower surface 12 b of the semiconductor substrate 12 . The lower electrode 72 is formed over substantially the entire lower surface 12 b of the semiconductor substrate 12 . The lower electrode 72 functions as a drain electrode.

As shown in FIG. 2 , in the element region 60 , a plurality of source regions 30 , a plurality of body regions 32 , a JFET region 33 , a drift region 34 and a drain region 35 are provided inside the semiconductor substrate 12 .

Each source region 30 is an n-type region. Each source region 30 is arranged at a position exposed on the upper surface 12 a of the semiconductor substrate 12 . Each source region 30 is in contact across the gate insulating film 24 from the upper electrode 70 . Source region 30 is in ohmic contact with upper electrode 70 .

Each body region 32 is a p-type region. Each body region 32 is arranged around the corresponding source region 30 . Body region 32 is exposed on upper surface 12 a of semiconductor substrate 12 . The body region 32 is in contact with the gate insulating film 24 , the upper electrode 70 and the peripheral insulating film 46 . Body region 32 is in ohmic contact with upper electrode 70 .

JFET region 33 is an n-type region. The JFET region 33 is arranged in a range sandwiched between the two body regions 32 . JFET region 33 is separated from source region 30 by body region 32 . The JFET region 33 is exposed on the upper surface 12 a of the semiconductor substrate 12 . The JFET region 33 is in contact with the gate insulating film 24 .

Drift region 34 is an n-type region. Drift region 34 is located below body region 32 and JFET region 33 . The drift region 34 contacts the body region 32 and the JFET region 33 from below. Drift region 34 is separated from source region 30 by body region 32 . Drift region 34 is also disposed within peripheral region 62, as will be described later. The drift region 34 is arranged across the element region 60 and the peripheral region 62 .

Drain region 35 is an n-type region. Drain region 35 has a higher n-type impurity concentration than drift region 34 . The drain region 35 is arranged below the drift region 34 . Like the drift region 34 , the drain region 35 is arranged across the element region 60 and the peripheral region 62 . The drain region 35 is exposed on the lower surface 12b of the semiconductor substrate 12. As shown in FIG. The drain region 35 is in ohmic contact with the lower electrode 72 .

As shown in FIG. 2 , in the peripheral region 62 , a drift region 34 , a drain region 35 and a plurality of breakdown voltage holding regions 42 are provided inside the semiconductor substrate 12 .

Drift region 34 in peripheral region 62 is exposed to upper surface 12 a of semiconductor substrate 12 . The drift region 34 is in contact with the peripheral insulating film 46 . The structure of the drain region 35 is similar to that of the drain region 35 in the element region 60 .

Each breakdown voltage holding region 42 is a p-type region. As shown in FIG. 1, the breakdown voltage holding regions 42 are arranged concentrically around the device region 60 . Each breakdown voltage holding region 42 is exposed on the upper surface 12 a of the semiconductor substrate 12 . Each breakdown voltage holding region 42 is in contact with a peripheral insulating film 46 . Each breakdown voltage holding region 42 is separated from each other by a drift region 34 . The breakdown voltage holding region 42 has a plurality of first breakdown voltage holding regions 42a and a plurality of second breakdown voltage holding regions 42b. The second breakdown voltage holding region 42b has a p-type impurity concentration lower than that of the first breakdown voltage holding region 42a. The first breakdown voltage holding regions 42a and the second breakdown voltage holding regions 42b are alternately arranged. Each first breakdown voltage holding region 42a is arranged in a range sandwiched between the two second breakdown voltage holding regions 42b, and each second breakdown voltage holding region 42b is arranged in a range sandwiched between the two first breakdown voltage holding regions 42a. are placed in Note that the number of the breakdown voltage holding regions 42 is not particularly limited, and can be appropriately set according to the breakdown voltage to be ensured.

Next, operation of the semiconductor device 10 will be described. When using the semiconductor device 10, the semiconductor device 10, a load (for example, a motor), and a power supply are connected in series. A power supply voltage is applied to the series circuit of the semiconductor device 10 and the load. A power supply voltage is applied such that the lower electrode 72 side has a higher potential than the upper electrode 70 . When an on-potential (potential higher than the gate threshold) is applied to the gate electrode 26, a channel is formed in the body region 32 (the body region 32 located between the source region 30 and the JFET region 33) in contact with the gate insulating film 24. be done. Then, electrons flow from the upper electrode 70 to the lower electrode 72 through the source region 30, the channel, the JFET region 33, the drift region 34, and the drain region 35, thereby turning on the semiconductor device 10. FIG. When the potential of the gate electrode 26 is lowered to the off potential (potential lower than the gate threshold), the channel disappears, the flow of electrons stops, and the semiconductor device 10 is turned off. Thus, the semiconductor device 10 can control the current flowing between the upper electrode 70 and the lower electrode 72 based on the potential of the gate electrode 26 .

When the semiconductor device 10 is turned off, a reverse voltage is applied to the pn junction at the interface between the body region 32 and the drift region 34 and the JFET region 33, so that a depletion layer is formed in the drift region 34 and the JFET region 33 from this pn junction. spread. In the element region 60, a depletion layer spreads from the upper surface 12a of the semiconductor substrate 12 toward the lower surface 12b. Drift region 34 in device region 60 is depleted by a depletion layer extending from body region 32 . Depleted drift region 34 holds the voltage between body region 32 and drain region 35 .

In the peripheral region 62, the depletion layer spreads from the central side of the semiconductor substrate 12 toward the outer peripheral side (that is, from the left side to the right side in FIG. 2). When the depletion layer extending in the peripheral region 62 reaches the innermost breakdown voltage holding region 42 , the depletion layer further extends from the breakdown voltage holding region 42 to the outer circumference side. Thus, each breakdown voltage holding region 42 promotes extension of the depletion layer toward the outer periphery. In the peripheral region 62 , the depletion layer extends to the outer peripheral side while passing through the plurality of breakdown voltage holding regions 42 and extends to the vicinity of the outer peripheral edge 12 c of the semiconductor substrate 12 . When the semiconductor device 10 is turned off, the outer peripheral edge 12c of the semiconductor substrate 12 becomes substantially the same potential as the lower electrode 72. As shown in FIG. Therefore, a potential difference is generated between the body region 32 and the outer peripheral edge 12c. The depleted drift region 34 in the peripheral region 62 maintains the potential difference between the body region 32 and the outer peripheral edge 12c.

As described above, the plurality of breakdown voltage holding regions 42 are composed of the first breakdown voltage holding regions 42a having a relatively high p-type impurity concentration and the second breakdown voltage holding regions 42b having a relatively low p-type impurity concentration. By arranging the second breakdown voltage holding region 42b having a low p-type impurity concentration, the spread of the depletion layer into the drift region 34 in the peripheral region 62 is suppressed as a whole. Therefore, in this embodiment, the width of the peripheral region 62 can be made smaller than in the conventional case by arranging the second breakdown voltage holding region 42b. On the other hand, since the p-type impurity concentration of the first breakdown voltage holding region 42a is high, the breakdown voltage of the peripheral region 62 can be ensured by arranging the first breakdown voltage holding region 42a.

When the depletion layer reaches each breakdown voltage holding region 42 , the depletion layer also spreads inside each breakdown voltage holding region 42 . The first breakdown voltage holding region 42a having a high p-type impurity concentration is hardly depleted. Therefore, almost no potential difference occurs inside each first breakdown voltage holding region 42a. On the other hand, a depletion layer spreads over a wide area inside the second breakdown voltage holding region 42b having a low p-type impurity concentration.

FIG. 3 shows the potential distribution within the semiconductor device 10 when the semiconductor device 10 is off. The dashed lines in FIG. 3 are equipotential lines. As described above, when the semiconductor device 10 is turned off, the drift region 34 in the depleted device region 60 holds the voltage between the body region 32 and the drain region 35 . Therefore, equipotential lines extend laterally in the device region 60 . Further, the drift region 34 in the depleted peripheral region 62 maintains the potential difference between the body region 32 and the outer peripheral edge. Therefore, equipotential lines extend in the vertical direction in the peripheral region 62 . The equipotential lines in the peripheral region 62 are curved and connected to the equipotential lines in the element region 60 .

As described above, the first breakdown voltage holding region 42a having a high p-type impurity concentration is hardly depleted, and no potential difference occurs in the first breakdown voltage holding region 42a. do not enter. On the other hand, since the second breakdown voltage holding region 42b is depleted, equipotential lines are distributed so as to pass through the second breakdown voltage holding region 42b. Thus, even if the second breakdown voltage holding region 42b having a low p-type impurity concentration is arranged, a potential difference occurs in the second breakdown voltage holding region 42b, so that the breakdown voltage of the peripheral region 62 can be ensured.

As described above, in the semiconductor device 10, the width of the peripheral region 62 can be reduced while ensuring the breakdown voltage of the peripheral region 62, as compared with the related art.

Next, a method for manufacturing the semiconductor device 10 will be described. First, as shown in FIG. 4, a semiconductor substrate having an n-type drain region 35, an n-type drift region 34 arranged on the drain region 35, and a first p-type region 80 arranged on the drift region 34 Prepare 12x. For example, the semiconductor substrate 12x can be manufactured by forming the drift region 34 on the surface of the drain region 35 by epitaxial growth and forming the first p-type region 80 on the surface of the drift region 34 by epitaxial growth.

Next, as shown in FIG. 5, a mask having a plurality of openings 63a is formed on the upper surface of the semiconductor substrate 12x. Each opening 63a is formed at a position corresponding to the JFET region 33 in the element region 60 and the second breakdown voltage holding region 42b in the peripheral region 62, respectively. Then, the upper surface of the semiconductor substrate 12x is etched through the mask 63. Next, as shown in FIG. As a result, recesses 82 are formed in the element region 60 to reach the drift region 34 through the first p-type region 80 , and a plurality of recesses 82 are formed in the peripheral region 62 to reach the drift region 34 through the first p-type region 80 . form an annular groove 84 of . Each annular groove 84 is formed in an annular shape extending concentrically when the semiconductor substrate 12x is viewed from above. Each annular groove 84 is formed to have a width wider than that of the second breakdown voltage holding region 42b.

Next, as shown in FIG. 6, an n-type region 86 having an n-type impurity concentration substantially equal to that of the drift region 34 is formed in the recess 82 and the annular groove 84 by epitaxial growth. In the device region 60, an n-type region 86 is grown so as to fill the recess 82. As shown in FIG. On the other hand, within the peripheral region 62 , an n-type region 86 is grown to cover the inner surface of each annular groove 84 . That is, the n-type regions 86 are formed so that the entire inside of each annular groove 84 is not filled. The width of the recess 82 is narrower than the width of each annular groove 84 . Therefore, by epitaxially growing the n-type region 86 , the entire recess 82 is filled with the n-type region 86 earlier than each annular groove 84 .

Next, as shown in FIG. 7, a second p-type region 88 having a p-type impurity concentration lower than that of the first p-type region 80 is formed inside each annular groove 84 by epitaxial growth. Here, a second p-type region 88 is formed so as to fill each annular groove 84 . The process shown in FIG. 7 is performed continuously with the process shown in FIG. 6 by switching the dopant gas during the growth of the n-type region 86 shown in FIG.

Next, as shown in FIG. 8, a CMP (Chemical Mechanical Polishing) technique is used to remove the second p-type region 88 and the n-type region 86 until the first p-type region 80 is exposed. As a result, the body region 32 and the JFET region 33 located in the element region 60, and the first breakdown voltage holding region 42a and the second breakdown voltage holding region 42b located in the peripheral region 62 are formed.

After that, the source region 30 is formed by ion implantation or the like, and the gate insulating film 24, the peripheral insulating film 46, the gate electrode 26, the upper electrode 70, and the lower electrode 72 are formed by a conventionally known method. 2 is completed.

In this manufacturing method, each of the plurality of annular first p-type regions 80 separated by the plurality of annular grooves 84 can function as the first breakdown voltage holding region 42a, and the plurality of annular grooves 84 formed in the plurality of annular grooves 84 can function as the first breakdown voltage holding regions 42a. Each of the second p-type regions 88 can function as the second breakdown voltage holding region 42b. In addition, the first p-type region 80 on the inner peripheral side of the innermost annular groove 84 can function as the body region 32 . Thus, in this manufacturing method, the body region 32 and the first breakdown voltage holding region 42a can be formed from the same first p-type region 80, and the number of manufacturing steps can be reduced.

In this manufacturing method, as shown in FIG. 6, after the inner surface of the annular groove 84 is covered with the n-type region 86, the second p-type region 88 is continuously formed in the annular groove 84 by switching the dopant gas. Form. Therefore, for example, after filling the annular groove 84 with the n-type region 86, a step of forming another annular groove for forming the second p-type region 88 can be omitted. Therefore, the manufacturing man-hours can be reduced, and the semiconductor device 10 can be efficiently manufactured.

Note that it is difficult to form a p-type region by ion implantation in a GaN-based semiconductor (semiconductor whose main material is a compound of gallium and nitrogen). In this manufacturing method, the p-type body region 32 and the breakdown voltage holding region 42 (that is, the first p-type region 80 and the second p-type region 88) are formed by epitaxial growth. Thus, the manufacturing method described above is a technique particularly useful for GaN-based semiconductors, and can suitably manufacture the semiconductor device 10 .

(Example 2)
Next, the semiconductor device 100 of Example 2 will be described. The semiconductor device 100 of the second embodiment differs from that of the first embodiment in the configuration of the breakdown voltage holding region 142 in the peripheral region 62 . Other configurations are the same as those of the first embodiment.

As shown in FIG. 9, in the peripheral region 62 of the semiconductor device 100, the width of the first breakdown voltage holding region 142a increases downward from the upper surface 12a of the semiconductor substrate 12. As shown in FIG. Both side surfaces of the first breakdown voltage holding region 142a are inclined downward from the upper surface 12a of the semiconductor substrate 12 so as to widen with respect to the upper surface 12a of the semiconductor substrate 12 . In addition, the width of the second breakdown voltage holding region 142b becomes narrower from the upper surface 12a of the semiconductor substrate 12 toward the lower side. Both side surfaces of the second breakdown voltage holding region 142b are inclined downward from the upper surface 12a of the semiconductor substrate 12 so as to narrow with respect to the upper surface 12a of the semiconductor substrate 12 .

The semiconductor device 100 of the second embodiment can be manufactured by changing the process shown in FIG. 5 of the first embodiment. In the method of manufacturing the semiconductor device 100, as shown in FIG. 10, when forming the plurality of annular grooves 184, etching is performed so that the width of each annular groove 184 becomes narrower from the upper surface of the semiconductor substrate 12x downward. to implement. After that, the semiconductor device 100 can be manufactured by carrying out the steps after FIG.

In the manufacturing method of the second embodiment, each annular groove 184 is formed such that the width of each annular groove 184 becomes narrower from the upper surface of the semiconductor substrate 12x toward the lower side. Therefore, in the subsequent formation of the n-type region 86 and the formation of the second p-type region 88 , the inside of each annular groove 184 can be suitably covered and filled, and voids are not formed in the n-type region 86 and the second p-type region 88 . occurrence can be suppressed.

Although the MOSFET is formed in the element region 60 in each of the above-described embodiments, the structure of the element formed in the element region 60 is not particularly limited. For example, an IGBT may be formed within the device region 60 . Also, in each of the above-described embodiments, a semiconductor device having a planar gate electrode has been described, but the technique disclosed in this specification may be applied to a semiconductor device having a trench gate electrode, for example.

Although the embodiments have been described in detail above, they are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the techniques exemplified in this specification or drawings simultaneously achieve a plurality of purposes, and achieving one of them has technical utility in itself.

10: Semiconductor device 12: Semiconductor substrate 24: Gate insulating film 26: Gate electrode 30: Source region 32: Body region 33: JFET region 34: Drift region 35: Drain region 42a: First breakdown voltage holding region 42b: Second breakdown voltage holding Region 46: Peripheral insulating film 60: Element region 62: Peripheral region 70: Upper electrode 72: Lower electrode 80: First p-type region 82: Recess 84: Annular groove 86: N-type region 88: Second p-type region

Claims (6)

A semiconductor device (10, 100),
a semiconductor substrate (12);
an upper electrode (70) in contact with the upper surface of the semiconductor substrate;
a lower electrode (72) in contact with the lower surface of the semiconductor substrate;
and
The semiconductor substrate comprises an element region (60) overlapping a contact surface between the upper electrode and the semiconductor substrate when viewed from above, and a peripheral region (62) disposed around the element region. ),
wherein the element region has an element capable of passing a current between the upper electrode and the lower electrode;
The peripheral area is
an n-type drift region (34) exposed on the upper surface of the semiconductor substrate;
a plurality of breakdown voltage holding regions (42) each looping around the device region, exposed to the upper surface of the semiconductor substrate and separated from each other by the drift region;
has
The plurality of breakdown voltage holding regions have a plurality of first breakdown voltage holding regions (42a) and a plurality of second breakdown voltage holding regions (42b) having a p-type impurity concentration lower than that of the plurality of first breakdown voltage holding regions,
The first breakdown voltage holding region and the second breakdown voltage holding region are alternately arranged,
semiconductor device. the width of the first breakdown voltage holding region increases from the top surface of the semiconductor substrate toward the bottom;
2. The semiconductor device according to claim 1, wherein said second breakdown voltage holding region has a width that decreases downward from said upper surface of said semiconductor substrate. 3. The semiconductor device according to claim 1, wherein said semiconductor substrate is made of gallium nitride. A method for manufacturing a semiconductor device,
said top surface of said first p-type region by etching a top surface of said first p-type region of a semiconductor substrate having an n-type drift region (34) and a first p-type region (80) disposed over said drift region; forming a plurality of annular grooves (84) extending concentrically when viewed from above such that each of the annular grooves penetrates the first p-type region and reaches the drift region;
forming an n-type region (86) covering inner surfaces of the plurality of annular grooves by epitaxial growth;
forming a second p-type region (88) having a p-type impurity concentration lower than that of the first p-type region inside the plurality of annular grooves by epitaxial growth;
A manufacturing method comprising: 4. The manufacturing method according to claim 3, wherein in the step of forming the plurality of annular grooves, etching is performed so that the width of each of the annular grooves becomes narrower from the upper surface of the semiconductor substrate toward the lower side. 6. The manufacturing method according to claim 4, wherein said semiconductor substrate is made of gallium nitride.

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