JP2005286328A - Process for manufacturing terminal region of trench mis device, semiconductor die including mis device, and method for forming the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a MIS structure, providing low on-cresistance and threshold voltage and capable of high-frequency operation. <P>SOLUTION: A trench MIS device is formed in a semiconductor die, including a P-epitaxial layer overlying an N+ substrate and an N-epitaxial layer. The device includes a drain-drift region extending from the bottom of the trench to the N-epitaxial layer. The terminal region of the die includes a half trench at the edge portion of the die and an N-type region, extending from the bottom of the half trench to the substrate. An insulating layer and a metal layer, overlying it, extend from the surface of the epitaxial layer to the inside of the half trench. Preferably, the elements in the terminal region are formed in the same process step as that used to form active elements of the device. The device is terminated by a terminal trench filled, with a plurality of polysilicons located in the vicinity of the edge of the die and the polysilicon in each terminal trench is connected to a mesa adjacent to the terminal trench. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a trench gate type power MOSFET excellent in on-resistance and breakdown voltage characteristics, and more particularly to a trench MOSFET suitable for high-frequency operation. The present invention also relates to a manufacturing process of such a MOSFET.

  Some metal insulator semiconductor (MIS) devices include a gate in a trench extending downwardly from the surface of a semiconductor substrate (eg, silicon). In such a device, the current flows mainly in the vertical direction, so that the cells can be arranged more densely. This leads to an increase in device current mobility and a decrease in on-resistance if all other conditions are the same. Devices included in the general category of MIS devices include metal oxide semiconductor field effect transistors (MOSFETs), insulated bipolar transistors (IGBTs), MOS gate thyristors, and the like.

For example, a trench MOSFET can be formed with high transconductance (g _{m, max} ) and low specific on-resistance (R _on ), which is important for optical linear signal amplification and switching. However, one of the most important issues for high frequency operation is a reduction in the internal capacitance of the MOSFET. The internal capacitance includes a gate-drain capacitance (C _gd ) (also referred to as feedback capacitance (C _rss )), input capacitance (C _iss ), and output capacitance (C _oss ).
US Application No. 09 / 591,179 US Application No. 09 / 927,320 US Patent No. 5,072,266

FIG. 1 is a cross-sectional view of a conventional n-type trench MOSFET 10. In MOSFET 10, an n-type epitaxial (“N-epi”) layer 14 is grown on an N ⁺ substrate 12. The N-epi layer 14 may be a lightly doped layer, ie, an N ⁻ layer. The p-type body region 16 separates the N-epi layer 14 and the N ⁺ source region 18. Current flows vertically through the channel (shown in broken lines) along the sidewalls of the trench 20. The sidewalls and bottom of trench 20 are lined with a thin gate insulator 22 (eg, silicon dioxide). The trench 20 is filled with a conductive material such as doped polysilicon, which forms the gate 24. The trench 20 including the gate 24 is covered with an insulating layer 26, which may be boron phosphosilica glass (BPSG). A conductor 28 is electrically connected to the source region 18 and the body region 16, and the conductor 28 is usually a metal or a metal alloy. The body contact region 30 facilitates ohmic contact between the metal 28 and the P body 16. The gate 24 is connected in the depth direction outside the plane of FIG.

A very disadvantage of MOSFET 10 is that the area where gate 24 and N-epi layer 14 overlap is large, and a portion of thin gate insulator 22 is exposed to the operating voltage of the drain. When the overlapping portion is large in this manner, the rated voltage of the drain of the MOSFET 10 is limited, causing a problem in the long-term reliability of the thin gate insulator 22, and the gate-drain capacitance C _{gd of the} MOSFET 10 is greatly increased. In the trench structure, C _gd is larger than in conventional lateral devices, which limits the switching speed of MOSFET 10 and therefore its use in high frequency applications.

One way that this disadvantage can be addressed is described in US application Ser. No. 09 / 591,179, which is illustrated in FIG. FIG. 2 is a cross-sectional view of a trench MOSFET 40 having an undoped polysilicon plug 42 near the bottom of the trench 20. MOSFET 40 is similar to MOSFET 10 of FIG. 1 except that it includes a polysilicon plug 42. Polysilicon plug 42 is separated from the bottom of trench 20 by oxide layer 22 and from gate 24 by oxide layer 44. The sandwich structure of oxide layer 22, polysilicon plug 42 and oxide layer 44 increases the distance between gate 24 and N-epi layer 14 and thus reduces C _gd .

However, in some situations, it may be preferable to have a better insulator material than non-doped polysilicon at the bottom of trench 19 for the purpose of minimizing C _gd for high frequency applications.

One way that this problem can be addressed is described in US application Ser. No. 09 / 927,320, which is illustrated in FIG. FIG. 3 is a cross-sectional view of a trench MOSFET 50 having a thick oxide layer 52 near the bottom of the trench 20. A thick oxide layer 52 separates the gate 24 and the N-epi layer 14. Thereby, the problem which arises when only the thin gate insulator 15 separates the gate 24 and the N-epi layer 14 (drain) as shown in FIG. 1 can be avoided. The thick oxide layer 52 is a more effective insulator than the polysilicon plug 42 shown in FIG. 2, so that the gate-drain capacitance C _{gd of the} MOSFET 50 is smaller than that of the MOSFET 40 of FIG. Reduced.

However, the solution of FIG. 3 still has a thin gate oxide region 54 between the body region 16 and the thick oxide layer 52. This is because the lower junction of the body region 16 and the upper end of the thick oxide layer 52 are not self-aligned. If body region 16 extends downward beyond the top of thick oxide layer 52, MOSFET 50 may have a high on-resistance R _on and a high threshold voltage. However, since this alignment is difficult to control during manufacturing, a significant error margin must be allowed to prevent overlap between the body region 16 and the thick oxide layer 52, which is a thin gate oxide region. This may result in a large overlap between the gate and drain at 54. The thin gate region 54 exists between the body region 16 and the polysilicon plug 42 in the MOSFET 40 of FIG. Thus, C _gd can still be a problem for high frequency applications. Accordingly, there is a need for a trench MOSFET with reduced gate-drain capacitance C _gd and improved high frequency performance.

  Another problem with trench MIS devices relates to the strength of the electric field at the corners of the trench, for example represented by the corners 56 shown in FIG. The field strength is greatest at the corners of the trench, so this is usually where avalanche breakdown occurs. Avalanche breakdown usually leads to the generation of hot carriers, and if breakdown occurs near the gate oxide layer, hot carriers can be injected into the gate oxide layer. This can damage or break the gate oxide layer and can cause long-term reliability issues for the device. Yield preferably occurs in the bulk silicon away from the gate oxide layer.

One technique for reducing the field strength at the corners of the trench and causing breakdown in bulk silicon away from the trench is taught in US Pat. No. 5,072,266. This technique is illustrated in FIG. 4, which shows a MOSFET 60. MOSFET 60 is similar to MOSFET 10 of FIG. 1 except that deep P ⁺ diffusion 62 extends downward from P body 16 to a level below the bottom of trench 20. The deep P ⁺ diffusion 62 has the effect of shaping the electric field to reduce the electric field strength at the corner 56 of the trench.

The technique of US Pat. No. 5,072,266 improves the breakdown voltage performance of the MOSFET, but sets the lower limit of the cell pitch indicated by “d” in FIG. This is because if the cell pitch becomes too small, the dopant from the deep P ⁺ diffusion portion enters the channel region of the MOSFET and raises its threshold voltage. Reducing the cell pitch increases the total perimeter of the MOSFET cell and provides a larger gate width for the current, thereby reducing the on-resistance of the MOSFET. Therefore, if the technology of the Bulucea patent is used to improve the breakdown voltage characteristics of the MOSFET, it is actually more difficult to reduce the on-resistance of the MOSFET.

  In summary, there is a clear need for a MIS structure that provides low on-resistance and threshold voltage, yet is capable of high frequency operation.

  In a MIS device according to the present invention, a first conductivity type substrate is covered by a second conductivity type epitaxial ("epi") layer. The trench is formed in the epitaxial layer and the gate is disposed in the trench and separated from the epitaxial layer by an oxide or other insulating layer.

In order to minimize the gate-drain capacitance C _gd , a thick insulating layer, preferably an oxide, is formed at the bottom of the trench. The trench is lined with a relatively thick layer of nitride, for example, and the nitride layer is subjected to a directional etch to remove the nitride layer from the bottom of the trench. At this point, a dopant of the first conductivity type is implanted through the bottom of the trench to form a drain drift region that extends from the bottom of the trench to the substrate.

  A thick insulating layer can be formed in several ways. An oxide or other insulating layer can be deposited, for example, by chemical vapor deposition (CVD), and the thick insulating layer can be etched back until only a “plug” remains at the bottom of the trench. The oxide layer may be formed by thermal oxidation at the bottom of the trench. The deposition process can be performed in such a way that the deposited material (eg, oxide) is selectively deposited on the silicon at the bottom of the trench rather than the material (eg, nitride) that covers the inside of the trench sidewalls. .

  After the thick insulating layer is formed at the bottom of the trench, the material covering the inside of the trench sidewall is removed. A relatively thin gate oxide layer is formed on the sidewalls of the trench and the trench is filled with a conductive gate material such as doped polysilicon. Threshold adjustment or body implantation may be performed, after which a source region of the first conductivity type is formed on the surface of the epitaxial layer.

The drain drift region can be formed in several ways. A dopant of the second conductivity type may be implanted through the bottom of the trench with a dose and energy that extends without diffusion from the bottom of the trench to the substrate. Alternatively, the second conductivity type dopant may be implanted at a lower energy through the bottom of the trench, initially forming a region of the second conductivity type immediately below the bottom of the trench. . By exposing the structure to a high temperature for a predetermined time, the dopant can be diffused downward toward the substrate. Alternatively, a layer of the second conductivity type can be implanted at or near the interface between the epitaxial layer and the substrate, after which the dopant can be diffused upward toward the bottom of the trench. The above processes may be combined. That is, a region of the second conductivity type is formed immediately below the bottom of the trench, a layer of the second conductivity type is injected at or near the interface between the epitaxial layer and the substrate, and the structure is heated. It is also possible to bond the region and the layer. A series of implants may be performed to form a drain drift region that includes a “stack” of second conductivity type regions between the trench bottom and the substrate.

  The resulting MIS device as a result of such a process has a thick oxide or other insulating layer at the bottom of the trench and a drain drift region extending from the bottom of the trench to the substrate. The drain drift region junction is preferably self-aligned with the edge of the thick insulating layer. Thereby, the gate-drain capacitance can be minimized without impairing the threshold voltage or on-resistance of the device. In the middle of the MOSFET cell, the P-epi layer extends below the level at the bottom of the trench to ensure that breakdown occurs away from the gate oxide layer. However, there is no deep implantation as taught in US Pat. No. 5,072,266, and therefore the cell pitch is reduced to the threshold voltage of the device as the second conductivity type dopant enters the channel region. It can be set without the risk of adverse effects.

  In order to increase the breakdown voltage (breakdown voltage) of the device, a low-concentration epitaxial layer of the first conductivity type may be formed on the substrate.

  According to one aspect of the invention, the edge termination region is fabricated using substantially the same process steps used to create the trench and drain drift region.

  According to another aspect of the present invention, the termination region of the MIS device includes a plurality of termination trenches and a first conductivity type region extending from the bottom of each termination trench to the substrate. Each termination trench includes a conductive material, and a metal layer connects the polysilicon in each termination trench to a contact area on the mesa adjacent to the trench.

  FIG. 5A shows an exemplary MIS device 70 according to the present invention. The MIS device 70 is a MOSFET, but it can also be another type of MIS device, such as an insulated bipolar transistor (IGBT) or a MOS gate thyristor.

The MIS device 70 is formed in an epitaxial (“epi”) layer 102. This layer is typically doped with P-type impurities and overlies the N ⁺ substrate 100. The N ⁺ substrate 100 forms the drain of the device, which can have a resistivity of, for example, 5 × 10 ⁻⁴ Ω · cm to 5 × 10 ⁻³ Ω · cm. The P-epi layer 102 may be doped with boron to a concentration of 1 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁷ cm ⁻³ . N ⁺ substrate 100 is typically about 200 microns thick and epi layer 102 can be 2 to 5 microns thick.

A trench 110 is formed in the P-epi layer 102. The inside of the trench 110 is covered with a gate oxide layer 170 and filled with polysilicon that functions as the gate 174. N ⁺ source region 178 and P ⁺ body contact region 180 are formed on the surface of P-epi layer 102. The remaining portion of the P-epi layer 102 forms a P-type base or body 103. Body 103 forms a junction with the N ⁺ substrate 100, which surface substantially coincident with the P-epi layer 102 and the N ⁺ substrate 100.

Metal layer 184 is electrically connected to N ⁺ source region 178 and P ⁺ body contact region 180. A boron phosphosilica glass (BPSG) layer 182 insulates the gate 174 from the metal layer 184. The gate 174 is electrically connected in the depth direction outside the drawing sheet.

In accordance with the present invention, the drain of device 70 includes (a) an N-type drain / drift region 116 extending between the bottom of trench 110 and N ⁺ substrate 100, and (b) a drain / drift region in trench 110. And a thick bottom oxide region 150 formed adjacent to 116. The junction 105 between the N drain / drift region 116 and the P body 103 extends between the N ⁺ substrate 100 and the trench 110. The N drain / drift region 116 may be doped with phosphorus at a concentration of, for example, 5 × 10 ¹⁵ cm ⁻³ to 5 × 10 ¹⁷ cm ⁻³ .

FIG. 7A is a graph of the doping concentration in the MOSFET 70. This graph is created by the computer simulation program SUPREME, and is taken in a longitudinal section through the channel region, indicated by II in FIG. The curve shown shows the arsenic and boron doping concentrations, and the third curve shows the net doping concentration. FIG. 7B is a similar graph taken in a longitudinal section across the bottom of the trench indicated by II-II in FIG. The horizontal axis in FIG. 7A shows the distance below the surface of the P-epi layer in microns, and the horizontal axis in FIG. 7B shows the distance below the bottom of the trench in microns. The vertical axis in FIG. 7A and the vertical axis in FIG. 7B indicate the common logarithm of the doping concentration in units of atoms / cm ³ . In FIG. 7A, the concentration of boron, which is the base dopant of the P-epi layer 102, is relatively flat and dominant in the channel region. The arsenic doping concentration increases with the transition from the channel region to the source or drain.

  8A and 8B are graphs showing the doping concentration in the same area as FIGS. 7A and 7B, respectively. However, FIGS. 8A and 8B were created using the computer simulation program MEDICI and show only N-type or P-type net doping concentrations.

  The SUPREME simulation and the MEDICI simulation are based on the fact that SUPREME only considers the doping concentration in a single longitudinal section and does not consider the effect of dopants in other laterally offset positions. The difference is that it takes into account all the dopants in the plane of the dimension.

Advantages of MOSFET 70 include:
1. Avalanche breakdown generally occurs at the interface between the N ⁺ substrate 100 and the P-epi layer 102 away from the trench (eg, the location indicated by 72 in FIG. 5A). Accordingly, damage to the gate oxide layer 170 due to hot carriers generated in the area where breakdown occurs can be prevented.

  2. Breakage of the gate oxide 170 at the corners of the trench where the electric field is maximized is prevented.

3. For a given threshold voltage, a higher punch-through breakdown voltage is obtained. The junction 105 between the N drain / drift region 116 and the P body 103 extends downward to the N ⁺ substrate 100. As shown in FIG. 5B, when a reverse bias is applied to the PN junction 105 as in the case where the MOSFET 70 is in an OFF state and blocking current, depletion regions indicated by broken lines 105A and 105B are generated. It extends along the entire length of the junction 105, so that the depletion region in the channel area does not expand so quickly towards the source region. The extension of the depletion region toward the source region is a condition that causes punch-through breakdown.

4). Also, a higher punch through breakdown voltage is obtained for a given threshold voltage. As shown in FIG. 9A, in a conventional MOSFET having a diffusion body, the dopant concentration of the body rapidly decreases as it approaches N-epi (drift region). The threshold voltage is determined by the peak doping concentration N _{A peak} . The punch-through breakdown voltage is determined by the total charge amount Q _channel in the channel region (represented by the area below the P body curve in FIG. 9A). In the MOSFET of the present invention, as shown in FIG. 9B, the doping profile of the P body region is relatively flat. Thus, even if the total charge in the channel increases, N _{A peak} can be the same, thus providing a higher punch-through breakdown voltage.

  5). Since there is no deep body diffusion (as taught in US Pat. No. 5,072,266) in each cell, additional P-type dopants enter the channel region to increase the MOSFET threshold voltage. The cell pitch can be reduced without fear. Thus, the cell packing density can be increased and the on-resistance of the device is reduced.

  6). In conventional trench MOSFETs, a lightly doped “drift region” is often formed between the channel and the heavily doped substrate. The doping concentration of the drift region must be kept below a certain level. Otherwise, effective depletion cannot be obtained and the strength of the electric field at the corner of the trench becomes too large. However, keeping the drift region doping concentration low increases the on-resistance of the device. In contrast, the N drain / drift region 116 of the present invention can be more highly doped. This is because the shape of the N drain / drift region 116 and the length of the junction 105 between the N drain / drift region 116 and the P body region 103 cause more effective depletion. The more heavily doped N drain drift region 116 reduces the on-resistance of the device.

7). As shown in FIG. 19A, it is not necessary to provide a separate P-type diffusion portion in the termination region of the MOSFET. This is because the P-epi layer 102 extends to the N ⁺ substrate 100 except where the N drain / drift region 116 is located. FIG. 19B shows a termination region of a conventional MOSFET, which includes a P-type diffusion portion 75. By eliminating the P-type termination spreader or field ring, the number of masking steps is reduced. For example, in the process described here, only five masking steps are required.

Formation of Drain / Drift Region FIGS. 12A-12N are cross-sectional views illustrating one embodiment of a process for fabricating a trench MOSFET, such as MOSFET 70 of FIG. 5A, in accordance with the present invention. As shown in FIG. 12A, the process begins by growing a lightly doped P-epi layer 102 (typically about 6-8 μm thick) on a heavily doped N ⁺ substrate 100. A pad oxide 104 (e.g., 100-200 mm thick) is grown on the P-epi layer 102 by dry thermal oxidation at 950 ° C. for 10 minutes. As shown in FIG. 12B, a nitride layer 106 (eg, 200-300 mm thick) is deposited on the pad oxide 104 by chemical vapor deposition (CVD). Using a normal photolithography process and a first (trench) mask, nitride layer 106 and pad oxide 104 are patterned to form openings 108 in which the trenches are to be placed. As shown in FIG. 12C, trench 110 is etched through opening 108 using a dry plasma etch such as reactive ion etching (RIE). The trench 110 may be about 0.5-1.2 μm wide and about 1-2 μm deep.

Second pad oxide 112 (e.g., 100-200cm) is grown by thermal oxidation on the sidewalls and bottom of trench 110, as shown in FIG. 12D. A thick nitride layer 114 (eg, 1000-2000 cm) is conformally deposited by CVD on the sidewalls and bottom of the trench 110 and on the nitride layer 106, as shown in FIG. 12E. The nitride layer 114 is etched by directional dry plasma etching such as RIE, using an etchant having a higher selectivity for the nitride layer 114 than the oxide. By this nitride etching, as shown in FIG. 12F, the spacer 115 of the nitride layer 114 remains along the sidewall of the trench 110, and the pad oxide 112 is exposed at the bottom center of the trench 110. The nitride layer 114 may be over-etched to such an extent that the nitride layer 106 is removed from above the pad oxide 104.

With the sidewall spacers 115 left in place, N-type dopant is implanted through the pad oxide 112 at the bottom of the trench 110 to form an N drain drift region 116 (FIG. 12G). For example, phosphorus can be implanted with an energy of 300 keV to 3.0 MeV at a dose of 1 × 10 ¹³ cm ⁻² to 1 × 10 ¹⁴ cm ⁻² . In order to prevent significant diffusion of phosphorus and consequent expansion of the N drain / drift region 116, is the amount of heat applied to the above structure (FIG. 12G) post-process limited to about 950 ° C. for 60 minutes? Alternatively, the structure described above (FIG. 12G) may be subjected to a rapid thermal anneal (RTA) at 1050 ° C. for 90 seconds. In either case, the N drain / drift region 116 maintains the substantially small shape shown in FIG. 12G. Advantageously, in the cross-sectional view of FIG. 12G, at least 75%, preferably 90% of the N drain drift region 116 is located directly below the trench 110.

  Instead, the N drain / drift region 116 implants phosphorous at a lower energy of 30 keV to 300 keV (typically 150 keV) to form an N-type region 118 immediately below the trench (FIG. 12H), after which It can also be formed by diffusing phosphorus by heating at 1050 ° C. to 1150 ° C. for 10 to 120 minutes (typically 90 minutes at 1100 ° C.), in which case the N-type region 118 is downward and Extending laterally, a drain / drift region 120 shaped as shown in FIG. 12I is formed.

In another variation of the process, a deep layer 122 (eg, phosphorus) is implanted at a relatively high energy at a location below the trench, as shown in FIG. 12J, and then heated until the phosphorus reaches the bottom of the trench. A drain drift region 124 as shown in FIG. 12K is obtained by diffusing phosphorus upward using a process. This is distinct from the process described above in connection with FIG. 12G where the N-type dopant extends from the bottom of the trench 110 to the interface between the N ⁺ substrate and the P-epi layer after implantation, and is also related to FIG. This is also distinguished from the process described above in which the post-implant dopant is located directly below the bottom of the trench. When implanting N-type dopants at a relatively high energy to form the deep layer 122, by changing the depth of the trench, the thickness of the P-epi layer 102, and the implantation energy, the layer 122 becomes an N ⁺ substrate. Above the interface between 100 and P-epi layer 102 (eg, when P-epi layer 102 is thick and / or trench depth is small), or within N ⁺ substrate 100 (eg, P-epi layer 102 is thin and / or Or if the trench depth is large).

FIG. 11 shows a schematic shape of a doping profile in a longitudinal section starting from the trench bottom when the drain / drift region is formed by diffusing a deeply implanted layer upward. As shown in FIG. 11, the concentration of the N-type dopant in the drain / drift region increases monotonously as it goes below the bottom of the trench. This is distinct from the doping profile below the trench in a MOSFET formed using a low energy process, as shown in FIG. 8B, where the doping concentration first decreases and then increases in the vicinity of the N ⁺ substrate.

  Using the process shown in FIGS. 12J and 12K provides an N drain drift region that is substantially confined to the region directly under the trench and allows for a smaller cell pitch. This process is easier to control and increases throughput.

Alternatively, a combination of upward and downward diffusion can be used to form the drain drift region. As shown in FIG. 12L, the deep N layer 12
2 (eg, phosphorus) is formed at the interface between the N ⁺ substrate 100 and the P-epi layer 102 by a high energy implantation process. As described above in connection with FIG. 12H, N-type dopant is implanted through the bottom of the trench to form an N ⁺ region 118 below the trench. The structure is then heated, for example from 900 ° C. to 1100 ° C. The deep N layer 122 is diffused upward and the N region 118 is diffused downward until they combine to form an N-type drain / drift region 126 as shown in FIG. 12M.

  Yet another alternative is to form a stack of overlapping implant regions 128, as shown in FIG. 12N, by performing N implants three or more times sequentially with increasing energy to form a drain drift region. It is. The stack 128 includes four implantation regions 128A to 128D, but the stack may be formed by performing implantation less than this number or five times or more. The stack can be formed substantially without diffusion (i.e., without heating), or by heating, the dopant can be diffused to increase the amount of overlap between regions 128A-128D. .

Optionally, a heavily doped N ⁺ region in the drain drift region 116, as shown in FIG. 12O, for the purpose of increasing current spreading in the drain drift region and further reducing the on-resistance of the device. It is also possible to inject 130.

At high or low energy, at the completion of the process, an N drain drift region extends from the N ⁺ substrate to the trench bottom. In many cases, the junction between the N drain / drift region and the P-epi layer extends from the substrate to the sidewall of the trench. If a low energy implantation process is used and the dopant is subsequently diffused by heat, the junction between the drain drift region and the P-epi layer will have a convex arc shape towards the outside of the drain drift region. (FIG. 12I).

  Any of the above methods can be used to form the drain drift region. Hereinafter, a method for forming a thick bottom insulating layer will be described. Here, the implantation process shown in FIG. 12G is used. However, it should be understood that any of the alternative methods can be used.

Thick Bottom Oxide Formation As shown in FIG. 13A, the process begins with the deposition of a thick insulating layer 150, eg, 2-4 μm thick. This deposition method is non-conformal, thereby filling the trench 110 and causing an overflow on the upper surface of the P-epi layer 102. The thick insulating layer 150 can be, for example, low temperature oxide (LTO), chemical vapor deposition (CVD) oxide, phosphosilica glass (PSG), boron phosphosilica glass (BPSG), or another insulating material. In the following description, it is assumed that the insulating layer 150 is a CVD oxide layer.

  Typically, the oxide layer 150 is etched back into the trench 110 by performing a wet etch using an etchant that has a higher selectivity for oxide than nitride. The oxide layer 150 is etched until only about 0.1-0.2 μm remains in the trench 110, as shown in FIG. 13B, to form a thick bottom oxide layer 151.

Nitride layer 106 and spacer 115 are typically removed by performing a wet etch using an etchant that has a higher selectivity for nitride than oxide. Thereafter, the exposed portions of the pad oxide 104 and the pad oxide 112 are removed by general wet etching. By this wet etching, a thick oxide layer 151 is formed.
A small part of it is removed, but that part is less important. The resulting structure with the thick oxide layer 151 remaining at the bottom of the trench 110 is shown in FIG. 13C.

  In another variant according to the invention, a gentle transition is formed between the thick and thin sections of the gate oxide layer.

  The process may be similar to the process described above through the steps shown in FIG. 12F, in which case the nitride etch leaves a sidewall spacer 115 along the sidewall of the trench 110, and the center bottom of the trench 110. The pad oxide 112 is exposed in the region. However, in the next step, instead of depositing a thick insulating layer, a thick oxide layer is grown by a thermal process. When this is done, the thermal oxide consumes a portion of the silicon and undercuts the edge portion of the sidewall spacer 115, so that the nitride is removed from the surface of the trench (lift-off). This forms a structure similar to a “bird's beak” in a conventional LOCOS (local oxidation of silicon) process often used to create field oxide regions on the top surface of a semiconductor device.

  FIG. 14 shows the structure after the thermal oxide layer 158 has grown at the bottom of the trench 110. This structure is shown in detail in FIG. The edge portion of the thermal oxide layer 158 presses the lower side of the sidewall spacer 115 and as a result is inclined or tapered.

  By changing the thickness of the sidewall spacer, the edge portion of the oxide layer can be positioned at a different location. FIG. 15A shows a relatively thick sidewall spacer 115, with the result that the edge of the oxide layer 158 is located at the bottom of the trench 110. FIG. 15B shows a thinner sidewall spacer 115A where the edge of the oxide layer 158A is substantially located at the corner of the trench 110. FIG. FIG. 15C shows a thinner sidewall spacer 115B, where the edge of the oxide layer 158B is located on the sidewall of the trench 110. FIG.

  Similarly, the edge of the oxide layer can be positioned at various intermediate points by changing the thickness of the sidewall spacer. The thickness of the side wall spacer is independent of the width and depth of the trench. For example, when the side wall spacer is in the range of 1,500 to 2,000 mm thick, the edge of the oxide layer is most likely located at the bottom of the trench (FIG. 15A). If the sidewall spacer is less than 500 mm thick, the edge of the oxide layer will usually be located on the sidewall of the trench (FIG. 15C).

  The oxide layer can be grown, for example, by heating the silicon structure at a temperature of 1,000 ° C. to 1200 ° C. for 20 minutes to 1 hour.

  Yet another method of forming a thick bottom oxide is shown in FIGS. 16A and 16B. As shown in FIGS. 12A-12G and described above, the oxide layer 160 is deposited after the drain / drift region 116 and the sidewall spacer 115 are formed, but this time the trench 110 is not on the sidewall spacer 115. A process is used that allows selective deposition on the silicon exposed at the bottom of the substrate. A process that can be used is a subatmospheric chemical vapor deposition (SACVD) process that uses ozone to cause a chemical reaction. During this reaction, ozone readily dissociates and releases atomic oxygen, which combines with a precursor such as TEOS to form silicon dioxide. This structure may then be annealed.

  Table 1 shows exemplary process parameters for the ozone activated TEOS SACVD formation of the thick insulating layer 21.

  The spacer 115 may include a material other than nitride. The material used for the spacer is chosen so that silicon dioxide is selectively deposited on the silicon over the spacer. The choice of material for the spacer depends on the oxide deposition process used. Table 2 shows the deposition selectivity of several materials during ozone activated TEOS SACVD.

As shown in Table 2, during ozone activated TEOS SACVD, silicon dioxide deposits on silicon at a rate five times that on nitride. Thus, during the fabrication of devices using nitride sidewall spacers 115, the silicon dioxide deposited at the bottom of trench 110 is about five times thicker than the silicon dioxide deposited on nitride sidewall spacers 115. Become. Actually, when a 3000-nm oxide film was grown on the silicon surface, no oxide growth was observed on the nitride surface. Such deposition selectivity is probably due to the low surface energy of silicon nitride compared to silicon. As shown in Table 2, silicon dioxide grown by thermal oxidation, or silicon dioxide deposited by TEOS PECVD, was also used when the deposition of layer 160 was using ozone activated TEOS SACVD. It can be a suitable material. This is because silicon dioxide is selectively deposited on silicon rather than these materials. Silicon dioxide deposited by SiH ₄ PECVD or BPSG deposited by PECVD may not be a suitable spacer material for ozone activated TEOS SACVD. This is because silicon dioxide does not select silicon for these materials. If a deposition process other than TEOS SACVD activated with ozone is used, materials other than those shown in Table 2 may be used for the sidewall spacers.

After the oxide layer 160 is deposited, a buffered oxide etch is used to remove the oxide deposited on the surface of the nitride sidewall spacer 115 and a wet nitride etch is used to remove the nitride sidewalls. The spacer 115 and the nitride layer 106 are removed. To ensure that all nitride is removed, another anneal may be performed, for example, at 1000 ° C. for 5-10 minutes to oxidize the remaining nitride, and an oxide etch may be performed after this anneal. You may do it. The oxide etch removes the oxidized nitride (oxynitride) but does not remove a large portion of the oxide layer 160.

  The pad oxides 104, 112 are also removed, but this is usually done by wet etching. This wet etch removes a minor portion of the oxide layer 160 that is not critical. The resulting structure is shown in FIG. Here, a portion of the oxide layer 160 remains at the bottom of the trench 110.

After the thick bottom oxide is formed by one of the above processes, a sacrificial oxide layer (not shown) can be grown on the sidewalls of the trench and then removed. This helps to remove crystal damage that occurred during trench etching. The sacrificial oxide layer can be about 500 mm thick and can be grown, for example, by dry thermal oxidation at 1050 ° C. for 20 minutes and removed by wet etching. The sacrificial gate oxide wet etch is performed in a short time to minimize the oxide layer etch at the bottom of the trench.

  Next, as shown in FIG. 17A, a gate oxide layer 170 or other insulating layer (eg, about 300-1000 mm thick) is formed on the sidewalls of the trench 110 and on the top surface of the P-epi layer 102. For example, the gate oxide layer 170 can be grown using dry thermal oxidation at 1050 ° C. for 20 minutes.

As shown in FIG. 17B, a layer of polysilicon or other conductive material 172 is deposited (eg, by a low pressure CVD (LPCVD) process) that fills the trench 110 and overflows the horizontal surface of the oxide layer 170. Arise. Polysilicon layer 172 can be, for example, pre-doped polysilicon, non-doped polysilicon layer subsequently implanted and annealed, or an alternative conductive material. The polysilicon layer 172 is etched, typically using reactive ion etching, until the top surface of the polysilicon layer 172 is at approximately the same level as the top of the P-epi layer 102, and the gate as shown in FIG. 17C. 174 is formed. In the N-type MOSFET, the gate 174 can be, for example, a polysilicon layer doped with phosphorus at a concentration of 1 × 10 ¹⁹ cm ⁻³ . In some embodiments, the polysilicon layer 172 may be etched beyond the top of the trench 110 to dent the gate 174 to minimize gate-source overlap capacitance. An oxide or other insulating layer may be formed on the upper surface of the substrate. In many cases, the polysilicon layer 172 is etched through an opening in the second (gate poly) mask, which means that a portion of the polysilicon layer 172 is part of the gate metal portion of the metal layer 184. It remains in the position where it is connected by (FIG. 17I).

Optionally, when the threshold voltage is adjusted, threshold adjustment implantation can be performed, for example, by implanting boron through the surface of the P-epi layer 102. Boron can be implanted with an energy of 150 keV at a dose of 5 × 10 ¹² cm ⁻² . As a result, the concentration of the P-type dopant is 1 in the portion of the P-epi layer 102 that forms the channel of the MOSFET. × 10 ¹⁷ atoms / cm ³ As described above, FIG. 10A shows a dopant profile in a longitudinal section cut by a line passing through a channel, and shows a threshold adjustment implant. As shown, the threshold adjustment implant is typically located in the area of the channel directly below the source region. The threshold voltage of the MOSFET is determined by the peak doping concentration N _{A peak} of the threshold adjustment implant. This step can be omitted if the threshold voltage of the device does not need to be adjusted.

If necessary, a body region 176 as shown in FIG. 17D can be formed by implanting a P-type dopant such as boron. A typical body implantation doping profile is shown in the graph of FIG. The body implant is somewhat similar to the threshold adjust implant, but uses higher energy and, as a result, the body implant is due to the junction between the P-epi layer and the N drain drift region. Extends to a near level. The threshold voltage of the MOSFET is determined by the peak doping concentration N _{A peak} of the body implant. Instead, the P body implant is implanted at a level lower than the bottom of the trench 110 but higher than the interface between the P-epi layer 102 and the N ⁺ substrate 100 as shown by the body region 186 in FIG. 17E. May be.

Next, the upper surface of the P-epi layer 102 is masked with a third (source) mask and an N-type dopant such as phosphorus is implanted to form the N ⁺ source region 178 shown in FIG. 17F. The source mask 190 is removed. A BPSG layer 182 is deposited on the top surface of the device, and a fourth (contact) mask 183 is deposited and etched on the surface of the BPSG layer 182. This is shown in FIG. 17G. The BPSG layer 182 is etched through the opening in the contact mask 183 and P-type dopant is implanted through the resulting opening of the BPSG layer 182 to form the P ⁺ body contact region 180. This is shown in FIG. 17H. For example, arsenic can be implanted into the N ⁺ source region 178 with an energy of 80 keV at a dose of 5 × 10 ¹⁵ cm ⁻² , resulting in a concentration of 1 × 10 ²⁰ cm ⁻³ , and Boron can be implanted into the P ⁺ body contact region 180 at an energy of 60 keV with a dose of 1 × 10 ¹⁵ cm ⁻² , thereby obtaining a dopant concentration of 5 × 10 ¹⁹ cm ⁻³ .

  A metal layer 184, preferably aluminum, is deposited as shown in FIG. 17I, creating a short between the source region 178 and the body contact region 180. That is, the source region and body contact region 180 are electrically connected. Patterning and etching metal layer 184 using a fifth (metal) mask (not shown) forms the source metal portion shown in FIG. 17I and the gate metal portion electrically connected to the gate. The Thereby, the fabrication of the MOSFET 70 is completed.

In another embodiment, the epitaxial layer is first lightly doped with N-type or P-type impurities, and a P-type impurity such as boron is implanted as a body dopant, the dopant being an interface between the epitaxial layer and the substrate. It is driven in until it reaches. Such an embodiment is shown in FIG. As shown in FIG. 18B, when boron is implanted and diffused, a P body region is formed on the N ⁺ substrate 102.

  The structure including the P body 176 as shown in FIG. 17D, the P body 186 as shown in FIG. 17E, and the P body 104 as shown in FIG. 18B forms the drain / drift region described herein. It can be used in combination with any of these processes. This process includes the process shown in FIGS. 12J and 12K, including diffusing the deeply implanted layer upward, and the upward diffusion of the deeply implanted layer and below the region implanted below the bottom of the trench. 12L and 12M including directional diffusion and the process illustrated in FIG. 12N including forming a stack of overlapping regions by implantation of multiple N-type regions at different energies.

  FIG. 6 shows an alternative embodiment. In MOSFET 95, the P-epi layer is divided into sub-layers P-epi1 and P-epi2. Using known processes, an epitaxial layer having sub-layers can be formed by changing the flow rate of the dopant gas during the growth of the epitaxial layer. Alternatively, the sublayer P-epi1 can be formed by implanting a dopant into the upper part of the epitaxial layer.

  The dopant concentration of the sublayer P-epi1 may be higher or lower than the dopant concentration of the sublayer P-epi2. The threshold voltage and punch-through breakdown voltage of the MOSFET are a function of the doping concentration of the sub-layer P-epi1, and the breakdown voltage and on-resistance of the MOSFET are a function of the doping concentration of the sub-layer P-epi2. Therefore, in the MOSFET of this embodiment, the threshold voltage and the punch-through breakdown voltage can be designed independently of the avalanche breakdown voltage and the on-resistance. The P-epi layer may include more than two sub-layers having different doping concentrations.

  MOSFET 95 includes a gate electrode 202 positioned in a trench 204 lined with an oxide layer. The upper surface of the gate 202 is recessed in the trench 204. The oxide layer includes a thick section 206 formed in accordance with the present invention generally disposed at the bottom of trench 204 and a relatively thin section 210 adjacent to the sidewalls of trench 204. There is a transition region 208 between the thick section 206 and the thin section 210, where the oxide layer thickness gradually decreases from the thick section 206 to the thin section 210. MOSFET 95 also includes a PN junction that intersects trench 204 at transition region 208. As described above, the location of the transition region 208 can be changed by changing the thickness of the nitride layer during fabrication of the MOSFET 95.

MOSFET 95 is also electrically connected to N ⁺ source region 214, P ⁺ body contact region 216, thick oxide layer 218 covering gate electrode 202, N ⁺ source region 214 and P ⁺ body contact region 216. A metal layer 220. As indicated by the dashed line, the MOSFET 95 includes a heavily doped region 222 at the bottom of the trench 204. The heavily doped region 222 can be created by implanting an N-type dopant such as arsenic or phosphorus after the nitride layer has been etched as shown in FIG.

FIG. 20 shows another alternative embodiment. In the MOSFET 98, the drain / drift region is omitted, and the trench 230 extends into the N ⁺ substrate 100 through the entire P-epi layer 102. This embodiment is particularly suitable for low voltage (eg 5 V or less) MOSFETs.

In order to increase the breakdown voltage (breakdown voltage) of the device, a lightly doped N-type epitaxial layer can be grown on the N ⁺ substrate 100 and under the P-epi layer 102. Some examples of this structure are shown in FIGS.

FIG. 21 shows a MOSFET 250 that is similar to the MOSFET 70 shown in FIG. 5A, but differs in that an N-epi layer 252 is grown on the N ⁺ substrate 100. The N-epi layer 252 may be 1-50 μm thick and phosphorus may be doped at a concentration of 1 × 10 ¹⁵ / cm ⁻³ to 1 × 10 ¹⁷ / cm ⁻³ . The doping concentration of the N-epi layer 252 may be higher or lower than the doping concentration of the P-epi layer 102.

Except for the growth of the N-epi layer 252, the process for fabricating the MOSFET 250 is similar to the process for fabricating the MOSFET 70 described above with reference to FIGS. 12A-12G. In particular, as shown in FIG. 12G, phosphorus / drift region 116 can be formed by implanting phosphorus through the bottom of the trench. However, the energy and dose of phosphorus implantation is set to ensure that the drain / drift region 116 extends downward not to the upper boundary of the N ⁺ substrate 100 but to the upper boundary of the N-epi layer 252.

FIG. 22 shows a MOSFET 260 having a drain / drift region 120 similar to the drain / drift region 120 shown in FIG. 12I. The MOSFET 260 implants phosphorus to form an N-type region immediately below the trench (see FIG. 12H), and then diffuses the phosphorus by heating to expand the N-type region downward and laterally. The drain / drift region 120 shown in FIG. 22 is formed.

  FIG. 23 shows a MOSFET 270 having a drain / drift region 124 similar to the drain / drift region 124 shown in FIG. 12K. The MOSFET 270 implants phosphorus to form an N-type region in the vicinity of the interface between the N-epi layer 252 and the P-epi layer 102 (see FIG. 12J), and then diffuses the phosphorus by heating to form an N-type region. The region is formed by extending upward and laterally to form the drain / drift region 124 shown in FIG.

  FIG. 24 shows a MOSFET 280 having a drain / drift region 126 similar to the drain / drift region 126 shown in FIG. 12M. To make MOSFET 280, a deep N layer (eg, phosphorus) is formed at the interface between N-epi layer 252 and P-epi layer 100 by a high energy implantation process. N-type dopants are implanted through the bottom of the trench to form a second N region just below the trench. This structure is then heated, for example to 900-1100 ° C. The deep N layer is diffused upward and the second N region is diffused downward until they are bonded together to form an N-type drain / drift region 126 as shown in FIG.

  FIG. 25 shows a MOSFET 290 including a drain drift region formed by performing a series of N implants with continuously increasing energy to create a stack of overlapping implant regions 128, similar to the structure shown in FIG. 12N. Indicates. The stack 128 includes four implant regions, but it is also possible to form a stack by implanting less than or more than four times. The stack can be formed without significant diffusion (ie, without heating), but may be heated to diffuse the dopant and increase the amount of overlap between the implanted regions.

  Another group of embodiments is similar to that shown in FIGS. 21-25, except that the thick bottom oxide region 150 is omitted and the bottom of the trench covers the inside of the walls of the trench 110. And the oxide layer having substantially the same thickness. To make this type of device, an N-type dopant such as phosphorus is implanted through the bottom of the trench 110 at the stage shown in FIG. 12C of the process, and deposition of the nitride layer 114 shown in FIGS. 12E and 12F. Further, the formation of the sidewall spacer 115 is omitted. If the N-type dopant is implanted to extend downward from the bottom of the trench as shown in FIG. 12G, the result is the MOSFET 300 shown in FIG. Alternatively, drain / drift regions of the type shown in FIGS. 12H-12I, 12J-12K, 12L-12M, and 12N are made by following the process described in connection with those figures. Is also possible. In any case, the drain / drift region extends from the bottom of trench 110 to the junction of N-epi layer 252.

Termination Region Devices made in accordance with the present invention are typically formed on a semiconductor die that was originally part of a semiconductor wafer. After the internal structure of the device is fabricated, the dies are separated from each other, usually by sawing the wafer with a scribe line that separates the dies. After a series of sawing in parallel, a second series of sawing is performed perpendicular to the first series of cuts.

As described above, an N-channel device according to the present invention is typically formed in a P-epi layer that covers an N ⁺ substrate or in a P-epi layer that covers an N-epi layer that covers an N ⁺ substrate. It is formed. Of course, these polarities are reversed in P-channel devices. Typically, in an N-channel device, the drain (N ⁺ substrate) is biased with some positive voltage and the N ⁺ source is grounded. Since the P body is normally shorted to the N ⁺ source, the P body is also grounded. The gate voltage typically varies between zero and some positive voltage when the device is turned off and on.

The process of cutting typically creates a current leakage path at the edge of the die, so the P-epi layer can reach a positive drain voltage when the N-channel device is turned off. A termination structure is required to prevent breakdown or current leakage between the P-epi layer and the N ⁺ source.

FIG. 27 shows the MOSFET 70 from FIG. 5A to the portion adjacent to the termination area 400. The termination area 400 includes a half trench 402A that extends to the edge 406 of the die. N region 408 extends downward from half trench 402 </ b> A to N-epi layer 252 through P-epi layer 102. P-epi layer 102 includes a P body layer 176. A source metal layer 184A that contacts the N ⁺ source and P body of MOSFET 70 extends into half trench 402A to cover BSPG layer 182, but there is a risk of electrical contact with the drain through the current leakage path described above. It ends before 406. In this structure, the portion of the source metal layer 184A that extends into the termination region 400 serves as a field plate for the junction of the N region 408 and the P-epi layer 102, widening the lines of electric force and Prevent yielding across joints.

FIGS. 28A-28E illustrate a method of making termination region 400 without adding any additional process steps to the process steps required to make MOSFET 70. FIG. The process is typically performed in parallel with the process described above, such as the process shown in FIGS. As shown in FIG. 28A, the process begins by forming an N-epi layer 252 and a P-epi layer 102 that cover the N ⁺ substrate 100. A pad oxide layer 104 is formed on the P-epi layer 102.

  A nitride layer 106 is deposited over the pad oxide layer 104 as shown in FIG. 28B. Nitride layer 106 and pad oxide layer 104 are patterned using a photolithographic process to form openings 410 in nitride layer 106 and pad oxide layer 104. Opening 410 coincides with, or includes, a scribe line between adjacent dies. This can be done simultaneously with the steps shown in FIG. 12B.

  As shown in FIG. 28C, a wide trench 402 is etched into the P-epi layer 102 through the opening 410. This can be done simultaneously with the steps shown in FIG. 12C.

  FIG. 28D shows the growth of the second pad oxide layer 412 in the trench 402. This can be done simultaneously with the growth of the pad oxide layer 112 shown in FIG. 12D.

  For example, as shown in FIG. 12G, when the drain drift region is implanted, the trench 402 remains exposed and the dopant enters the P-epi layer 102. The dopant is implanted and / or diffused in any of the above ways to form an N-type region 408 extending from the bottom of the trench 402 to the N-epi layer 252. This stage of the process is shown in FIG. 28E. No thick bottom oxide layer is formed in the wide trench 402. Thus, the nitride spacer 115 is not formed on the sidewalls of the wide trench 402 (see FIGS. 12E and 12F), and N-type dopant is implanted using the nitride layer 106 as a mask.

As mentioned above, at some point after the process, a BPSG layer 182 may be deposited and patterned to cover the gate electrode in the active region of the device. The deposition and patterning of the BPSG layer 182 is shown, for example, in FIGS. 17G and 17H. Following this, a metal layer 184 is deposited as shown in FIG. 17I. These layers are also deposited in the wide trench 402. When the metal layer 184 is patterned and divided into a source metal layer and a gate metal layer, the portion of the source metal layer 184A in the central region within the wide trench 402 is also etched, resulting in the structure shown in FIG. 28F. can get. This is done by conventional photolithography patterning and etching. As a result, the source metal layer 184A extends into the wide trench 402.

  After the BPSG layer 182 and metal layer 184 are deposited, a passivation layer (not shown) may be deposited to protect the top surface of the device.

  After these processes are performed, the die is sawed at the center of the wide trench 402, for example at dashed line 409 in FIG. 28F.

  Thereby, the structure shown in FIG. 28G is obtained, and a half trench 402A located at the edge 406 formed by sawing is formed. As shown in FIG. 28G, the BPSG layer 182 and the metal layer 184A extend from the top surface of the P-epi layer 102 into the half trench 402A. In this example, a P body layer 176 is implanted and diffused into the P-epi layer 102 (see FIG. 17D), but this is optional.

  29 and 30 show two alternative embodiments. In the embodiment shown in FIG. 29, openings 416 are formed in the BPSG layer 182 and the second pad oxide layer 412, and the edge pieces 184B are separated from the metal layer 184A. Preferably, these steps are performed simultaneously with the patterning of BPSG layer 182 and metal layer 184, respectively. The metal comprising layer 184 flows into opening 416 and makes ohmic contact with N region 408. Therefore, edge piece 184B is biased at the drain potential, and the lateral isolation distance between source metal layer 184A and edge piece 184B must be large enough to withstand the source-drain voltage. If a passivation layer is subsequently deposited, this will flow into the gap between the source metal layer 184A and the edge piece 184B.

The embodiment shown in FIG. 30 is similar to the embodiment of FIG. 29 except that an N ⁺ region 414 is formed at the bottom of the half trench 402A to enhance the ohmic contact between the edge piece 184B and the N region 408. It is different. N ⁺ region 414 may be implanted along the N ⁺ source region, as shown in FIG. 17F.

FIG. 31 shows the MOSFET 70 from FIG. 5A to the portion adjacent to the termination area 500. In this embodiment, an N epitaxial layer 252 is formed on the N ⁺ substrate 100 and a P epitaxial layer 102 is formed on the N epitaxial layer 252.

Termination area 500 includes four termination trenches 502, 504, 506 and 508. N region 510 extends from the bottom of each of trenches 502, 504, 506 and 508 to N epitaxial layer 252. Termination trenches 502, 504, 506 and 508 are each lined with an oxide layer 512 and filled with polysilicon 514. In the P epitaxial region 102, P ⁺ regions 516, 518, 520 and 522 are provided to the right of the termination trenches 502, 504, 506 and 508, respectively. Metal layers 524, 526, 528, and 530 connect polysilicon 514 in each of termination trenches 502, 504, 506, and 508 to P ⁺ regions 516, 518, 520, and 522, respectively, through openings in BPSG layer 182. Connect electrically. Polysilicon 514 in each of termination trenches 502, 504, 506 and 508, and P ⁺ regions 516, 518,
520 and 522 are electrically floated. Termination trenches 502, 504, 506 and 508 have a thick bottom oxide layer, as shown in FIG.

  In other embodiments, termination regions according to the present invention may include fewer or more than four termination trenches. In each embodiment, each of the metal layers is electrically connected to polysilicon in one of the plurality of termination trenches and a mesa adjacent to the termination trench. For example, if there are two termination trenches, the metal layer that is electrically connected to the polysilicon in the first termination trench is the P epitaxial layer 102 between the first termination trench and the second termination trench. The metal layer electrically connected to the inner mesa and electrically connected to the polysilicon in the second termination trench is electrically connected to the P epitaxial layer 102 on the opposite side of the second termination trench. Is done.

Typically, N ⁺ substrate 100, which represents the drain of MOSFET 70, is positively biased with respect to N ⁺ source region 178. As described above, in many examples, the source region is grounded and the drain is biased with a positive voltage. Each N ⁺ source region 178 is coupled to P body 103 via P ⁺ region 180 and source metal layer 184. Thus, the source-drain voltage of the chip is distributed across the termination trenches 502, 504, 506 and 508 or stepped down. Since the polysilicon filling each of the trenches 502, 504, 506, and 508 is in a floating state, the trenches function together as one voltage divider.

Termination region 500 can be fabricated with the same process steps used to fabricate MOSFET 70. However, in the area of termination region 500, there is no opening in the mask used to form N ⁺ source region 178, and BPSG layer 182 is patterned to terminate the termination trench as shown in FIG. Openings are formed above 502, 504, 506 and 508 and between termination trenches 502, 504, 506 and 508. P ⁺ regions 516, 518, 520, and 522 may be implanted through the openings in BPSG layer 182 between termination trenches 502, 504, 506, and 508. In addition, the source metal layer is patterned to form metal layers 524, 526, 528 and 530.

  The principle of the present invention can also be applied to structures other than the structure shown in FIG. In some embodiments, the trench has an implanted drain drift region, but may not have a thick bottom oxide layer. This is described in the aforementioned US application Ser. No. 10 / 317,568, and such an embodiment is shown in FIG. There, the trenches in MOSFET 80 and termination trenches 502, 504, 506, and 508 in termination region 600 do not include thick bottom oxide.

Furthermore, the principles of the invention are applicable to devices that do not include an implanted drain drift region. FIG. 33 shows a conventional trench MOSFET 90 and termination region 700 that are formed in an N epitaxial layer 92 that covers the N ⁺ substrate 100. P body region 94 is typically implanted into N epitaxial layer 92 and diffused to a level near the bottom of the trench, and N ⁺ source region 178 and P ⁺ body contact region 180 are formed in P body region 94. Again, the polysilicon in each of the termination trenches 502, 504, 506 and 508 and the adjacent portions of the P body region 94 step down the source-drain voltage.

Although several specific embodiments of the present invention have been described above, these embodiments are for illustrative purposes only. Those skilled in the art will appreciate that numerous additional embodiments may be made in accordance with the broad principles of the present invention. For example, the above embodiment is an N-channel MOSFET.
However, it is possible to make a P-channel MOSFET according to the present invention by reversing the conductivity types in various regions within the MOSFET.

¹ is a diagram showing a conventional trench MOSFET formed in an N epitaxial layer covering an N ⁺ substrate. FIG. It is a figure which shows the trench MOSFET which has a non-doped polysilicon plug near the bottom part of a trench. FIG. 5 shows a trench MOSFET having a thick oxide layer near the bottom of the trench. FIG. 6 is a diagram showing a MOSFET having a deep P ⁺ diffusion that extends downward to a level below the bottom of the trench near the center of the cell. (A) is a figure which shows the MIS device according to this invention, (B) is a figure which shows the depletion area | region formed in a device when a reverse bias is applied to the MIS device of (A). FIG. 2 shows a MIS device according to the invention in which the epitaxial layer is divided into two sub-layers with different doping concentrations. It is the graph produced using the computer simulation program SUPREME which shows the dopant density | concentration of MOSFET of FIG. 5 (A) in the longitudinal cross section which passes along a channel area | region. It is the graph produced using the computer simulation program SUPREME which shows the dopant density | concentration of MOSFET of FIG. 5 (A) in the longitudinal cross section which passes along the bottom part of a trench. 6 is a graph created using a computer simulation program MEDICI, showing the dopant concentration of the MOSFET of FIG. 5A in a vertical section through the channel region. It is the graph produced using computer simulation program MEDICI which shows the dopant density | concentration of MOSFET of FIG. 5 (A) in the longitudinal cross section which passes along the bottom part of a trench. FIG. 1 is a graph of a doping profile in a longitudinal section through a channel of a conventional MOSFET as shown in FIG. 1, wherein (A) is a graph showing that the doping concentration of the channel region rapidly decreases in the direction toward the drain; (B) is a graph showing that the doping concentration of the channel region is relatively constant. FIG. 9B is a graph of a doping profile similar to the graph of FIG. 9B, wherein FIG. 9A is a graph showing a case where a threshold adjustment injection portion is added, and FIG. 9B is a case where a body injection portion is added. It is a graph to show. It is a figure which shows the schematic shape of the doping profile in the longitudinal cross-section under a trench, when a drain drift region is formed by injecting a deep layer and diffusing the deep layer upward. FIG. 6 shows a process for forming a drain drift region by implanting a dopant between the trench sidewall spacers through the bottom of the trench. FIG. 6 shows a process for forming a drain drift region by implanting a dopant between the trench sidewall spacers through the bottom of the trench. FIG. 6 shows a process for forming a drain drift region by implanting a dopant between the trench sidewall spacers through the bottom of the trench. FIG. 6 shows a process for forming a drain drift region by implanting a dopant between the trench sidewall spacers through the bottom of the trench. FIG. 6 shows a process for forming a drain drift region by implanting a dopant between the trench sidewall spacers through the bottom of the trench. FIG. 6 shows a process for forming a drain drift region by implanting a dopant between the trench sidewall spacers through the bottom of the trench. FIG. 6 shows a process for forming a drain drift region by implanting a dopant between the trench sidewall spacers through the bottom of the trench. FIG. 6 shows a process for forming a drain drift region by implanting a dopant into a region immediately below a trench bottom between sidewall spacers of the trench and diffusing it downward toward the substrate. FIG. 6 shows a process for forming a drain drift region by implanting a dopant into a region immediately below a trench bottom between sidewall spacers of the trench and diffusing it downward toward the substrate. FIG. 5 shows a process for forming a drain drift region by implanting a deep layer of dopant below a trench and diffusing the dopant upwardly toward the trench. FIG. 5 shows a process for forming a drain drift region by implanting a deep layer of dopant below a trench and diffusing the dopant upwardly toward the trench. Implant dopant between the sidewall spacers of the trench to form a relatively shallow region directly below the bottom of the trench and a deep layer below the trench, and then diffuse the dopant until the shallow region and deep layer combine. FIG. 4 is a diagram showing a process of forming a drain / drift region by forming the drain drift region. Implant dopant between the sidewall spacers of the trench to form a relatively shallow region directly below the bottom of the trench and a deep layer below the trench, and then diffuse the dopant until the shallow region and deep layer combine. FIG. 4 is a diagram showing a process of forming a drain / drift region by forming the drain drift region. FIG. 5 shows a process for forming a drain / drift region by forming a stack of regions by performing a series of implants with different energies between trench sidewall spacers and through the bottom of the trench. FIG. 6 shows an example in which a heavily doped region is implanted into the drain drift region. FIG. 5 illustrates a process for forming a thick bottom oxide layer by depositing oxide between trench sidewall spacers. FIG. 5 illustrates a process for forming a thick bottom oxide layer by depositing oxide between trench sidewall spacers. FIG. 5 illustrates a process for forming a thick bottom oxide layer by depositing oxide between trench sidewall spacers. FIG. 4 illustrates a process for forming a thick bottom oxide layer by thermally growing oxide between trench sidewall spacers. FIG. 15 illustrates the process of FIG. 14 when the sidewall spacers have various different thicknesses. FIG. 4 illustrates a process for forming a thick bottom oxide layer by utilizing different deposition rates of oxide on various materials. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 6 illustrates a process for continuing to fabricate a MIS device after a thick bottom oxide layer is formed. FIG. 5 shows an example where the epitaxial layer is first lightly doped with N-type or P-type impurities and then P-type is implanted as a body dopant. It is a figure which shows a mode that creation of the edge termination area | region of a MIS device is simplified by this invention. FIG. 5 shows an example in which the drain drift region is omitted and the trench extends through the epitaxial layer into the substrate. It is a figure which shows the Example by which the low-concentration epitaxial layer of the same conductivity type as a board | substrate is formed on a board | substrate, and the proof pressure of a device is raised. It is a figure which shows the Example by which the low-concentration epitaxial layer of the same conductivity type as a board | substrate is formed on a board | substrate, and the proof pressure of a device is raised. It is a figure which shows the Example by which the low-concentration epitaxial layer of the same conductivity type as a board | substrate is formed on a board | substrate, and the proof pressure of a device is raised. It is a figure which shows the Example by which the low-concentration epitaxial layer of the same conductivity type as a board | substrate is formed on a board | substrate, and the proof pressure of a device is raised. It is a figure which shows the Example by which the low-concentration epitaxial layer of the same conductivity type as a board | substrate is formed on a board | substrate, and the proof pressure of a device is raised. FIG. 22 shows a MOSFET similar to the MOSFET shown in FIG. 21 but with the thick bottom oxide omitted. It is a figure which shows the termination | terminus area | region of MOSFET according to this invention. It is a figure which shows the process which produces the termination | terminus area | region of FIG. It is a figure which shows the process which produces the termination | terminus area | region of FIG. It is a figure which shows the process which produces the termination | terminus area | region of FIG. It is a figure which shows the process which produces the termination | terminus area | region of FIG. It is a figure which shows the process which produces the termination | terminus area | region of FIG. It is a figure which shows the process which produces the termination | terminus area | region of FIG. It is a figure which shows the process which produces the termination | terminus area | region of FIG. It is a figure which shows the 2nd Example of the termination | terminus area | region according to this invention. It is a figure which shows the 3rd Example of the termination | terminus area | region according to this invention. FIG. 6 is a cross-sectional view of a termination region of a MOSFET according to one aspect of the present invention. FIG. 6 is a cross-sectional view of an alternative termination region of a MOSFET according to the present invention. FIG. 6 is a cross-sectional view of another alternative termination region of a MOSFET according to the present invention.

Explanation of symbols

70 MIS device, 100 N ⁺ substrate, 102 P-epi layer, 103 P body, 110 trench, 116 N drain / drift region, 150 thick bottom oxide region, 170 gate oxide layer, 174 gate, 176 P body layer, 178 N ⁺ source region, 180 P ⁺ body contact region, 182 BSPG layer, 184 metal layer, 184A source metal layer, 252 N-epi layer, 400 termination area, 402A half trench, 406 edge, 408 N region, 500 termination area , 502, 504, 506, 508 termination trench, 510 N region, 512 oxide layer, 514 polysilicon, 516, 518, 520, 522 P ⁺ region, 524, 526, 528, 530 metal layer.

Claims (32)

A process for producing a termination region of a trench MIS device, comprising:
Providing a semiconductor wafer, the wafer including a first layer of a first conductivity type and a second layer of a second conductivity type covering the first layer;
Forming a first trench in the wafer, the first trench being coincident with a scribe line that delimits the die of the wafer, and a bottom of the first trench is in the second layer. Located, and
The first conductivity type dopant is introduced through the bottom of the first trench to form the first conductivity type region extending from the bottom of the first trench to the first layer. Steps,
Forming an insulating layer in the first trench and covering the surface of the second layer of the second conductivity type;
Forming a termination metal layer so as to cover the insulating layer in the first trench and the surface of the second layer of the second conductivity type;
Etching an opening in the metal layer at the bottom of the first trench, the scribe line intersecting the opening, and
Cutting the wafer with the scribe line with a saw.   Forming a second trench in an active region of the die while forming the first trench, the bottom of the second trench being located in the second layer. Item 2. The process according to Item 1.   While introducing the first conductivity type dopant through the bottom of the first trench, introducing the first conductivity type dopant through the bottom of the second trench, and The process of claim 2 including forming a drain drift region of the first conductivity type extending from the bottom of a second trench to the first layer.   4. The process of claim 3, comprising forming a source region of the first conductivity type adjacent to the surface of the second trench and the second layer.   The process of claim 4, comprising introducing a conductive material into the second trench to form a gate.   The process of claim 5, wherein forming the insulating layer comprises depositing an insulating layer that covers the gate and extends into the first trench.   The process of claim 6 including forming a source metal layer overlying the surface of the second layer, the source metal layer being electrically connected to the source region.   8. The process of claim 7, wherein the source metal layer extends into the first trench but does not extend to the scribe line.   9. The process of claim 8, wherein the source metal layer covers a junction of the first conductivity type region.   The process of claim 7, comprising forming an opening in the insulating layer at the bottom of the first trench.   Patterning the source metal layer to form an edge piece, the edge piece being provided at a position near the scribe line, electrically insulated from the rest of the source metal layer, and The process of claim 10, wherein the process extends into the opening in the insulating layer and is electrically connected to the region of the first conductivity type.   Forming a heavily doped region of the first conductivity type within the region of the first conductivity type, wherein the edge section is in electrical contact with the region of the first conductivity type that is heavily doped. The process of claim 11. A semiconductor die including a trench MIS device, wherein the die includes a first layer of a first conductivity type and a second layer of a second conductivity type covering the first layer, Includes a termination region, and the termination region is
A half trench formed in the second layer adjacent to an edge of the die;
A region of the first conductivity type extending from the bottom of the half trench to the first layer;
An insulating layer extending from the bottom of the half trench along the wall of the half trench and extending to cover the surface of the second layer;
A source metal layer covering the insulating layer, the source metal layer extending from a position in the half trench so as to cover a surface of the second layer, and the source metal layer is a source region of the MIS device. A semiconductor die, wherein the edge of the source metal layer in the half trench is laterally spaced from the edge of the die. A trench located in the second layer in the active region of the die;
A drain drift region of the first conductivity type extending from the bottom of the trench to the first layer;
A conductive gate in the trench,
The die of claim 13, wherein the insulating layer extends from a position above the trench into the half trench.   The die of claim 14, wherein the source region is adjacent to the trench.   The half trench includes a metal edge piece adjacent to the edge of the die, the metal edge piece being electrically insulated from the source metal layer, and from the first conductivity type region. The die of claim 13, which is electrically connected.   The die according to claim 13, wherein the metal edge piece is electrically connected to the region of the first conductivity type through an opening in the insulating layer at the bottom of the half trench.   The die of claim 17, comprising a region of the first conductivity type that includes a heavily doped region of the first conductivity type in contact with the metal edge piece.   The die according to claim 13, wherein the second layer includes an epitaxial layer of the second conductivity type.   The die according to claim 19, wherein the first layer includes a substrate and an epitaxial layer of the first conductivity type covering the substrate. A semiconductor die including a MIS device, the die including a first layer of the first conductivity type covering a second layer of a second conductivity type opposite to the first conductivity type; The die
Including an active region including a MIS device;
The MIS device is
An active trench comprising a conductive gate material and extending downwardly from a surface of the first layer, the bottom of the active trench being located in the first layer;
Including a source region of the second conductivity type in the first layer, the source region adjacent to the surface of the die and a sidewall of the active trench;
A drain drift region of the second conductivity type extending downward from the bottom of the active trench to the second layer;
The die further includes
Including the termination region,
The termination region is
Including at least first and second termination trenches, each of the termination trenches extending downward from the surface of the die, each of the termination trenches comprising a conductive material and in the first layer The conductive material in each of the termination trenches is insulated from the first layer by a dielectric layer covering the sidewalls of the termination trench and the interior of the bottom; and
A region of the second conductivity type extending from the bottom of each of the termination trenches to the first layer;
Including at least first and second metal layers above the surface of the die, the first metal layer comprising: the conductive material in the first termination trench; and the second layer. Electrically connected to a portion in the mesa between the first trench and the second trench, the second metal layer comprising the conductive material in the second termination trench; The conductive material in the first and second termination trenches is electrically connected to a portion of the second layer in a region opposite to the mesa of the second termination trench, A semiconductor die that is electrically isolated from each other and each of the conductive materials in the first and second termination trenches are electrically isolated from the source region and the first layer.   The semiconductor die of claim 21, wherein the conductive material in the first and second termination trenches can be electrically floated.   The semiconductor die of claim 21, wherein the second layer includes the substrate and a first epitaxial layer covering the substrate.   24. The semiconductor die according to claim 23, wherein the first layer includes a second epitaxial layer of a first conductivity type formed on the first epitaxial layer.   The semiconductor die of claim 21, wherein the conductive material comprises polysilicon.   The semiconductor die of claim 21, wherein the dielectric layer covering the interior of each of the termination trenches includes a thick portion at the bottom of the trench.   The surface of the first layer includes first and second contact regions of the second conductivity type, and the first and second contact regions are dopants of the first conductivity type and the first The first contact region is adjacent to the interface between the first metal layer and the first layer, and the second contact region is The semiconductor die of claim 21, adjacent to an interface between a second metal layer and the first layer. A semiconductor die including a MIS device, wherein the die includes a first layer of a first conductivity type covering a second layer of a first conductivity type, and the first layer covering the first layer. A body region of a second conductivity type opposite to the conductivity type, the die further comprising:
A plurality of trenches, the trenches including an active trench and a termination trench, each of the trenches extending from the surface of the die downwardly through the body region and having a bottom located in the first layer. In addition,
A plurality of mesas located between the trenches and between one of the termination trenches and an edge of the die;
Including an active area including a MIS device,
The MIS device is
An active trench comprising a conductive gate material;
A source region of the first conductivity type adjacent to the surface of the die and a sidewall of the active trench;
The die further includes
Including the termination region,
The termination region is
A dielectric layer that includes at least first and second termination trenches, each of the termination trenches including a conductive material, and wherein the conductive material in each of the termination trenches covers a sidewall and a bottom of the termination trench. Insulated from the body region and the first layer by,
At least first and second metal layers above the surface of the die, the first metal layer comprising the conductive material in the first termination trench, the first trench, and the first metal layer. Electrically connected to a first portion of the body region in a first mesa between two trenches, and the second metal layer includes the conductive material in the second termination trench; Electrically connected to a second portion of the body region in the second mesa on the opposite side of the second termination trench from the first mesa, and in the first and second termination trenches Conductive materials are electrically isolated from each other, and each of the conductive materials in the first and second termination trenches is electrically isolated from the source region and the first layer. , Semiconductor die.   Each of the first and second mesas includes a heavily doped contact region of the second conductivity type on the surface of the die, and the first and second metal layers are respectively 30. The semiconductor die of claim 28, in contact with heavily doped contact regions in the first and second mesas. A method of forming a semiconductor die including a MIS device, comprising:
Providing a semiconductor substrate;
Forming an epitaxial layer of a first conductivity type on the substrate, the substrate having a net doping concentration of a second conductivity type opposite to the first conductivity type, and
Etching a plurality of trenches in the epitaxial layer to form a plurality of mesas between the trenches and between one of the trenches and an edge of the die, the trenches comprising: Extending from the surface and having a bottom in the epitaxial layer, wherein the trench includes an active trench and a termination trench, the mesa comprising an active mesa between the active trenches, the one of the trenches and the die of the die. Including a termination mesa between the edge, and
Introducing the second conductivity type dopant through the bottom of the active trench and the termination trench to form the second conductivity type region extending between each of the trenches and the substrate; When,
Forming an oxide layer on the walls of the trench;
Filling the trench with a conductive material;
Implanting the second conductivity type dopant into the epitaxial layer while preventing the dopant from entering the epitaxial layer at a location adjacent to the termination trench, thereby providing a source adjacent to the active trench. Forming a region;
Forming a dielectric layer over the surface of the first layer;
Forming an opening above the source region, the termination trench and the termination mesa by masking and etching the dielectric layer;
Depositing metal to cover the dielectric layer and the opening;
Forming a source metal layer extending into the opening above the source region and a plurality of termination metal layers by masking and etching the metal, wherein the termination metal layers are electrically connected to each other. Each of the termination metal layers is in one of the openings above the termination trench and in one of the openings in the dielectric layer covering the termination mesa. Extending to electrically connect a conductive material and a termination mesa in one of the termination trenches.   31. The method of claim 30, comprising forming a contact region by implanting a dopant of the first conductivity type through the opening in the dielectric layer above the termination mesa.   32. The method of claim 30, wherein providing a semiconductor substrate comprises forming a second epitaxial layer of the second conductivity type on the semiconductor member of the second conductivity type.

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