KR20120017423A - LMDOS with self-aligned vertical LD and back drain - Google Patents

Abstract

The field effect transistor includes a first conductivity type semiconductor region having an upper surface and a lower surface, and the lower surface of the semiconductor region extends in contact with the substrate. Well regions of the second conductivity type are disposed in the semiconductor region. The field effect transistor also includes source regions of a first conductivity type disposed in the well regions, and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each gate electrode is insulated by the underlying well region and the gate dielectric. At least one LDD region of the first conductivity type is disposed in the semiconductor region every two adjacent well regions so as to contact two adjacent well regions. The sinker region is disposed in the semiconductor region directly below the at least one LDD region such that the sinker region is located along the vertical direction with the at least one LDD region between the top and bottom surfaces of the semiconductor region.

Description

LDMOS with self aligned vertical LDD and backside drain

Embodiments of the present invention relate to field effect transistors such as metal oxide semiconductor field effect transistors (MOSFETs) and methods of manufacturing field effect transistors.

Lateral Diffused MOS (LDMOS) structures are widely used in high voltage transistors. LDMOS transistors can provide a wide frequency range, high linearity, good ruggedness performance, and high breakdown voltages. Conventional LDMOS transistors have contacted source and drain regions near the surface of the semiconductor wafer, so that the current flow in the transistor is almost along the lateral dimension. In an alternative design, LDMOS transistors have drain contacts along the backside of the die. LDMOS transistors having a back drain have a structure arranged in a horizontal order of a source, a polysilicon gate, a lightly doped drain (LDD), and a sinker region. This arrangement tends to result in large device sizes. On the drain side of the transistor, the LDD region often extends laterally to obtain a high voltage. In addition, the sinker region needs to be sufficiently diffused to reach the backside drain. This deep diffusion tends to consume additional die area due to side diffusion and misalignment.

Thus, there is a need for an LDMOS structure that has a small cell pitch and good transistor performance and that can be formed using a simple fabrication process.

According to embodiments of the present invention, various techniques are described for reducing cell pitch and on-resistance R _{DS ( on )} in LDMOS transistors. In addition, embodiments of the present invention provide a method for manufacturing a simple and cost-effective LDMOS transistors.

According to an embodiment of the present invention, the field effect transistor includes a first conductive semiconductor region having an upper surface and a lower surface, wherein the lower surface of the semiconductor region extends in contact with the substrate. Well regions of the second conductivity type are disposed in the semiconductor region. The field effect transistor also includes source regions of a first conductivity type disposed in the well regions, and a gate electrode extending over each well region and overlapping a corresponding one of the source regions. Each of the gate electrodes is insulated by the gate region and the well region below. At least one LDD region of the first conductivity type is disposed in the semiconductor region every two adjacent well regions so as to contact two adjacent well regions. A sinker region is disposed in the semiconductor region directly below the at least one LDD region such that it is positioned along the vertical direction between the upper and lower surfaces of the semiconductor region. The sinker region has a higher dopant concentration than the at least one LDD region.

In one embodiment, the at least one LDD region is disposed between the gate electrodes and self-aligned to the gate electrodes.

In another embodiment, the sinker region is fully embedded within the semiconductor region so as not to reach the top surface of the semiconductor region.

In another embodiment, the semiconductor region includes two or more epitaxial layers.

In another embodiment, the semiconductor region includes an upper epitaxial layer and a lower epitaxial layer having different dopant concentrations.

In another embodiment, a portion of the sinker region extends laterally in the semiconductor region directly below the gate electrode.

In another embodiment, the at least one LDD region forms an upper LDD region, and the field effect transistor is of a first conductivity type disposed in the semiconductor region directly below the upper LDD region and directly above the sinker region. It further includes a lower LDD region.

In another embodiment, the lower LDD region has a higher dopant concentration than the upper LDD region and is disposed between the gate electrodes and self-aligned to the gate electrodes.

According to another embodiment of the present invention, the field effect transistor includes a first conductive semiconductor region having an upper surface and a lower surface, wherein the lower surface of the semiconductor region extends in contact with the substrate. A second conductivity type well region is disposed in the semiconductor region, and a source region of the first conductivity type is disposed in the well region. The field effect transistor also includes a gate electrode extending over the well region and overlapping the source region, wherein the gate electrode is insulated by the well region and a gate dielectric. An upper LDD region of a first conductivity type is disposed in the semiconductor region adjacent to and in contact with the well region, and a lower LDD region of the first conductivity type is disposed in the semiconductor region immediately below and in contact with the upper LDD. . Both the upper LDD region and the lower LDD region are self-aligned to the gate electrode. In addition, a sinker region is disposed in the semiconductor region immediately below and in contact with the lower LDD region such that it is located in a vertical direction between the upper and lower LDD regions between the upper and lower surfaces of the semiconductor region. In one embodiment, the sinker region has a higher dopant concentration than the upper and lower LDD regions.

In one embodiment of the field effect transistor, the sinker region is fully embedded within the semiconductor region so as not to reach the top surface of the semiconductor region.

In another embodiment, the semiconductor region includes an upper epitaxial layer and a lower epitaxial layer, wherein the upper epitaxial layer has a lower doping concentration than the lower epitaxial layer, and the lower epitaxial layer is lower than the substrate. Has a doping concentration.

In another embodiment, the sinker region extends through both the lower and upper epitaxial layers, and both the lower and upper LDD regions extend only into the upper epitaxial layer.

In another embodiment, a portion of the sinker region extends laterally in the semiconductor region directly below the gate electrode.

According to an alternative embodiment of the present invention, a method of manufacturing a field effect transistor includes the following steps. First, a first conductive semiconductor region having an upper surface and a lower surface is formed, and the lower surface of the semiconductor region extends in contact with the substrate. The semiconductor region includes a sinker region of a first conductivity type. The method includes forming gate electrodes on a semiconductor region, forming well regions of a second conductivity type in the semiconductor region, and forming source regions of a first conductivity type in the well regions. do. At least one LDD region is formed in the semiconductor region every two adjacent well regions such that at least one LDD region contacts the two adjacent well regions.

In one embodiment of the method, the sinker region is fully embedded within the semiconductor region so as not to reach the upper surface of the semiconductor region.

In another embodiment, the semiconductor region includes two or more epitaxial layers.

In another embodiment, the forming of the semiconductor region may include forming a lower epitaxial layer of a first conductivity type on the substrate, and forming a first conductive layer into the lower epitaxial layer to form an implant region. Selectively implanting dopants of a type, forming an upper epitaxial layer of a first conductivity type over the lower epitaxial layer, and dopants in the implant region are diffused into the upper epitaxial layer, the implant region and Performing a temperature cycle such that the out-diffused regions together form the sinker region.

In another embodiment, the upper epitaxial layer has a lower doping concentration than the lower epitaxial layer, and the lower epitaxial layer has a lower doping concentration than the substrate.

In another embodiment, forming the at least one LDD region may include forming the gate electrodes such that the at least one LDD region formed between two adjacent well regions is self-aligned with corresponding gate electrodes. Implanting dopants of a first conductivity type into the semiconductor region using as a mask.

In another embodiment, forming the at least one LDD region may include implanting dopants of a first conductivity type using the gate electrodes as a mask to form an upper LDD region in the semiconductor region, and Implanting dopants of a first conductivity type using the gate electrodes as a mask to form a lower LDD region in a semiconductor region. The lower LDD region is directly over and in contact with the sinker region and the upper LDD region is directly over and in contact with the lower LDD region. In some embodiments, the sinker region has a higher doping concentration than the lower LDD region, and the lower LDD region has a higher doping concentration than the upper LDD region.

Various additional features and advantages of the invention will be further understood with reference to the following detailed description and the accompanying drawings.

According to the present invention, there is provided an LDMOS structure having a small cell pitch and excellent transistor performance, which can be formed using a simple fabrication process.

1 is a schematic cross-sectional view of an LDMOS transistor according to an embodiment of the present invention.
2 is a schematic cross-sectional view of an LDMOS transistor according to another embodiment of the present invention.
3A-3J are schematic cross-sectional views illustrating a schematic process flow for fabricating an LDMOS transistor characterized by vertically stacked LDD and sinker regions, in accordance with an embodiment of the present invention.
4 shows an exemplary doping profile of an LDMOS transistor according to one embodiment of the invention.

Embodiments of the present invention relate to LDMOS transistors having a small cell pitch and low resistance R _{DS ( on )} . In some embodiments of the present invention, one or more LDD regions are arranged in a vertical stack with a sinker region, wherein the LDD region (s) are self-aligned to the gate electrodes. This arrangement substantially reduces the cell pitch: (1) by stacking LDD region (s) and sinker regions that are typically laterally arranged in conventional LDMOS transistors, and (2) self-aligning manner of LDD regions. By reducing the cell pitch by eliminating provisions for misalignment that must occur in conventional LDMOS designs.

In some embodiments, the LDD region (s) and the sinker region are formed between two gate electrodes and are shared by two half cells. The LDD region (s) may be self-aligned to all of the gate electrodes, and the LDD region (s) are oriented so as to extend vertically rather than laterally, such that the LDD region (s) are between the gate electrodes. Lithographic performance can be used to create the smallest possible space. In certain embodiments, the sinker region is first implanted into the lower semiconductor layer and then diffused into the upper semiconductor layer, and then one or more LDD regions are formed in the upper semiconductor layer directly on top of the sinker region. . Implants and thermal cycles are designed such that the sink region and the underlying LDD region (s) contact each other to ensure reduced R _{DS ( on )} .

1 is a schematic cross-sectional view of an LDMOS transistor 100 according to an embodiment of the present invention. LDMOS transistor 100 includes a semiconductor region 102 having an upper surface 131 and a lower surface 132. The bottom surface 132 of the semiconductor region 102 extends in contact with the heavily doped substrate 101. In the illustrated embodiment, the semiconductor region 102 includes two epitaxial layers, a lower epitaxial layer 103 and an upper epitaxial layer 104, but depending on design goals, more than just one or two. Many epitaxial layers may be used. The LDMOS transistor 100 includes well regions 111 extending into the semiconductor region 102, source regions 114 and heavy body regions 113 extending into the well regions 111. It includes. In the exemplary embodiment shown, the substrate 101, the semiconductor region 102, and the source regions 114 are n-type, and the well regions 111 and the high concentration body regions 113 are p-type. to be.

The sinker region 105 is embedded within the semiconductor region 102. One or more LDD regions, for example regions 109 and 112, are also formed in the semiconductor region 102 and are stacked vertically over the sinker region 105. Vertical stacking allows the LDD regions to be optimized for reduced resistance and reduced cell pitch. In a particular embodiment, the upper LDD region 109 is self-aligned to the gate electrodes 108, adjacent to and in contact with the well regions 111. In embodiments having a second lower LDD region 112, the lower LDD region 112 is disposed in the semiconductor region 102 directly below the upper LDD region 109, and the second LDD region 112 is also a gate electrode. Self-aligned to the field 108. In embodiments having only one LDD region 109, the LDD region is in direct contact with the sinker 105. In one embodiment, the sinker region 105 has a higher dopant concentration than the two LDD regions 109 and 112, and the lower LDD region 112 has a higher dopant concentration than the upper LDD region 109. The dopant profile results in low R _{DS ( on )} and high breakdown voltage.

LDMOS transistor 100 has gate electrodes 108 extending over semiconductor region 102. One side of each gate electrode 108 has a source region 114 disposed on the side, and the other side has an LDD region 109 disposed on the side. The gate electrodes 108 extend over the well regions 111 and overlap the source regions 114 and the LDD region 109. In addition, gate electrodes 108 are insulated from underlying layers by gate dielectric layer 106. Another dielectric layer 115 may be formed over the gate electrodes 108 to insulate the gate electrodes 108 from the top source connection layer 116.

Source connection layer 116 (eg, including metal) is formed on dielectric layer 115 and is in contact with source regions 114 and high concentration body regions 113. The drain connection layer 117 is in contact with the substrate 101 along the rear surface of the transistor 100. During transistor operation, at least a portion of the current flows through the upper and lower LDD regions and the sinker region.

FIG. 2 shows a half-cell representation of the LDMOS transistor of FIG. 1, except for the same structure as that of FIG. 1. According to embodiments of the invention, many variations of the structure shown in FIGS. 1 and 2 are possible. For example, more than two LDD regions may be formed on the sinker region, depending _{on the} desired breakdown voltage and R _{DS ( on )} . These additional LDD regions may be self-aligned to the gate electrodes. In some embodiments, the sinker region may also be formed using an ion implant self-aligned to the gate electrode. There may of course be other alternatives and variations, some of which are discussed below.

3A-3J are cross-sectional views illustrating schematic process flows for manufacturing the LDMOS transistor shown in FIG. 2, in accordance with an embodiment of the present invention. In FIG. 3A, the semiconductor region 302 is formed on the n-type substrate 301. The substrate 301 is preferably heavily doped. Highly doped substrates may be formed using conventional techniques, or may be commercially available. In some embodiments, the semiconductor region 302 is also n-type. The semiconductor region 302 may be one continuous layer (eg, one epitaxial layer) or may include multiple epitaxial layers. If semiconductor region 302 includes multiple epitaxial layers, each epitaxial layer may have a different doping concentration, depending on design goals.

The heavily doped sinker region 305 embedded in the semiconductor region 302 may be formed using conventional implant techniques. The sinker region 305 may extend across several epitaxial layers included in the semiconductor region 302. In the illustrated embodiment, the sinker region 305 extends within both the lower epitaxial layer 303 and the upper epitaxial layer 304. Hard masks (not shown) may be used to obtain the formation of the desired implant and sinker regions 305.

In a particular embodiment, lower epitaxial layer 303 is first formed on substrate 301. To form the sinker region 305, a masked implant step is performed to implant the n-type dopants into certain regions of the lower epitaxial layer 303. Next, an upper epitaxial layer 304 is formed on the lower epitaxial layer 303. In an alternative embodiment, the sinker implant step may be performed after both epitaxial layers 303 and 304 are formed. In this case, higher implant energy may be used to position the sinker region at the desired depth. In order to allow the sinker dopants to diffuse into the upper epitaxial layer 304 and to allow the dopants from the n + substrate 301 to diffuse into the lower epitaxial layer 303, an annealing step may follow after the implant step. . The annealing step results in a dopant distribution that reduces electrical resistance and also heals structural damage to the epitaxial layers during the implant steps. Implant dopant type, concentration and implant energy to form the sinker region and various LDD regions, as well as temperature cycles, can be designed to ensure final structure, the sinker region 305 being in contact with the lower LDD region 312 and The lower LDD region 312 contacts the upper LDD region 309 to ensure a low R _{DS ( on )} .

Next, as shown in FIG. 3B, a gate dielectric layer 306 is formed on the upper epitaxial layer 304. Gate dielectric layer 306 may be formed using known techniques, such as a gate dielectric process. In one embodiment, gate dielectric layer 306 is formed by exposing top epitaxial layer 304 to an oxidizing atmosphere. Next, a polysilicon layer 307 is formed on the gate dielectric layer 306. Next, the polysilicon layer 307 is selectively removed to form the gate electrode 308 as shown in FIG. 3C. Optionally, a second insulating layer 320 may be formed on the gate electrode 320 to seal the gate electrode without exposing it to subsequent processing steps. Insulating layer 320 may be formed, for example, by oxidizing polysilicon gate 308. In an alternate embodiment, a silicide layer may be formed on the polysilicon layer prior to patterning the gate electrode.

3D shows the formation of the upper LDD region 309. After formation of the gate electrode 308, dopants for forming the upper LDD region 309 are implanted in the upper epitaxial layer 304 without using a mask layer. Thus, the upper LDD region 309 is self-aligned to the gate electrode 308. Since no mask is used, dopants are implanted on both sides of the gate electrode 308. However, subsequent p-well and source implants will compensate for the dopants implanted in this step with respect to the source side of the gate electrode 308. In one embodiment, the LDD dopant used is arsenic implanted with a dose of about 4E12 ions / cm ² , and the implant energy used is about 120 KeV. In an alternate embodiment, a mask layer may be used to prevent the source side of gate 308 from being exposed to dopants.

In FIG. 3E, mask layer 310 is used to cover the drain side of gate electrode 308, and another implant step is performed to form p-type well region 311. Well drive-in is then performed. One of many known techniques can be used for the well implant and drive-in. Note that the upper LDD region 309 may be formed after forming the well region 311. In FIG. 3F, the mask layer 322 (which may be the same as the mask layer used for the well implant of FIG. 3E) may be used to form the gate electrode 308 during the source implant process to form the n-type source region 314. Used to cover the drain side. The source region is heavily doped with arsenic or phosphorus using known techniques.

In FIG. 3G, an LDD implant is performed to form the lower LDD region 312 without a mask. Thus, the lower LDD region is self-aligned to the gate electrode 308. Lower LDD region 312 has a higher dopant concentration than upper LDD region 309 and is implanted with higher energy. Upper and lower LDD regions 309 and 312 are formed such that both upper and lower LDD regions 309 and 312 and sinker region 305 form a vertical stack, as shown. In one embodiment, lower LDD region 312 is formed with a phosphorus of about 2.7E13 ions / cm ² and an energy of about 170 KeV. In an alternate embodiment, lower LDD region 312 may be formed using a mask to prevent the LDD dopants from entering the source side of gate electrode 308, if desired.

In one embodiment, the substrate is heavily doped with phosphorus, the lower epitaxial layer is arsenic doped, and serves as a capping layer for controlling the top-diffusion of dopants from the substrate. In the above embodiment, the sinker region and the upper LDD region are formed using arsenic dopants, and the lower LDD region is formed using phosphorus. In order to minimize R _{DS ( on )} without excessive lateral diffusion of the LDD regions, the appropriate dopant concentrations and combinations of energies and dopant types, together with appropriate thermal cycles, are used in the sinker region and the upper and lower LDD regions. Let them touch each other.

Next, in FIG. 3H, a mask layer 324 is used to define a window that allows high concentration body dopants to be implanted into the body region 311 to form the high concentration body region 313. In FIG. 3I, dielectric layer 315 is formed on gate electrode 308 using conventional techniques. In one embodiment, dielectric layer 315 includes BPSG. In FIG. 3J, a portion of dielectric layer 315 is removed, a high density body recess formed through known source and extending through source region 314 and terminating within high density body region 313. Next, source connection layer 316 is formed on dielectric layer 315 using conventional methods. The source connection layer 316 is in contact with the source region 314 and the high concentration body region 313. The source connection layer 316 may be formed of a suitable metal such as aluminum, copper, heat resistant metal, metal silicide, or the like. In an alternate embodiment, high concentration body region 313 may be formed by implanting dopants along the bottom of the high concentration body recess after the high concentration body recess is formed. Finally, a drain connection layer 317 is formed on the backside of the substrate, completing the transistor structure.

Although FIGS. 3A-3J illustrate a particular sequence of steps for forming an LDMOS field effect transistor, it should be noted that other orders or steps may be performed in accordance with alternative known techniques. In addition, the individual steps shown in FIGS. 3A-3J may include a number of sub-steps that may be performed in various orders, suitable for each individual step. Also, depending on the particular design, additional steps may be added or removed. Those skilled in the art will recognize many variations, modifications, and alternatives in light of the present disclosure.

4 shows an exemplary doping profile along line AA ′ of FIG. 3J. In FIG. 4, the horizontal axis from left to right corresponds to the vertical dimension from the top surface of the semiconductor region 302 to the substrate 301. It can be seen that the upper epitaxial layer extends to a depth of about 0.55 μm. The second epitaxial layer has a thickness of about 1.5 μm and extends from a depth of about 0.55 μm to a depth of about 2.05 μm. A portion of the substrate is shown from about 2.05 μm to 3.00 μm.

In FIG. 4, reference numeral 401 is used to identify the general position of the upper and lower LDD regions, and reference numeral 402 is used to identify the general position of the sinker region. As shown, the sinker region has a peak concentration near the top surface of the upper epitaxial layer implanted with sinker dopants. Subsequent thermal cycles cause the sinker dopants to diffuse into the upper epitaxial layer. During various thermal cycles, dopants from the heavily doped substrate 404 also diffuse into the lower epitaxial layer, resulting in a gradual dopant profile, indicated at 403 in FIG. 4. The exemplary dopant profile of FIG. 4 advantageously reduces transistor on-resistance R _{DS ( on )} while maintaining the desired breakdown voltage. The particular dopant profile shows only a specific example in accordance with one embodiment of the present invention, and it is understood that the process conditions can be adjusted to create various areas of electrical resistance and dopant profile to meet the requirements of specific designs. For example, depending _{on the} desired breakdown voltage and R _{DS ( on )} , the doping concentration of two LDD regions can be adjusted, or only one LDD region can be used instead of two, or alternatively two Three or more LDD regions formed in the epitaxial layers may be used.

Many advantages can be realized by the present invention. For example, by stacking LDD and sinker regions in the vertical direction, it is possible to reduce the cell pitch, thus increasing the number of cells that can be accommodated within a given die size. As in another example, by the ability to adjust the doping concentrations of the LDD and sinker regions, it is possible to control the overall resistance of the regions. It also helps to adjust R _{DS ( on )} which provides the transistor with improved switching characteristics. In addition, the above-described embodiments provide self-aligned LDD regions on the drain side of the gate electrodes, thus reducing the complexity and cost of the process. In one particular embodiment, a cell pitch reduction from 2.0-2.2 μm of the conventional LDMOS transistors being compared to about 1.2 μm of LDMOS formed using the techniques of the present invention was obtained.

While a complete description of certain embodiments of the invention has been described above, various modifications, changes, and alternatives may be used. For example, while silicon is given as one example of the substrate material, other materials may be used. Also, although an implant is given as an example of introduction of dopants, other doping methods, such as gas or topical dopant sources, may be used to provide dopants for diffusion, depending on the appropriate mask used. In addition, the process sequences shown by FIGS. 3A-3J are for n-channel FETs, and it will be apparent to those skilled in the art in view of the present disclosure to modify the process sequences to form p-channel FETs. . Accordingly, the scope of the present invention should not be limited to the above-described embodiments, but is defined by the following claims.

Claims (20)

A first conductive semiconductor region having an upper surface and a lower surface extending in contact with the substrate;
Well regions of a second conductivity type disposed in the semiconductor region;
Source regions of a first conductivity type disposed in the well regions;
A gate electrode extending over each well region and overlapping a corresponding one of the source regions, each of which is insulated by a gate dielectric with a lower well region;
At least one LDD region of a first conductivity type disposed in the semiconductor region every two adjacent well regions so as to contact two adjacent well regions; And
Disposed in the semiconductor region directly below the at least one LDD region, such that the upper and lower surfaces of the semiconductor region are located in a direction perpendicular to the at least one LDD region; A field effect transistor comprising a sinker region having a high dopant concentration. The method according to claim 1,
And wherein the at least one LDD region is disposed between the gate electrodes and self-aligned to the gate electrodes. The method according to claim 1,
And the sinker region is completely embedded in the semiconductor region so as not to reach the upper surface of the semiconductor region. The method according to claim 1,
And the semiconductor region comprises two or more epitaxial layers. The method of claim 4, wherein
And wherein the semiconductor region comprises an upper epitaxial layer and a lower epitaxial layer having different dopant concentrations. The method according to claim 1,
And a portion of the sinker region extends laterally in the semiconductor region directly below the gate electrode. The method according to claim 1,
The at least one LDD region forms an upper LDD region,
And the field effect transistor further includes a first conductive type lower LDD region disposed in the semiconductor region directly below the upper LDD region and directly above the sinker region. The method of claim 7, wherein
And the lower LDD region has a higher dopant concentration than the upper LDD region and is disposed between the gate electrodes and self-aligned to the gate electrodes. A first conductive semiconductor region having an upper surface and a lower surface extending in contact with the substrate;
A well region of a second conductivity type disposed in the semiconductor region;
A source region of a first conductivity type disposed in the well region;
A gate electrode extending over the well region and overlapping the source region and insulated by the well region and a gate dielectric;
An upper LDD region of a first conductivity type disposed in the semiconductor region adjacent to and in contact with the well region and self-aligned to the gate electrode;
A lower LDD region of a first conductivity type disposed in the semiconductor region immediately below and in contact with the upper LDD and self-aligned to the gate electrode; And
Disposed in the semiconductor region directly below and in contact with the lower LDD region, such that the upper and lower LDD regions are located in a vertical direction between the upper and lower surfaces of the semiconductor region. A field effect transistor comprising a sinker region having a higher dopant concentration than the regions. 10. The method of claim 9,
And the sinker region is completely embedded in the semiconductor region so as not to reach the upper surface of the semiconductor region. 10. The method of claim 9,
The semiconductor region includes an upper epitaxial layer and a lower epitaxial layer,
The upper epitaxial layer has a lower doping concentration than the lower epitaxial layer, and the lower epitaxial layer has a lower doping concentration than the substrate. The method of claim 11, wherein
And the sinker region extends through both the lower and upper epitaxial layers, and both the lower and upper LDD regions extend only into the upper epitaxial layer. 10. The method of claim 9,
And a portion of the sinker region extends laterally in the semiconductor region directly below the gate electrode. Forming a first conductivity type semiconductor region having an upper surface and a bottom surface extending in contact with the substrate, the semiconductor region comprising a sinker region of a first conductivity type;
Forming gate electrodes on the semiconductor region;
Forming well regions of a second conductivity type in the semiconductor region;
Forming source regions of a first conductivity type in the well regions; And
Forming at least one LDD region in the semiconductor region every two adjacent well regions so as to contact two adjacent well regions. The method of claim 14,
And the sinker region is completely embedded in the semiconductor region so as not to reach the upper surface of the semiconductor region. The method of claim 14,
And said semiconductor region comprises at least two epitaxial layers. The method of claim 14,
Forming the semiconductor region,
Forming a lower epitaxial layer of a first conductivity type on the substrate;
Selectively implanting dopants of a first conductivity type into the lower epitaxial layer to form an implant region;
Forming an upper epitaxial layer of a first conductivity type on the lower epitaxial layer; And
Fabricating a field effect transistor comprising diffusing dopants in the implant region into the upper epitaxial layer and performing a temperature cycle such that the implant region and the out-diffused region together form the sinker region. Way. The method of claim 17,
And wherein the upper epitaxial layer has a lower doping concentration than the lower epitaxial layer, and the lower epitaxial layer has a lower doping concentration than the substrate. The method of claim 14,
Forming the at least one LDD region,
Implanting dopants of a first conductivity type in the semiconductor region using the gate electrodes as a mask such that the at least one LDD region formed between two adjacent well regions is self-aligned with corresponding gate electrodes. A method of manufacturing a field effect transistor, comprising the step. The method of claim 14,
Forming the at least one LDD region,
Implanting dopants of a first conductivity type using the gate electrodes as a mask to form an upper LDD region in the semiconductor region; And
Implanting dopants of a first conductivity type using the gate electrodes as a mask to form a lower LDD region in the semiconductor region,
The lower LDD region is directly over and in contact with the sinker region, the upper LDD region is directly over and in contact with the lower LDD region,
The sinker region has a higher doping concentration than the lower LDD region, and the lower LDD region has a higher doping concentration than the upper LDD region.

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