JP5601816B2 - Manufacturing method of semiconductor device - Google Patents

Description

  The present invention relates to a semiconductor device, and more particularly to a trench gate type power semiconductor device used for control of high power and a method for manufacturing the same.

  Power semiconductor devices are high-power semiconductor devices used to control electric devices such as motors. Power MOSFETs (MOS: Metal-Oxide-Semiconductor, FET: Field Effect Transistor) and IGBTs (Insulated Gate Bipolar Transistors) MOS transistors such as are mainly used. In recent years, inverter control in motor control has become widespread due to demands for energy saving and environmental load reduction, and higher efficiency (low loss) power semiconductor devices are required.

  As one method for improving efficiency (lowering loss), reduction of conduction loss (on-resistance) has been attempted by miniaturizing a unit cell. In addition, by adopting the “trench gate structure” as the cell structure of the semiconductor device, the cell area can be greatly miniaturized while increasing the channel width. On-resistance has been greatly reduced (see, for example, Patent Document 1).

JP 2000-277531 A

As described above, the trench gate structure enables a significant reduction in cell area as compared with the planar gate structure. However, with further progress in miniaturization in recent years, the threshold voltage V _{th of the} cell is reduced. There are some problems that the value is higher than the design value or varies from cell to cell and that the withstand voltage (breaking current / rated current) is lower than the specified value. These problems are problems to be solved when further increasing the efficiency of the power semiconductor device.

Accordingly, an object of the present invention is to provide a semiconductor device having a trench gate structure and a method for manufacturing the same, which can ensure a desired withstand voltage even when a unit cell is miniaturized and can suppress variations in threshold voltage _Vth for each cell. It is to provide.

In order to achieve the above object, the present invention is a semiconductor device including a MOS transistor having a trench gate structure,
The transistor has a first conductivity type channel region formed between adjacent trench regions, two second conductivity type source regions, and a first conductivity type semiconductor region formed between the two second conductivity type source regions. And
The first conductivity type semiconductor region is formed to protrude in a rectangular shape from the two second conductivity type source regions toward the first conductivity type channel region,
In the region forming the boundary between the first conductivity type semiconductor region and the first conductivity type channel region, the region having the concentration gradient of the first conductivity type impurity in the width direction of the trench region is 200 dB / μm or more. A semiconductor device is provided.

The present invention also provides a method for manufacturing a semiconductor device comprising a MOS transistor having a trench gate structure in order to achieve the above object.
The transistor has a first conductivity type channel region formed between adjacent trench regions, two second conductivity type source regions, and a first conductivity type semiconductor region formed between the two second conductivity type source regions. And
The first conductivity type semiconductor region is formed to protrude in a rectangular shape from the two second conductivity type source regions toward the first conductivity type channel region,
In the region forming the boundary between the first conductivity type semiconductor region and the first conductivity type channel region, the region having the concentration gradient of the first conductivity type impurity in the width direction of the trench region is 200 dB / μm or more. And
There is provided a method of manufacturing a semiconductor device, wherein the diffusion heat treatment for forming the first conductive type semiconductor region is a laser annealing process using a laser beam having a wavelength of 1.1 μm or less.

According to the present invention, in a semiconductor device including a MOS transistor having a trench gate structure, a desired cutoff withstand is ensured even if a unit cell is miniaturized, and variation in threshold voltage _Vth for each cell is suppressed. A semiconductor device having the trench gate structure can be provided.

FIG. 5 is a schematic vertical sectional view showing an example of a conventional structure of a p-channel IGBT trench gate structure cell. FIG. 4 is a schematic vertical cross-sectional view showing an example of an ideal structure of a p-channel IGBT trench gate structure cell. 6 is a graph showing an example of a relationship between a distance between u1 and p1 in FIG. 1 and a threshold voltage _Vth in a conventional semiconductor device. It is the graph which showed one example of the relationship between the distance between u1-p1 in FIG. 1, and interruption | blocking tolerance in the conventional semiconductor device. It is a graph which shows an example of the measurement result of the concentration distribution of the p-type impurity in the conventional semiconductor device. It is a principal part longitudinal cross-sectional schematic diagram of one example of the semiconductor device which concerns on this invention. It is a schematic diagram of the principal part longitudinal cross-section after a trench area | region (a gate insulating film and a gate electrode) formation process. It is a schematic diagram of a main part longitudinal section showing an ion implantation process for forming a p − type semiconductor region (channel region). It is a schematic diagram of the principal part longitudinal cross-section after a p <-> type | mold semiconductor region (channel region) formation process. It is a schematic diagram of an essential part longitudinal section showing an ion implantation process for forming an n + -type semiconductor region (source region). It is a schematic diagram of the principal part longitudinal cross-section after an n + type semiconductor region (source region) formation process. It is a schematic diagram of the principal part longitudinal cross-section which shows the ion implantation process for p + type semiconductor region formation. It is a schematic diagram of the principal part longitudinal cross-section which shows the laser annealing process for p + type semiconductor region formation. It is a graph which shows an example of the measurement result of the density | concentration distribution of the p-type impurity in the semiconductor device which concerns on this invention. It is a schematic diagram of the principal part longitudinal cross-section after an interlayer insulation film formation process. It is a schematic diagram of the principal part longitudinal cross-section which shows the etching process process of an interlayer insulation film. It is a schematic diagram of the principal part longitudinal cross-section which shows the ion implantation process for p + type semiconductor region formation. It is a schematic diagram of the principal part longitudinal cross-section which shows the laser annealing process for p + type semiconductor region formation. It is a schematic diagram of the principal part longitudinal cross-section after an interlayer insulation film shaping process.

  The inventors of the present invention have completed the present invention as a result of investigating in detail the factors that cause the above problems in miniaturization of unit cells and intensively researching them. First, a conventional semiconductor device will be described.

  FIG. 1 is a schematic longitudinal sectional view showing a conventional (realistic) structural example of a p-channel IGBT trench gate structure cell, and FIG. 2 is an ideal structural example of a p-channel IGBT trench gate structure cell. It is the longitudinal cross-sectional schematic diagram which showed. As shown in FIGS. 1 and 2, a p-channel IGBT trench gate structure cell includes an n + type semiconductor layer 2 and an n − type semiconductor layer (drift layer) 3 stacked on a p + type semiconductor substrate 1 and n A p-type semiconductor region (channel region) 4, an n + type semiconductor region (source region) 6 and a trench region 7 (gate insulating film 8 and gate electrode 9) are formed on the -type semiconductor layer (drift layer) 3. Metal wirings 12 are formed on the upper surfaces of these semiconductor laminates 10 with an interlayer insulating film 11 therebetween. A p + type semiconductor region 5 is interposed between two n + type semiconductor regions (source regions) 6 sandwiched between the two trench regions 7 so as to protrude into the p − type semiconductor region (channel region) 4. Is formed.

  In addition, a layer or region having “n” or “p” in the conductivity type means a layer or region in which electrons and holes are majority carriers, and “+” and “−” are impurities (n-type). It means that the concentration of impurities and p-type impurities is relatively high or relatively low. In the case of an n-channel IGBT, the conductivity types “n” and “p” are interchanged.

As shown in FIG. 2, the p + type semiconductor region 5 (the boundary between the p + type semiconductor region 5 and the p − type semiconductor region (channel region) 4) is ideally rectangular and has a p − type semiconductor region (channel). It is desirable to form so that it protrudes to (region) 4. However, in reality, as shown in FIG. 1, in general, due to the manufacturing process (particularly, diffusion heat treatment), a comparatively gentle curved surface (broad profile) is usually obtained. Therefore, the conventional trench gate structure cell originally has a problem that it is difficult to control the distance between the p + -type semiconductor region 5 and the trench region 7. In addition, due to further progress in miniaturization in recent years, the absolute distance between adjacent trench regions 7 has become smaller and smaller, resulting in fluctuations in the processing accuracy and manufacturing process of trench regions 7 (non-ideality). There is a problem that the threshold voltage V _{th of the} cell is easily affected and varies.

Therefore, the relationship between the distance between u1 and p1 shown in FIG. 1 and the threshold voltage _{Vth of the} cell was investigated. FIG. 3 is a graph showing an example of the relationship between the distance between u1 and p1 in FIG. 1 and the threshold voltage _Vth in the conventional semiconductor device. As shown in FIG. 3, when the distance between u1 and p1 is 0.5 μm or more, the fluctuation of the threshold voltage V _th is small, while when it is less than 0.5 μm, the fluctuation of the threshold voltage V _th is large. . From this result, it was considered that the reason why the cell threshold voltage V _th varied was that the distance between u1 and p1 fluctuated across 0.5 μm.

Next, for the purpose of stabilizing the threshold voltage V _th , the profile of the p + type semiconductor region 5 is shallowed (the protrusion of the p + type semiconductor region 5 with respect to the p − type semiconductor region (channel region) 4 is reduced). However, since the electrical resistance between the trench regions 7 is increased, latch-up is caused, and there is a problem that the specified cutoff value of the cell (breakdown tolerance = breakdown current / rated current) cannot be secured.

  Therefore, the relationship between the distance between u1 and p1 shown in FIG. 1 and the cutoff resistance of the cell was investigated. FIG. 4 is a graph showing an example of the relationship between the distance between u1 and p1 in FIG. As shown in Fig. 4, it was found that when the distance between u1 and p1 is about 0.37μm or more, the withstand capability falls below "2". . This result means that it is necessary to control the electrical resistance between the trench regions 7 to a certain value or less (control the impurity concentration to a certain value or more).

  Next, in order to grasp the impurity concentration between the trench regions 7, the concentration distribution of the p-type impurity was investigated at a position along the a-a 'line between u1-u2 shown in FIG. FIG. 5 is a graph showing an example of the measurement result of the concentration distribution of p-type impurities in a conventional semiconductor device. The p-type impurity concentration is measured by SIMS (secondary ion mass spectrometry), and the boundary between the p + type semiconductor region 5 and the p− type semiconductor region (channel region) 4 is 1 from the concentration at the position of p1 or p2. It was defined as the position where the density was / 100.

As can be seen from FIG. 5, the concentration distribution of the p-type impurity in the conventional semiconductor device shows a typical concentration distribution suggesting a diffusion phenomenon in an isothermal field. Since the p + type semiconductor region 5 has a wider base, the p + type semiconductor region 5 tends to approach the trench region 7 (the distance between u1 and p1 tends to be small), and the cell threshold voltage _Vth increases. It was thought that it was scattered. In addition, since the impurity concentration at the bottom of the p + -type semiconductor region 5 is low, the electrical resistance between the trench regions 7 is likely to increase, and it was considered that the withstand voltage was reduced.

  Embodiments according to the present invention will be described below with reference to the drawings. However, the present invention is not limited to the embodiments taken up here, and may be modified as appropriate without departing from the scope of the invention. In addition, the same code | symbol is attached | subjected to a synonymous part in drawing, and the overlapping description is abbreviate | omitted. Although the case of a p-channel IGBT will be described, the same applies to an n-channel IGBT in which the conductivity types “n” and “p” are interchanged.

[First embodiment of the present invention]
(Structure of semiconductor device)
FIG. 6 is a schematic vertical sectional view showing an important part of an example of a semiconductor device according to the present invention. As shown in FIG. 6, the p-channel IGBT trench gate structure cell has an n + type semiconductor layer 2 and an n − type semiconductor layer (drift layer) 3 stacked on a p + type semiconductor substrate 1 to form an n − type semiconductor layer. A p − type semiconductor region (channel region) 4, an n + type semiconductor region (source region) 6, and a trench region 7 (gate insulating film 8 and gate electrode 9) are formed on (drift layer) 3, and these semiconductor laminates A metal wiring 12 is formed on the upper surface of 10 via an interlayer insulating film 11. A p + type semiconductor region 5 is interposed between two n + type semiconductor regions (source regions) 6 sandwiched between the two trench regions 7, and the p + type semiconductor region 5 is a p− type semiconductor region (channel region). It is formed so as to protrude in a rectangular shape from the two n + -type semiconductor regions (source regions) 6 toward 4.

  Furthermore, the concentration of the p-type impurity changes sharply in the region that forms the boundary between the p + -type semiconductor region 5 and the p − -type semiconductor region (channel region) 4, and the change rate of the concentration is 1/100 (or 100 times). The trench region 7 has a region whose distance in the width direction (lateral direction in the figure) is 0.1 μm or less. In other words, the region forming the boundary has a region where the concentration gradient of the p-type impurity is 200 dB / μm or more. The rectangular profile and steep impurity concentration gradient in the p + type semiconductor region 5 indicate that the semiconductor device according to the present invention achieves a structure closer to the ideal in the trench gate structure cell than in the past.

(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device according to the present invention will be described. Here, as a manufacturing process, an example of a procedure for forming an interlayer insulating film after forming a first conductive type semiconductor region between two second conductive type source regions will be described with reference to FIGS. The order of forming the trench regions may be before or after forming the first conductivity type channel region and the second conductivity type source region.

  FIG. 7 is a schematic diagram of a longitudinal section of the main part after the trench region (gate insulating film and gate electrode) formation step. A semiconductor stacked body 10 in which the trench region 7 (gate insulating film 8 and gate electrode 9) is formed is prepared. There is no particular limitation on the process until the trench region 7 is formed, and a conventional process can be used.

  FIG. 8 is a schematic vertical cross-sectional view showing the main part of an ion implantation process for forming a p − type semiconductor region (channel region). After forming a silicon oxide film to be an ion implantation through film 13 on the surface of the semiconductor laminate 10, a p-type impurity is formed on the entire surface of the n − type semiconductor layer (drift layer) 3 by ion implantation to form a channel region. (For example, boron: B) is introduced.

  FIG. 9 is a schematic cross-sectional view of the main part after the step of forming a p − type semiconductor region (channel region). In order to remove the ion implantation through film 12 formed on the surface of the semiconductor stacked body 10 and form a p-type semiconductor region (channel region) 4 having a desired impurity concentration distribution, diffusion heat treatment for the p-type impurity is performed. Apply.

  FIG. 10 is a schematic vertical cross-sectional view showing the main part of an ion implantation process for forming an n + type semiconductor region (source region). After masking the surface of the semiconductor stack 10 on which the p-type semiconductor region (channel region) 4 is formed using a photoresist 14, a p-type semiconductor region (channel region) is formed by ion implantation to form a source region. ) Selectively introduce n-type impurities (for example, arsenic: As) into 4.

  FIG. 11 is a schematic cross-sectional view of the main part after the n + -type semiconductor region (source region) formation step. In order to remove the photoresist 14 formed on the surface of the semiconductor stacked body 10 and form an n + -type semiconductor region (source region) 6 having a desired impurity concentration distribution, a diffusion heat treatment is performed on the n-type impurity.

  FIG. 12 is a schematic vertical cross-sectional view showing a main part of an ion implantation process for forming a p + type semiconductor region. After masking the surface of the semiconductor stacked body 10 on which the n + type semiconductor region (source region) 6 is formed using a photoresist 14, a first conductive type semiconductor region is provided between the two n + type semiconductor regions (source region) 6. To form a p-type impurity (for example, boron: B) by ion implantation. This photoresist 14 is also used as a mask for performing laser annealing as a diffusion heat treatment that is the next step, and therefore it is preferable to form the photoresist 14 so as to have a film thickness of 1.0 to 2.0 μm.

FIG. 13 is a schematic vertical cross-sectional view showing a laser annealing process for forming a p + -type semiconductor region. In order to form the p + -type semiconductor region 5 having a desired impurity concentration distribution, a laser annealing process is performed as a diffusion heat treatment for the p-type impurity. At this time, using the photoresist 14 formed in the previous step as a mask, a laser beam having a wavelength of 1.1 μm or less (for example, YLF laser, lithium yttrium fluoride (LiYF ₄ ) laser, the wavelength varies depending on the dopant and harmonics, but is generally 263 ˜1053 nm).

  In order to heat the silicon material by laser light irradiation, the laser light needs to be absorbed by the silicon material. For that purpose, it is necessary that the energy of the light is larger than the band gap energy (1.1 eV) of the silicon material, and light having a wavelength of 1127 nm or less is necessary in the calculation.

  In addition, the irradiated light is considered to be absorbed with a certain penetration depth, but in particular, the light having a wavelength of about 1.0 to 1.1 μm is considered to have a relatively long penetration length. That is, it is considered that only the irradiated region (region having a certain depth) can be heated extremely locally. In other words, the laser annealing treatment in the present invention has an effect that only the region where ion implantation for forming the p + -type semiconductor region 5 is performed can be heated to perform a diffusion heat treatment. This is very different from diffusion heat treatment in the conventional isothermal field, and the diffusion region (heated region) is extremely limited, thereby forming a rectangular profile of the p + type semiconductor region 5 and a steep impurity concentration gradient in the boundary region. It is thought that it contributes to.

  After the laser annealing process, the photoresist 14 formed on the surface of the semiconductor laminate 10 is removed, and the interlayer insulating film 11 and the metal wiring 12 are formed to have the cross-sectional structure as shown in FIG. The device is completed.

  In order to confirm the effect of the present invention, the concentration distribution of the p-type impurity was investigated at the same position as the conventional semiconductor device. FIG. 14 is a graph showing an example of the measurement result of the concentration distribution of the p-type impurity in the semiconductor device according to the present invention. The result of FIG. 5 is also shown in the figure. As can be seen from FIG. 14, the semiconductor device according to the present invention has a rectangular concentration profile. In addition, in the region that forms the boundary between the p + type semiconductor region 5 and the p − type semiconductor region (channel region) 4, the concentration of the p-type impurity changes sharply, and the change rate of the concentration is 1/100 (or 100 times). It was confirmed that the distance is 0.1 μm or less.

Further, when the threshold voltage V _th and the cutoff withstand voltage of the semiconductor device according to the present invention were investigated, the variation in the threshold voltage V _th for each cell was suppressed, and the desired cutoff withstand voltage was secured. That is, the semiconductor device according to the present invention can cope with further miniaturization of the unit cell, and can be said to be a semiconductor device effective for high efficiency (low loss).

[Second Embodiment of the Present Invention]
(Method for manufacturing semiconductor device)
Next, a method for manufacturing a semiconductor device according to the second embodiment will be described. Here, as a manufacturing process, an example of a procedure for forming the first conductive type semiconductor region after forming the interlayer insulating film will be described with reference to FIGS. The description of the same parts as those in the first embodiment is omitted.

  FIG. 15 is a schematic diagram of a longitudinal section of the main part after the interlayer insulating film forming step. An interlayer insulating film 15 is formed on the surface of the semiconductor stacked body 10 on which the n + type semiconductor region (source region) 6 is formed. This interlayer insulating film 15 is preferably formed so as to have a film thickness of 2.0 to 3.0 μm because it is used as a mask in the subsequent laser annealing treatment step.

  FIG. 16 is a schematic diagram of a main part longitudinal cross section showing an etching process of an interlayer insulating film. In order to selectively process the interlayer insulating film 15, a photoresist 16 is formed, and then the interlayer insulating film 15 is processed by wet etching or dry etching. Thereafter, the photoresist 16 is removed.

  FIG. 17 is a schematic diagram of a main part longitudinal section showing an ion implantation process for forming a p + -type semiconductor region. In order to form a first conductivity type semiconductor region between two n + type semiconductor regions (source regions) 6, a p-type impurity (for example, boron: B) is selectively introduced by ion implantation.

  FIG. 18 is a schematic vertical cross-sectional view showing a laser annealing process for forming a p + type semiconductor region. Similarly to the first embodiment, in order to form the p + -type semiconductor region 5 having a desired impurity concentration distribution, a laser annealing process is performed as a diffusion heat treatment for the p-type impurity.

  FIG. 19 is a schematic diagram of a main part longitudinal section after the interlayer insulating film shaping step. In order to remove the surface damage layer of the interlayer insulating film 15 and shape it into a required shape (interlayer insulating film 11), the interlayer insulating film is etched back by wet etching.

  Thereafter, the metal wiring 12 is formed to complete the semiconductor device according to the present invention having the cross-sectional structure as shown in FIG.

1 ... p + type semiconductor substrate, 2 ... n + type semiconductor layer, 3 ... n- type semiconductor layer (drift layer),
4 ... p-type semiconductor region (channel region), 5 ... p + type semiconductor region,
6 ... n + type semiconductor region (source region), 7 ... trench region,
8 ... Gate insulating film, 9 ... Gate electrode, 10 ... Semiconductor laminate, 11 ... Interlayer insulating film,
12 ... metal wiring, 13 ... through film for ion implantation, 14 ... photoresist, 15 ... interlayer insulating film.

Claims (1)

A method for manufacturing a semiconductor device including a MOS transistor having a trench gate structure,
The transistor has a first conductivity type channel region formed between adjacent trench regions, two second conductivity type source regions, and a first conductivity type semiconductor region formed between the two second conductivity type source regions. And
The first conductivity type semiconductor region has a first conductivity type to the first conductivity type channel region so as to protrude in a rectangular shape from the two second conductivity type source regions toward the first conductivity type channel region. It is formed by impurity ion implantation and diffusion heat treatment,
In the region forming the boundary between the first conductivity type semiconductor region and the first conductivity type channel region, the region in which the concentration gradient of the first conductivity type impurity in the width direction of the trench region is 200 dB / μm or more. Have
The method of manufacturing a semiconductor device, wherein the diffusion heat treatment for forming the first conductivity type semiconductor region is a laser annealing treatment using a laser beam having a wavelength of 1.1 μm or less.

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