JP2017107939A - Semiconductor device and semiconductor device manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device and a semiconductor device manufacturing method which can inhibit deterioration in withstand voltage, which is caused by a difference between a first distance and a second distance.SOLUTION: A semiconductor device 10 comprises a semiconductor substrate 12 where a cell area A1 and a termination area A2 are zoned. The cell area A1 has a p-type first body layer 25a, a first trench 21, a gate electrode 31 stored in the first trench 21 and a p-type first floating region 36 provided at a lower position of the first trench 21. The termination area A2 has a p-type second body layer 25b, a second trench 22 and a second floating region 42 provided at a lower position of the second trench 22. A depth D2 of the second body layer 25b is set deeper than a depth D1 of the first body layer 25a so as to equalize a first distance Z1 with a second distance Z2.SELECTED DRAWING: Figure 3

Description

  The present invention relates to a semiconductor device and a method for manufacturing the semiconductor device.

  As a semiconductor device, for example, a semiconductor device including a semiconductor substrate in which a cell area and a termination area are partitioned (see, for example, Patent Document 1). The semiconductor substrate has, for example, a drift layer and a body layer formed on the drift layer. And in patent document 1, the 1st trench in which the gate electrode was accommodated in the cell area, and the 1st floating region arrange | positioned in the downward position of a 1st trench so that the bottom part of a 1st trench might be covered are formed. It is described that the first floating region can achieve both improvement in breakdown voltage and reduction in on-resistance.

  Further, in Patent Document 1, an annular second trench surrounding the cell area and a second floating region disposed below the second trench so as to cover the bottom of the second trench are formed in the termination area. It describes that the second floating region can increase the breakdown voltage while suppressing the expansion of the termination area.

JP 2007-173319 A

  Here, in order to reduce the on-resistance, the bottom surface of the gate electrode protrudes below the interface between the drift layer and the body layer disposed in the cell area. In this case, the distance between the bottom surface of the gate electrode in the vertical direction and the upper end of the first floating region is defined as the first distance, and the vertical distance between the upper end of the second floating region corresponding to the innermost second trench and the body layer is increased. When the distance is the second distance, the inventors of the present application have found that the breakdown voltage of the semiconductor device decreases due to the difference between the first distance and the second distance.

  The present invention has been made in view of the above-described circumstances, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress a decrease in breakdown voltage caused by the difference between the first distance and the second distance. That is.

  A semiconductor device that achieves the above object includes a semiconductor substrate in which a cell area in which a plurality of cells are arranged and a termination area surrounding the cell area are partitioned, and the cell area has a first conductivity type first. A first drift layer; a first body layer of a second conductivity type formed on the first drift layer; a first trench penetrating the first body layer and reaching the first drift layer; A gate electrode accommodated in the first trench and opposed to the first body layer via an insulating film, and provided to cover a bottom portion of the first trench at a position below the first trench. A first floating region of the second conductivity type, and the termination area includes a second drift layer of the first conductivity type and a second conductivity type second formed on the second drift layer. Surround the body layer and the cell area A second trench extending through the second body layer and reaching the second drift layer, and a bottom portion of the second trench at a position below the second trench. And a bottom surface of the gate electrode protrudes below an interface between the first body layer and the first drift layer, and the second trench and One or a plurality of the second floating regions are provided, and a distance between an upper end of the first floating region and a bottom surface of the gate electrode in a vertical direction is a first distance, and the one or more second trenches are formed. Of the innermost peripheral second trenches, the vertical distance between the upper end of the second floating region corresponding to the innermost peripheral second trench in the innermost periphery and the second body layer is the second distance. The depth of the second body layer of circumference, said as the first distance and the second distance is equal, characterized in that it is set deeper than the depth of the first body layer.

  According to this configuration, since the depth of the second body layer is set deeper than the depth of the first body layer so that the first distance and the second distance are the same, the cell area and the termination area Thus, the electric field strength distribution can be made uniform, and the breakdown voltage can be improved through the distribution.

  In the semiconductor device, the first floating region may be surrounded by the first drift layer, and the one or more second floating regions may be surrounded by the second drift layer. According to such a configuration, a floating region having a desired shape can be realized relatively easily.

  In the semiconductor device, the first floating region and the one or more second floating regions may reach a diffusion layer formed under both drift layers. According to such a configuration, the breakdown voltage can be further improved.

  A method of manufacturing a semiconductor device that achieves the above object includes a first conductivity type drift layer and a second conductivity type body layer formed on the drift layer, and a plurality of cells are arranged. A method of manufacturing a semiconductor device including a semiconductor substrate in which a cell area and a termination area surrounding the cell area are partitioned, by performing etching so as to penetrate the body layer and reach the drift layer A trench forming step of forming a first trench disposed in the cell area and an annular second trench disposed in the termination area; and a second step from a bottom of the first trench and the second trench. By implanting conductivity type impurity ions, a second conductivity type first floating region covering the bottom of the first trench and a second conductor covering the bottom of the second trench. A floating region forming step of forming a second floating region of the mold, and implanting impurity ions of the first conductivity type near the interface between the drift layer and the body layer from the surface of the cell area in the semiconductor substrate, Depth adjustment to make the depth of the first body layer, which is the body layer, disposed in the cell area shallower than the depth of the second body layer, which is the body layer, is disposed in the termination area And a gate electrode forming step of forming a gate electrode in the first trench, wherein in the gate electrode forming step, the bottom surface of the gate electrode protrudes from the lower surface of the first body layer. A gate electrode is formed, and in the trench formation step, one or a plurality of the second trenches are formed, and the top of the first floating region in the vertical direction is formed. The first distance is the distance between the gate electrode and the bottom surface of the gate electrode, and the upper end of the second floating region corresponding to the innermost second trench in the innermost circumference of the one or more second trenches, and the When the vertical distance from the second body layer is the second distance, in the depth adjustment step, the depth of the first body layer is set so that the first distance and the second distance are the same. The depth is smaller than the depth of the second body layer.

  According to such a configuration, the depths of both body layers can be made different by a relatively simple process, and the first distance and the second distance can be made the same through this. Therefore, it is possible to suppress a decrease in breakdown voltage due to the difference between the first distance and the second distance in a relatively simple process.

  According to this invention, it is possible to suppress a decrease in breakdown voltage due to the difference between the first distance and the second distance.

The top view which shows a semiconductor device typically. FIG. 2 is a sectional view taken along line 2-2 in FIG. 1. The enlarged view of FIG. (A)-(d) Sectional drawing which shows the manufacturing method of a semiconductor device typically. (A)-(c) Sectional drawing which shows the manufacturing method of a semiconductor device typically. Sectional drawing which shows the floating area | region of another example typically. (A), (b) Sectional drawing which shows typically the manufacturing method of the body layer of another example.

  Hereinafter, an embodiment of a semiconductor device will be described. For convenience of illustration, FIGS. 1 to 5 show dimensions different from the actual dimensions. In FIG. 1, illustration of the termination-side insulating film 41 and the surface electrode 51 is omitted, and the trenches 21 and 22 are simplified.

  As shown in FIG. 1, the semiconductor device 10 includes a semiconductor substrate 12 in which a cell area A1 in which a plurality of cells 11 are arranged and a termination area A2 surrounding the cell area A1 are partitioned. In the present embodiment, the plurality of cells 11 include, for example, trench type MOSFETs using Si (silicon).

  The semiconductor substrate 12 has, for example, a rectangular plate shape. The cell area A1 is a rectangular area smaller than the semiconductor substrate 12, and the terminal area A2 is a frame-shaped area surrounding the cell area A1.

  A plurality of first trenches 21 are formed in the cell area A1. Each first trench 21 extends in one direction. The plurality of first trenches 21 are arranged at a predetermined pitch in a direction orthogonal to the extending direction of the first trenches 21. Each first trench 21 has the same shape.

  A plurality of (three in this embodiment) second trenches 22 are formed in the termination area A2. Each second trench 22 is formed in an annular shape surrounding the cell area A1. Each second trench 22 has a rounded rectangular shape in plan view. The plurality of second trenches 22 have similar shapes with different sizes in plan view, and the second trenches 22 are arranged on the same center. That is, the cell area A1 is surrounded by the multiple second trenches 22.

  In this case, among the plurality of second trenches 22, the one having the smallest size in plan view is arranged on the innermost periphery of the termination area A <b> 2. The second trench 22 disposed on the innermost periphery is defined as the innermost peripheral second trench 22i. It can be said that the innermost second trench 22i is the second trench 22 closest to the cell area A1 (in other words, the cell 11).

Next, a cross-sectional structure of the semiconductor device 10 will be described.
As shown in FIGS. 2 and 3, the semiconductor substrate 12 is formed on the n ⁺ -type drain layer 23 as a diffusion layer, the drift layer 24 formed on the drain layer 23, and the drift layer 24. And a p-type body layer 25. That is, the semiconductor substrate 12 has a structure in which the drain layer 23 → the drift layer 24 → the body layer 25 are stacked in this order. The drift layer 24 is n-type lower than the impurity concentration of the drain layer 23. In other words, the drain layer 23 is a layer formed under the drift layer 24 and having a higher impurity concentration than the drift layer 24.

  Needless to say, the layering direction of the layers 23 to 25 is not limited to the vertical direction. Further, upper (or upper) and lower (or lower) are used for the sake of convenience to show the relative relationship to the last, and are not limited to the upper direction in the vertical direction and the lower direction in the vertical direction. The same applies to the following description.

  Here, for convenience of explanation, the drift layer 24 and the body layer 25 disposed in the cell area A1 are referred to as a first drift layer 24a and a first body layer 25a, and the drift layer 24 and the body layer 25a disposed in the termination area A2 The body layer 25 is a second drift layer 24b and a second body layer 25b.

  Next, the cross-sectional structure of the cell area A1 will be described. The first trench 21 extends downward from the cell area surface 12a, which is the surface of the cell area A1 in the semiconductor substrate 12, and penetrates the first body layer 25a. In addition, it reaches the first drift layer 24a. The cell area surface 12a can also be said to be the upper surface of the first body layer 25a.

  As shown in FIG. 3, a gate electrode 31 and a buried insulating film 32 are provided in the first trench 21. The buried insulating film 32 has a deposited insulating film 32 a deposited in the first trench 21 and a gate insulating film 32 b formed on the side wall of the first trench 21. The gate electrode 31 is accommodated in the first trench 21 in a state surrounded by the buried insulating film 32, and faces the first body layer 25a via the gate insulating film 32b.

  The bottom surface 31a of the gate electrode 31 protrudes below the interface 26a between the first body layer 25a and the first drift layer 24a (in other words, the lower surface of the first body layer 25a). That is, the gate electrode 31 is disposed so as to face both the first body layer 25a and the first drift layer 24a with the gate insulating film 32b interposed therebetween.

  Further, the thickness (depth) of the buried insulating film 32 between the bottom portion 21a of the first trench 21 and the bottom surface 31a of the gate electrode 31, that is, the thickness of the deposited insulating film 32a is sufficiently larger than the thickness of the gate insulating film 32b. For example, it is set thicker than the length of the gate electrode 31 in the vertical direction. Accordingly, a sufficient distance can be secured between the bottom surface 31a of the gate electrode 31 and a first floating region 36 described later.

  An interlayer insulating film 33 is formed above the buried insulating film 32. The interlayer insulating film 33 covers the upper surface of the buried insulating film 32 and the peripheral portion of the first trench 21 on the cell area surface 12a.

  In the present embodiment, the upper surface of the gate electrode 31 is located slightly below the cell area surface 12a and is covered with the buried insulating film 32, but is not limited thereto. For example, the upper surface of the gate electrode 31 may be aligned with the cell area surface 12a. In this case, the upper surface of the gate electrode 31 is covered with the interlayer insulating film 33. Further, specific materials for the buried insulating film 32 and the interlayer insulating film 33 are arbitrary, but for example, a silicon oxide film or the like can be considered.

2 and 3, the first body layer 25a inside the first outermost trench 21 has an n ⁺ -type source region 34 having a higher impurity concentration than the first drift layer 24a, and a first A p ⁺ type body contact region 35 having an impurity concentration higher than that of the body layer 25a is formed. The source region 34 and the body contact region 35 are exposed on the cell area surface 12a. The source region 34 is provided on the periphery of each first trench 21 inside the first outermost trench 21 and constitutes a part of the side wall of each first trench 21. The body contact region 35 is provided at a position adjacent to the source region 34 and is joined to the source region 34.

  The outermost first trenches 21 are first trenches 21 provided at both ends in the arrangement direction of the first trenches 21 among the plurality of first trenches 21 arranged at a predetermined pitch. In other words, the outermost first trench 21 is the first trench provided at a position closest to the innermost second trench 22 i in the arrangement direction of the first trench 21 among the plurality of first trenches 21. 21. The source region 34 is not formed on the periphery of the outermost first trench 21, and there is no body between the outermost first trench 21 and the termination area A 2 (in other words, the innermost second trench 22 i). The contact region 35 is not formed. For this reason, the outermost peripheral cell 11 does not function as a switching element.

  A p-type first floating region 36 is formed below the first trench 21 in the first drift layer 24a. The first floating region 36 extends along the first trench 21. The first floating region 36 of the present embodiment has, for example, an oval cross section orthogonal to the extending direction, and is surrounded by the first drift layer 24a. The first floating region 36 covers the bottom 21 a of the first trench 21 and a part of the side wall of the first trench 21 on the bottom 21 a side. For this reason, the boundary portion between the first floating region 36 and the first trench 21 is U-shaped when viewed from the extending direction of the first trench 21. In addition, as viewed from the vertical direction, a part of the first floating region 36 protrudes in the width direction (in other words, the arrangement direction of the first trenches 21) from the first trench 21. The first body layer 25a is opposed to the up and down direction via the first drift layer 24a. That is, the first floating region 36 and the first body layer 25a are separated. Further, the first floating region 36 and the drain layer 23 are separated from each other, and the first drift layer 24a is interposed therebetween.

  According to such a configuration, the portion where the electric field concentrates is dispersed in the vicinity of the bottom surface 31 a of the gate electrode 31 and the first floating region 36. For this reason, the peak of the electric field is relaxed as compared with the configuration in which the first floating region 36 is not provided, that is, the configuration in which the electric field is concentrated only in the vicinity of the bottom surface 31a of the gate electrode 31, so that the breakdown voltage can be improved.

  Next, the sectional structure of the termination area A2 will be described. As shown in FIGS. 2 and 3, the second trench 22 extends downward from the termination area surface 12b, which is the surface of the termination area A2 in the semiconductor substrate 12. And penetrates through the second body layer 25b and reaches the second drift layer 24b. The termination area surface 12b can also be said to be the upper surface of the second body layer 25b.

  In the present embodiment, a plurality of second trenches 22 are provided, but the depth and width of each second trench 22 are set to be the same. The depths of the first trench 21 and the second trench 22 are also set to be the same.

  A termination-side insulating film 41 is formed in the termination area A2. The termination-side insulating film 41 covers the termination area surface 12 b while being buried in the second trench 22. Incidentally, the outermost interlayer insulating film 33 provided above the outermost first trench 21 protrudes to the termination area A2 side and is continuous with the termination side insulating film 41.

  A p-type second floating region 42 is formed at a position below the second trench 22 in the second drift layer 24b. The second floating region 42 has an annular shape that surrounds the cell area A1 when viewed in the vertical direction. The second floating region 42 of the present embodiment has an oval cross section, for example, and is surrounded by the second drift layer 24b. The second floating region 42 covers the bottom 22 a of the second trench 22 and a part of the side wall of the second trench 22 on the bottom 22 a side. For this reason, the boundary portion between the second floating region 42 and the second trench 22 is U-shaped when viewed from the extending direction of the second trench 22. Further, when viewed from above and below, a part of the second floating region 42 protrudes in the width direction from the second trench 22, and the protruding part and the second body layer 25b define the second drift layer 24b. Via the top and bottom. That is, the second floating region 42 and the second body layer 25b are separated.

  Incidentally, since the first trench 21 and the second trench 22 have the same depth, the first floating region 36 and the second floating region 42 are provided at the same depth position in the drift layer 24. . Therefore, as shown in FIG. 3, the upper end 36a of the first floating region 36 and the upper end 42a of the second floating region 42 are arranged at the same depth position.

  Here, the distance between the bottom surface 31a of the gate electrode 31 and the upper end 36a of the first floating region 36 in the vertical direction is defined as a first distance Z1. Further, the second floating region 42 corresponding to the innermost peripheral second trench 22i, more specifically, the second floating region 42 provided at a position below the innermost peripheral second trench 22i, the innermost peripheral second floating region 42i. And A distance between the upper end 42a of the innermost peripheral second floating region 42i and the second body layer 25b in the vertical direction is defined as a second distance Z2.

  In such a configuration, the depth D2 of the second body layer 25b is set deeper than the depth D1 of the first body layer 25a so that the first distance Z1 and the second distance Z2 are the same. Specifically, the depth D2 of the second body layer 25b is set to be equal to the protrusion dimension Zt of the bottom surface 31a of the gate electrode 31 with respect to the interface 26a between the first body layer 25a and the first drift layer 24a. It is set deeper than the depth D1. In the present embodiment, the depth D2 of the second body layer 25b is constant.

  Note that the fact that the first distance Z1 and the second distance Z2 are the same is not limited to a completely identical configuration, and a certain amount of error (for example, ± 5% or less) is allowed. In other words, the depth D2 of the second body layer 25b is set deeper than the depth D1 of the first body layer 25a so that the second distance Z2 approaches (preferably matches) the first distance Z1. It can be said that there is.

  Incidentally, the upper end 36a of the first floating region 36 is a portion that is closest to the first body layer 25a. For example, the first floating region 36 and the first trench 21 (in other words, the buried insulating film 32) This is the upper end of the boundary portion on the end area A2 side. The upper end 36a of the first floating region 36 can also be said to be the upper end portion of the portion of the first floating region 36 that protrudes from the first trench 21 toward the termination area A2 when viewed from the up-down direction.

  Similarly, the upper end 42a of the innermost peripheral second floating region 42i is a portion closest to the second body layer 25b. For example, the innermost peripheral second floating region 42i and the second trench 22 (in other words, the terminal end) This is the upper end portion on the cell area A1 side in the boundary portion with the side insulating film 41). Further, the upper end 42a of the innermost peripheral second floating region 42i is a portion of the innermost peripheral second floating region 42i that protrudes from the innermost peripheral second trench 22i toward the cell area A1 when viewed in the vertical direction. It can also be said to be the upper end.

  The depths D1 and D2 of the body layers 25a and 25b can be said to be the thicknesses of the body layers 25a and 25b. Further, the vertical direction can be said to be the thickness direction of the semiconductor substrate 12 or the stacking direction of the layers 23 to 25.

  Here, since the depth D1 of the first body layer 25a and the depth D2 of the second body layer 25b are different, as shown in FIG. 3, the interface between the first drift layer 24a and the first body layer 25a. A step surface 50 is formed between 26a and the interface 26b between the second drift layer 24b and the second body layer 25b. The step surface 50 is a curved surface that is convex from the cell area A1 toward the terminal area A2. The step surface 50 is formed by a depth adjustment process in which both depths D1 and D2 are made different by selectively implanting n-type impurity ions into the body layer 25 having a uniform depth later. The depth adjustment step will be described later.

  As shown in FIGS. 2 and 3, the semiconductor device 10 includes a surface electrode 51. The surface electrode 51 covers the entire surface of the semiconductor substrate 12 while being bonded to the source region 34 and the body contact region 35. Although not shown, the semiconductor device 10 includes a back electrode provided below the drain layer 23 and joined to the drain layer 23.

  Incidentally, the semiconductor device 10 of this embodiment is mounted on a vehicle, for example, and is used to drive a motor mounted on the vehicle. In detail, for example, the semiconductor device 10 is electrically connected to a DC power source mounted on the vehicle and is also electrically connected to a coil of the motor, and direct current power supplied from the DC power source is converted by the motor. It is used as an inverter that converts AC power that can be driven.

Next, the operation of this embodiment will be described.
When a voltage is applied between the drain layer 23 and the source region 34, the electric field concentrates on the vicinity of the bottom surface 31a of the gate electrode 31 and the first floating region 36 in the cell area A1, while the termination area A2 Inside, the electric field concentrates on the interface 26 b between the second drift layer 24 b and the second body layer 25 b and the second floating region 42.

  Here, in this embodiment, since the depth D1 of the first body layer 25a and the depth D2 of the second body layer 25b are different, the distance between the two locations where the electric field concentrates in the cell area A1. The one distance Z1 is the same as the second distance Z2, which is the distance between two locations where the electric field concentrates in the termination area A2. For this reason, the breakdown voltage of the semiconductor device 10 is high.

  As a factor that the breakdown voltage is improved when the first distance Z1 and the second distance Z2 are the same, the electric field strength distribution is matched between the cell area A1 and the termination area A2.

Next, a method for manufacturing the semiconductor device 10 will be described with reference to FIGS.
First, as shown in FIG. 4A, an n-type layer is epitaxially grown on an n ⁺ -type bulk substrate constituting the drain layer 23, and ion implantation is performed on the epitaxial layer. The body layer 25 is formed.

  Thereafter, as shown in FIG. 4B, a trench mask 61 of silicon oxide film is formed, and etching is performed so as to penetrate the body layer 25 and reach the drift layer 24 with the trench mask 61 formed. By performing, the trench formation process which forms the some 1st trench 21 and the some 2nd trench 22 is performed.

  Then, as shown in FIG. 4C, p-type impurity ions are implanted and diffused into the bottom portions 21a and 22a of both trenches 21 and 22 in a state where the trench mask 61 is formed, thereby causing the first floating. A floating region forming step for forming the region 36 and the second floating region 42 is performed.

  Subsequently, as shown in FIG. 4D, an insulating film 62 that covers both the cell area surface 12a and the termination area surface 12b while filling the first trench 21 and the second trench 22 is formed. Thereafter, as shown by a two-dot chain line in FIG. 4D, pattern etching is performed to remove the insulating film 62 formed on the cell area surface 12a while leaving the insulating film 62 formed on the termination area surface 12b. Thus, the cell area surface 12a is exposed. In this case, a space is formed in the first trench 21 by removing a part of the insulating film 62 in the first trench 21 in conjunction with removing the insulating film 62 on the cell area surface 12a. The insulating film 62 formed in the termination area surface 12b and the second trench 22 corresponds to the termination-side insulating film 41, and the insulating film 62 remaining in the first trench 21 corresponds to the deposited insulating film 32a. To do.

  Thereafter, as shown in FIG. 5A, a depth adjusting step is performed in which n-type impurity ions are implanted and diffused from the cell area surface 12a toward the vicinity of the interface 26 between the drift layer 24 and the body layer 25. To do. In this case, the acceleration energy and the like of the impurity ions are adjusted so that the impurity ions are selectively implanted near the interface 26 between the drift layer 24 and the body layer 25 in the cell area A1. Accordingly, as shown in FIG. 5B, the depth D1 of the first body layer 25a, which is the body layer 25 disposed in the cell area A1, is the body layer 25 disposed in the termination area A2. The depth D2 of the second body layer 25b is shallower and the step surface 50 is formed.

  Incidentally, in the depth adjustment step, the depth of the first body layer 25a is set so as to correspond to the protruding dimension Zt of the gate electrode 31 to be formed later so that the first distance Z1 and the second distance Z2 are the same. The depth D1 is made shallower than the depth D2 of the second body layer 25b.

  Since the termination-side insulating film 41 exists on the termination area surface 12b and the deposited insulating film 32a exists in the first trench 21, n-type impurity ions are not present in the termination area A2 and the first floating region 36. Not injected.

  Subsequently, as illustrated in FIG. 5B, the gate electrode 31 and the gate insulating film 32 b are formed in the space above the deposited insulating film 32 a in the first trench 21. Although a specific method of this step is arbitrary, for example, a gate insulating film 32b is formed on the side wall of the first trench 21 by heat treatment or the like, and then the gate electrode 31 (for example, polysilicon or the like) is formed using a CVD method or the like. A method for growing the plant can be considered.

  In the step of forming the gate electrode 31, the gate electrode 31 is formed so that the bottom surface 31 a of the gate electrode 31 protrudes downward from the interface 26 a between the first drift layer 24 a and the first body layer 25 a by the protruding dimension Zt.

  Thereafter, as shown in FIG. 5C, a source region 34, a body contact region 35, and an interlayer insulating film 33 are formed. Thereby, the cell 11 is formed. Thereafter, the front electrode 51 and the back electrode are formed.

According to the embodiment described above in detail, the following effects are obtained.
(1) The semiconductor device 10 includes a semiconductor substrate 12 in which a cell area A1 in which a plurality of cells 11 are arranged and a termination area A2 surrounding the cell area A1 are partitioned. The cell area A1 includes an n-type first drift layer 24a, a p-type first body layer 25a formed on the first drift layer 24a, the first body layer 25a, and the first drift layer 24a. And the first trench 21 reaching up to. The cell area A1 is accommodated in the first trench 21 and is located below the first trench 21 with the gate electrode 31 facing the first body layer 25a via the buried insulating film 32. And a p-type first floating region 36 provided so as to cover the bottom 21 a of the first trench 21.

  The termination area A2 includes an n-type second drift layer 24b and a p-type second body layer 25b formed on the second drift layer 24b. In addition, the termination area A2 is formed in an annular shape surrounding the cell area A1, and passes through the second body layer 25b and reaches the second drift layer 24b, and at a position below the second trench 22. And a p-type second floating region 42 provided so as to cover the bottom portion 22a of the second trench 22. A plurality of second trenches 22 and second floating regions 42 are provided so as to surround the cell area A1.

  In this configuration, the bottom surface 31a of the gate electrode 31 protrudes below the interface 26a between the first body layer 25a and the first drift layer 24a. As a result, part of the gate electrode 31 faces the first drift layer 24a via the buried insulating film 32, so that the cell 11 (MOSFET in this embodiment) operates normally and has an on-resistance. Reduction can be achieved.

  The depth D2 of the second body layer 25b around the innermost second trench 22i is greater than the depth D1 of the first body layer 25a so that the first distance Z1 and the second distance Z2 are the same. Is also deeply set. Specifically, the depth D2 of the second body layer 25b is the same as that of the first body layer 25a by the protruding dimension Zt of the bottom surface 31a of the gate electrode 31 from the interface 26a between the first body layer 25a and the first drift layer 24a. It is set deeper than the depth D1. Thereby, the fall of the pressure | voltage resistance resulting from the 1st distance Z1 and the 2nd distance Z2 differing can be suppressed. Therefore, reduction in on-resistance and improvement in breakdown voltage can be achieved.

  (2) The first floating region 36 and the second floating region 42 are surrounded by the drift layer 24. According to this configuration, since both floating regions 36 and 42 are shallower than the configuration in which both floating regions 36 and 42 reach the drain layer 23, both floating regions 36 and 42 having a desired shape are formed. Can be formed relatively easily.

  More specifically, when the deep floating regions 36 and 42 are formed, the time required for the formation tends to be long. On the other hand, in the present embodiment, since both the floating regions 36 and 42 need only be relatively shallow, the above disadvantages can be suppressed, and the floating regions 36 and 42 having a desired shape can be made relatively easy. Can get to.

  (3) The depth of the first trench 21 and the depth of the second trench 22 are set to be the same. Thereby, the 1st floating area | region 36 and the 2nd floating area | region 42 are easy to be arrange | positioned in the same depth position. In this case, the first distance Z1 and the second distance Z2 can be made the same by making the depth D1 of the first body layer 25a different from the depth D2 of the second body layer 25b. Thereby, the effect of (1) can be obtained without making the depths of both trenches 21 and 22 (in other words, the depth positions of both floating regions 36 and 42) different.

  (4) The semiconductor substrate 12 includes an n-type drift layer 24 and a p-type body layer 25 formed on the drift layer 24. The manufacturing method of the semiconductor device 10 including the semiconductor substrate 12 includes a first trench 21 disposed in the cell area A1 by performing etching so as to penetrate the body layer 25 and reach the drift layer 24, and And a trench forming step of forming a plurality of second trenches 22 arranged in the termination area A2. In addition, the method for manufacturing the semiconductor device 10 includes a floating region forming step in which both floating regions 36 and 42 are formed by implanting p-type impurity ions from the bottoms 21a and 22a of both trenches 21 and 22.

  In such a configuration, the manufacturing method of the semiconductor device 10 includes the first body layer in the cell area A1 by implanting n-type impurity ions from the cell area surface 12a to the vicinity of the interface 26 between the drift layer 24 and the body layer 25. There is a depth adjusting step for making the depth D1 of 25a shallower than the depth D2 of the second body layer 25b in the termination area A2. The manufacturing method of the semiconductor device 10 includes a step of forming the gate electrode 31 so that the bottom surface 31a of the gate electrode 31 protrudes from the lower surface of the first body layer 25a. In the depth adjustment step, the first distance Z1 is provided. And the second distance Z2 are made equal to each other so that the depth D1 of the first body layer 25a is shallower than the depth D2 of the second body layer 25b so as to correspond to the protrusion of the gate electrode 31. Thereby, the depths D1 and D2 of both the body layers 25a and 25b can be made different, and the first distance Z1 and the second distance Z2 can be made the same through this.

  Further, in the configuration in which the step of forming the first body layer 25a and the step of forming the second body layer 25b are performed separately, it is necessary to perform deep ion implantation and diffusion treatment twice to ensure a predetermined film thickness. Therefore, there is a concern that the process becomes complicated. On the other hand, in the present embodiment, the deep ion implantation and diffusion process are performed only once, so that the process can be simplified.

  (5) The manufacturing method of the semiconductor device 10 includes a step of forming the insulating film 62 covering both the cell area surface 12a and the termination area surface 12b while filling both the trenches 21 and 22 after the floating region forming step. . The method for manufacturing the semiconductor device 10 exposes the cell area surface 12a by etching the insulating film 62 formed on the cell area surface 12a while leaving the insulating film 62 formed on the termination area surface 12b. A step of removing a part of the insulating film 62 in the first trench 21 to form a space for the gate electrode 31 in the first trench 21 is provided. And a depth adjustment process is performed after the said process. As a result, the n-type impurity ions can be prevented from being implanted into the termination area A2 and the first floating region 36, and the n-type impurity ions can be selectively implanted into the interface 26 in the cell area A1. Therefore, since it is not necessary to prepare a dedicated mask, the process can be further simplified.

In addition, you may change the said embodiment as follows.
As shown in FIG. 6, the first floating region 71 may extend downward from the bottom 21 a of the first trench 21 and reach the drain layer 23. In this case, the breakdown voltage can be further improved. The second floating region 72 may extend downward from the bottom 22 a of the second trench 22 and reach the drain layer 23.

  The number of the second trenches 22 is arbitrary, and may be two, for example, four or more. The number of second trenches 22 may be one. When the number of the second trenches 22 is one, the one second trench 22 is the innermost peripheral second trench 22i.

  O Although the depth D2 of the 2nd body layer 25b was fixed, it is not restricted to this, You may differ according to a place. For example, the depth of the portion around the innermost second trench 22 i in the second body layer 25 b (specifically, the portion facing the innermost second floating region 42 i when viewed in the vertical direction) and other portions. May be different. Specifically, only the peripheral portion may be deeper than the depth D1 of the first body layer 25a, and other portions may be the same as the depth D1 of the first body layer 25a.

  The manufacturing method of the semiconductor device 10 is not limited to that of the embodiment, and may be arbitrary as long as the structure can be realized. For example, as shown in FIG. 7A, the second body layer is formed by first implanting and diffusing p-type impurity ions only in the termination area A2 while masking the cell area A1 using a dedicated mask. 25b is formed. At this stage, the first body layer 25a is not formed in the cell area A1. Thereafter, as shown in FIG. 7B, the first body layer 25a is formed by implanting and diffusing p-type impurity ions only in the cell area A1, while masking the termination area A2 using a mask. To do. In this case, conditions such as acceleration energy applied to impurity ions may be adjusted so that the depth D1 of the first body layer 25a is shallower than the depth D2 of the second body layer 25b. Thereafter, both trenches 21 and 22 are preferably formed. When both the body layers 25a and 25b are formed as described above, the stepped surface 80 gradually protrudes toward the cell area A1 from the bottom to the top and protrudes from the terminal area A2 toward the cell area A1. It becomes an arc shape.

The cell 11 inside the outermost first trench 21 is a Si MOSFET, but is not limited thereto, and may be a SiC (silicon carbide) MOSFET, for example.
(Circle) the cell 11 inside the outermost 1st trench 21 is not restricted to MOSFET, For example, IGBT may be sufficient. In this case, the semiconductor device 10 may include an emitter region instead of the source region 34 and a p ⁺ collector layer instead of the drain layer 23.

The application target of the semiconductor device 10 is not limited to the inverter and is arbitrary. Further, the mounting target of the semiconductor device 10 is not limited to the vehicle and is arbitrary.
○ The n-type and p-type may be reversed. That is, in each embodiment, the n-type corresponds to the “first conductivity type” and the p-type corresponds to the “second conductivity type”, but the p-type corresponds to the “first conductivity type” and the n-type The mold may correspond to the “second conductivity type”.

Next, a preferable example that can be grasped from the embodiment and another example will be described below.
(A) In the semiconductor device, the upper end of the first floating region is the upper end portion near the termination area in the boundary portion between the first floating region and the insulating film embedded in the first trench. The upper end of the two floating regions is preferably the upper end portion on the cell area side in the boundary portion between the innermost peripheral second floating region and the insulating film embedded in the second trench.

(B) For the semiconductor device, the depth of the first trench and the depth of the second trench may be set to be the same.
(C) Regarding the semiconductor device manufacturing method, after the floating region forming step, an insulating film is formed to cover both the surface of the cell area and the surface of the termination area in the semiconductor substrate while filling the first trench and the second trench. By etching the insulating film in the cell area while leaving the insulating film in the termination area, the surface of the cell area is exposed and a part of the insulating film in the first trench is removed, and the gate electrode is formed in the first trench. A step of forming a space may be provided, and a depth adjustment step may be performed after the step.

  DESCRIPTION OF SYMBOLS 10 ... Semiconductor device, 11 ... Cell, 12 ... Semiconductor substrate, 21 ... 1st trench, 21a ... Bottom part of 1st trench, 22 ... 2nd trench, 22a ... Bottom part of 2nd trench, 22i ... Innermost 2nd trench 23a drain layer (diffusion layer) 24a first drift layer 24b second drift layer 25a first body layer 25b second body layer 31 gate electrode 31a bottom surface of the gate electrode 36, 71 ... first floating region, 36a ... upper end of first floating region, 42, 72 ... second floating region, 42a ... upper end of second floating region (innermost peripheral second floating region), 42i ... innermost peripheral Second floating region, A1 ... cell area, A2 ... terminal area, Z1 ... first distance, Z2 ... second distance, D1 ... depth of first body layer, D2 ... second body layer Depth.

Claims (4)

In a semiconductor device comprising a semiconductor substrate in which a cell area in which a plurality of cells are arranged and a termination area surrounding the cell area are partitioned,
The cell area is
A first drift layer of a first conductivity type;
A first body layer of a second conductivity type formed on the first drift layer;
A first trench penetrating the first body layer and reaching the first drift layer;
A gate electrode housed in the first trench and facing the first body layer via an insulating film;
A first floating region of a second conductivity type provided to cover the bottom of the first trench at a position below the first trench;
Have
The termination area is
A second drift layer of a first conductivity type;
A second body layer of a second conductivity type formed on the second drift layer;
A second trench formed in an annular shape surrounding the cell area, penetrating the second body layer and reaching the second drift layer;
A second floating region of a second conductivity type provided to cover the bottom of the second trench at a position below the second trench;
Have
The bottom surface of the gate electrode protrudes below the interface between the first body layer and the first drift layer,
One or a plurality of the second trench and the second floating region are provided,
The distance between the upper end of the first floating region and the bottom surface of the gate electrode in the vertical direction is a first distance, and corresponds to the innermost second trench in the innermost circumference among the one or more second trenches. When the vertical distance between the upper end of the second floating region and the second body layer is the second distance,
The depth of the second body layer around the innermost second trench is set deeper than the depth of the first body layer so that the first distance and the second distance are the same. A semiconductor device characterized by comprising: The first floating region is surrounded by the first drift layer;
The semiconductor device according to claim 1, wherein the one or more second floating regions are surrounded by the second drift layer.   2. The semiconductor device according to claim 1, wherein the first floating region and the one or more second floating regions reach a diffusion layer formed under the both drift layers. A cell area having a first conductivity type drift layer and a second conductivity type body layer formed on the drift layer, wherein a plurality of cells are arranged, and a termination area surrounding the cell area A method of manufacturing a semiconductor device including a partitioned semiconductor substrate,
Etching is performed so as to penetrate the body layer and reach the drift layer, thereby forming a first trench disposed in the cell area and an annular second trench disposed in the termination area. A trench forming step,
By implanting second conductivity type impurity ions from the bottoms of the first trench and the second trench, the second conductivity type first floating region covering the bottom of the first trench and the bottom of the second trench are formed. A floating region forming step for forming a second floating region of the second conductivity type to cover;
The body layer is disposed in the cell area by implanting first conductivity type impurity ions from the surface of the cell area in the semiconductor substrate to the vicinity of the interface between the drift layer and the body layer. A depth adjusting step of making the depth of one body layer shallower than the depth of the second body layer, which is the body layer disposed in the termination area;
Forming a gate electrode in the first trench; and
With
In the gate electrode forming step, the gate electrode is formed so that a bottom surface of the gate electrode protrudes from a lower surface of the first body layer,
In the trench formation step, one or a plurality of the second trenches are formed,
The distance between the upper end of the first floating region and the bottom surface of the gate electrode in the vertical direction is a first distance, and corresponds to the innermost second trench in the innermost circumference among the one or more second trenches. When the vertical distance between the upper end of the second floating region and the second body layer is the second distance,
In the depth adjusting step, the depth of the first body layer is made shallower than the depth of the second body layer so that the first distance and the second distance are the same. Device manufacturing method.

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