JP5554417B2 - Trench gate power semiconductor device and manufacturing method thereof - Google Patents

Description

  The present invention relates to a trench gate power semiconductor device and a manufacturing method thereof.

  Conventionally, trench gate power MOSFETs have been widely used in various power supply devices such as DC-DC converters (see, for example, Patent Document 1). FIG. 12 is a diagram for explaining a conventional trench gate power MOSFET 900.

As shown in FIG. 12, a conventional trench gate power MOSFET 900 includes an n ⁺ -type drain layer 912, an n ⁻ -type drift layer 914 located on the drain layer 912, and a p-type located on the drift layer 914. The body layer 920, the groove 924 formed by opening the body layer 920 and reaching the drift layer 914, and the body layer 920 are disposed in the body layer 920, and at least a part thereof is exposed to the inner peripheral surface of the groove 924. An n ⁺ -type source region 932 formed, a gate insulating film 926 formed on the inner peripheral surface of the groove 924, a gate electrode layer 928 formed on the inner peripheral surface of the gate insulating film 926, and a gate A source electrode layer (not shown) formed in contact with the source region 932 is provided while being insulated from the electrode layer 928. In conventional trench gate power MOSFET 900, p ⁺ type buried region 940 extending deeper than the groove protrudes downward from body layer 920 in the region sandwiched between adjacent trenches 924 in drift layer 914. Is formed. In FIG. 12, reference numeral 934 indicates a p ⁺ type contact region.

According to the conventional trench gate power MOSFET 900, since the unit cell area can be reduced as compared with the case of the normal planar gate power MOSFET, the on-resistance can be reduced as compared with the case of the normal planar gate power MOSFET. It becomes possible.
Further, according to the conventional trench gate power MOSFET 900, in the region sandwiched between adjacent trenches 924 in drift layer 914, p ⁺ type buried region 940 extending deeper than the trench protrudes downward from body layer 920. Therefore, the electric field in the vicinity of the bottom surface of the groove 924 is relaxed during reverse bias, and the reverse breakdown voltage can be increased.

US Pat. No. 5,072,266

However, in the conventional trench gate power MOSFET 900, the region where the on-current flows during forward bias becomes narrow due to the presence of the p ⁺ -type buried region 940, so that it is difficult to further reduce the on-resistance. There is.

  Such a problem is also seen in the case of a trench gate power MOSFET in which p and n are reversed. Such a problem is not a problem that exists only in the case of the trench gate power MOSFET, but a problem that exists in the trench gate IGBT and other trench gate power semiconductor devices in general.

  Accordingly, the present invention has been made to solve the above-described problems, and an object of the present invention is to provide a trench gate power semiconductor device that has a high reverse breakdown voltage and can further reduce the on-resistance.

[1] A trench gate power semiconductor device according to the present invention includes a first conductivity type drift layer, a second conductivity type body layer located on the drift layer and opposite to the first conductivity type, and the body A groove formed by opening a layer and reaching the drift layer, and a first conductivity type formed by being disposed in the body layer and exposing at least a part of the inner peripheral surface of the groove The first semiconductor region, the gate insulating film formed on the inner peripheral surface of the trench, the gate electrode film formed on the inner peripheral surface of the gate insulating film, and the gate electrode film. A first electrode layer formed in contact with the first semiconductor region, and a region of a second conductivity type extending deeper than the groove in a region sandwiched between the adjacent grooves in the drift layer. An embedded region is formed in contact with the body layer; The depth position where the second conductivity type impurity in the buried region has the maximum concentration is deeper than the depth position located between the bottom surface of the body layer and the bottom surface of the buried region. .

[2] In the trench gate power semiconductor device of the present invention, the periphery of the buried region in the drift layer contains a first conductivity type impurity having a concentration higher than that of the drift layer so as to cover the buried region. It is preferable that a high concentration first conductivity type semiconductor region is formed.

[3] In the trench gate power semiconductor device of the present invention, the depth position of the bottom surface of the groove is deeper than the depth position located between the bottom surface of the body layer and the bottom surface of the drift layer. It is preferable.

[4] In the trench gate power semiconductor device of the present invention, the trench gate power semiconductor device is a trench gate power MOSFET, the first semiconductor region is a source region, and the first electrode layer is a source electrode. Preferably, the first conductivity type drift layer is disposed on the first conductivity type drain layer.

[5] In the trench gate power semiconductor device of the present invention, the trench gate power semiconductor device is a trench gate IGBT, the first semiconductor region is an emitter region, and the first electrode layer is an emitter electrode layer. The first conductivity type drift layer is preferably disposed on the second conductivity type collector layer.

[6] A method for manufacturing a trench gate power semiconductor device according to the present invention is for manufacturing the trench gate power semiconductor device according to the present invention (the trench gate power semiconductor device according to any one of [1] to [5] above). A method of manufacturing a trench gate power semiconductor device, wherein a second conductivity type impurity is ion-implanted into a predetermined region of the drift layer by a multi-stage ion implantation method using a high energy ion implanter to form the buried region. It is characterized by that.

[7] A method for manufacturing a trench gate power semiconductor device according to the present invention is a method for manufacturing a trench gate power semiconductor device for manufacturing the trench gate power semiconductor device according to the present invention (the trench gate power semiconductor device according to [2] above). A first conductivity type impurity is ion-implanted into a predetermined region of the drift layer by an ion implantation method using a high-energy ion implantation apparatus, and a multi-stage ion implantation method using a high-energy ion implantation apparatus. The high-concentration first conductive semiconductor region and the buried region are formed by ion-implanting a second conductive impurity into a predetermined region of the drift layer.

  According to the trench gate power semiconductor device of the present invention, the depth position where the second conductivity type impurity in the buried region has the maximum concentration is more than the depth position located between the bottom surface of the body layer and the bottom surface of the buried region. As shown in FIG. 2 to be described later, the electric field in the vicinity of the bottom surface of the groove is further relaxed during reverse bias, and the reverse breakdown voltage is further improved as compared with the case of the conventional trench gate power MOSFET 900. It becomes possible to make it higher.

  For this reason, since it is possible to increase the impurity concentration of the drift region while maintaining the reverse breakdown voltage, the on-resistance can be further reduced as compared with the case of the conventional trench gate power MOSFET. Therefore, the trench gate power semiconductor device of the present invention is a trench gate power semiconductor device that has a high reverse breakdown voltage and can further reduce the on-resistance.

  According to the manufacturing method of the trench gate power semiconductor device of the present invention (the manufacturing method of the trench gate power semiconductor device of [6] above), the trench gate power semiconductor device of the present invention (of [1] to [5] above). Any one of the trench gate power semiconductor devices) can be manufactured.

  According to the method of manufacturing a trench gate power semiconductor device of the present invention (the method of manufacturing the trench gate power semiconductor device of [7] above), the trench gate power semiconductor device of the present invention (trench gate according to [2] above). Power semiconductor device) can be manufactured.

1 is a view for explaining a trench gate power semiconductor device 100 according to Embodiment 1. FIG. It is a figure which shows typically the electric potential distribution at the time of reverse bias. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment. FIG. 6 is a view for explaining a method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment. FIG. FIG. 6 is a view for explaining a trench gate power semiconductor device 102 according to a second embodiment. FIG. 6 is a view for explaining a method for manufacturing the trench gate power semiconductor device 102 according to the second embodiment. 4 is a cross section of a trench gate power semiconductor device 104 according to a third embodiment. It is sectional drawing of the trench gate power semiconductor device 200 which concerns on a modification. It is a figure shown in order to demonstrate the conventional trench gate power MOSFET900.

  Hereinafter, a trench gate power semiconductor device and a manufacturing method thereof according to the present invention will be described based on embodiments shown in the drawings.

[Embodiment 1]
1. Trench gate power semiconductor device 100 according to the first embodiment
FIG. 1 is a view for explaining a trench gate power semiconductor device 100 according to the first embodiment. 1A is a cross-sectional view of the trench gate power semiconductor device 100, and FIG. 1B is a diagram showing the concentration profiles of p and n impurities in the trench gate power semiconductor device 100. FIG.

As shown in FIG. 1A, the trench gate power semiconductor device 100 according to the first embodiment includes an n ⁻ type drift layer 114, a p type body layer 120 positioned on the drift layer 114, and a body layer 120. And a groove 124 formed to reach the drift layer 114, and an n ⁺ type formed by being exposed in the inner peripheral surface of the groove 124 and being disposed in the body layer 120. A source region (first semiconductor region) 132; a gate insulating film 126 formed on the inner peripheral surface of the trench 124; a gate electrode film 128 formed on the inner peripheral surface of the gate insulating film 126; The trench gate power MOSFET is provided with a source electrode layer (first electrode layer) 136 that is insulated from 128 and formed in contact with the source region 132.

In the trench gate power semiconductor device 100 according to the first embodiment, a p-type buried region 140 extending deeper than the groove 124 is formed in the body layer 120 in a region sandwiched between adjacent grooves 124 in the drift layer 114. The depth position P at which the p-type impurity in the buried region 140 has the maximum concentration is in contact with the bottom surface P2 of the body layer 120 as shown in FIGS. 1 (a) and 1 (b). It lies deeper than the depth position located in the middle of the bottom surface P3 of the embedded region 140. In FIG. 1A, reference numeral 110 indicates a semiconductor substrate, reference numeral 130 indicates a protective insulating film, reference numeral 134 indicates a p ⁺ -type contact region, reference numeral 112 indicates an n ⁺ -type drain layer, Reference numeral 138 denotes a drain electrode layer.

The drain layer 112 has a thickness of, for example, 300 μm, and the drain layer 112 has an impurity concentration of, for example, 2 × 10 ¹⁹ cm ⁻³ . The thickness of the drift layer 114 is, for example, 20 μm, and the impurity concentration of the drift layer 114 is, for example, 1 × 10 ¹⁵ cm ⁻³ . The thickness of the body layer 120 is, for example, 1.5 μm, and the impurity concentration of the body layer 120 is, for example, 1 × 10 ¹⁷ cm ⁻³ on the surface.

The depth of the groove is 2 μm, for example. The depth of the source region 132 is, for example, 0.3 μm, and the impurity concentration of the source region 132 is, for example, 2 × 10 ¹⁹ cm ⁻³ . The depth of the contact region 134 is 1 μm, for example, and the impurity concentration of the contact region 134 is 2 × 10 ¹⁹ cm ⁻³ , for example. The thickness of the gate insulating film 126 is, for example, 0.1 μm. The gate electrode layer 128 is made of, for example, polysilicon doped with phosphorus. The source electrode layer 136 is made of, for example, aluminum and has a thickness of, for example, 5 μm. The source electrode layer 136 is insulated from the gate electrode layer 128 by the protective insulating film 130. The drain electrode layer 138 is made of, for example, nickel and has a thickness of, for example, 2 μm.

  The depth position of the bottom surface P3 of the buried region 140 is deeper than the bottom surface P2 of the body layer 120 by 5 μm. The depth position P at which the p-type impurity has the maximum concentration in the buried region 140 is at a position 3 μm deeper than the bottom surface P2 of the body layer 120. Therefore, the depth position P at which the p-type impurity has the maximum concentration in the buried region 140 is deeper than the depth position located between the bottom surface P2 of the body layer 120 and the bottom surface P3 of the buried region 140.

2. Effect of Trench Gate Power Semiconductor Device 100 According to Embodiment 1 FIG. 2 is a diagram schematically showing a potential distribution during reverse bias. FIG. 2A is a diagram schematically showing a potential distribution at the time of reverse bias in the trench gate power semiconductor device 100 according to the first embodiment, and FIG. 2B is a diagram in the trench gate power semiconductor device 100a according to the comparative example. It is a figure which shows typically the electric potential distribution at the time of reverse bias. The trench gate power semiconductor device 100 according to the first embodiment is manufactured by a “method of manufacturing the trench gate power semiconductor device 100 according to the first embodiment” described later. Further, the trench gate power semiconductor device 100a according to the comparative example is manufactured by a “method of manufacturing the trench gate power semiconductor device 100a according to the comparative example” described later. In FIG. 2, equipotential lines are indicated by broken lines.

  According to the trench gate power semiconductor device 100 according to the first embodiment, as shown in FIG. 1B, the depth position P where the p-type impurity in the buried region 140 has the maximum concentration is the bottom surface P2 of the body layer 120. Since it is deeper than the depth position located in the middle of the bottom surface of the buried region 140, the electric field in the vicinity of the bottom surface of the groove 124 is further relaxed during reverse bias as shown in FIG. The reverse breakdown voltage can be further increased as compared with the conventional trench gate power MOSFET 900. Therefore, according to the trench gate power semiconductor device 100 according to the first embodiment, it is possible to increase the impurity concentration in the drift region while maintaining the reverse breakdown voltage, so that it is much more than in the case of the conventional trench gate power MOSFET. The on-resistance can be lowered.

  Therefore, the trench gate power semiconductor device 100 according to the first embodiment is a trench gate power semiconductor device that has a high reverse breakdown voltage and can further reduce the on-resistance.

3. Method of Manufacturing Trench Gate Power Semiconductor Device 100 According to Embodiment 1 The trench gate power semiconductor device 100 according to Embodiment 1 can be manufactured by the following method.

  3 to 7 are views for explaining the method of manufacturing the trench gate power semiconductor device according to the first embodiment. 3A to FIG. 3C, FIG. 4A to FIG. 4C, FIG. 5A to FIG. 5C, FIG. 6A to FIG. 6C, and FIG. (A)-FIG.7 (c) are each process drawing.

(1) Semiconductor Substrate Preparation Step As shown in FIG. 3A, a structure in which an n ⁺ type semiconductor substrate to be the drain layer 112 and an n ⁻ type epitaxial layer 113 to be the drift layer 114 and the body layer 120 are stacked. A semiconductor substrate 110 is prepared.

(2) Groove Formation Step Thereafter, as shown in FIG. 3B, a groove 124 having a predetermined depth is formed from the surface of the n ⁻ type epitaxial layer 113. The depth of the groove is, for example, 2 μm.

(3) Gate insulating film forming step Thereafter, the semiconductor substrate 110 is subjected to a heat treatment under an oxidizing atmosphere, and as shown in FIG. 3C, the surface of the n ⁻ type epitaxial layer 113 and the inner peripheral surface of the trench 124 Thermal oxide films 126 and 126 ′ are formed on the bottom surface and the side surface. Among the thermal oxide films 126 and 126 ′, the thermal oxide film 126 formed on the inner peripheral surface (bottom surface and side surface) of the groove 124 becomes the gate insulating film 126.

(4) Gate Electrode Layer Formation Step Thereafter, as shown in FIG. 4A, a doped polysilicon film 128 ′ is formed so as to fill the groove 124 from the surface side of the n ⁻ type epitaxial layer 113.
Thereafter, as shown in FIG. 4B, the polysilicon film 128 ′ is etched back, and the polysilicon film 128 ′ is removed while leaving the polysilicon film 128 ′ only in the trench 124. Thereby, the gate electrode layer 128 is formed on the inner peripheral surface of the groove 124.

(5) P-type body layer forming step Thereafter, as shown in FIG. 4C, p-type impurities (for example, boron ions) are ion-implanted from the surface side of the n ⁻ -type epitaxial layer 113 by ion implantation. Ion implantation is performed under conditions of a relatively low acceleration voltage (for example, 100 eV) and a relatively low dose (for example, 1 × 10 ¹³ cm ⁻² ).
Next, heat treatment (for example, 1000 ° C., 1 hour) is performed on the semiconductor substrate 110 to diffuse and activate the p-type impurities, thereby forming the body layer 120 as shown in FIG.

(6) Ion Implantation Step for Forming Buried Layer Subsequently, after forming a mask M1 in a predetermined region on the surface of the body layer 120, the mask M1 is passed through the mask M1 and FIGS. 5 (b), 5 (c) and As shown in FIG. 6A, p-type impurities (for example, boron ions) are ion-implanted from the surface side of the n ⁻ -type epitaxial layer 113 by a multistage ion implantation method. In this step, first, boron ions are implanted under conditions of a first acceleration voltage (for example, 600 keV) and a first dose (for example, 1 × 10 ¹³ cm ⁻² ), and then a second acceleration voltage (for example, 550 keV). ) And a second dose (for example, 3 × 10 ¹² cm ⁻² ), and then boron ions are implanted, and then a third acceleration voltage (for example, 500 keV) and a second dose (for example, 1 × 10 ¹² cm). ^-2 ) by implanting boron ions.

(7) Ion Implantation Step for Forming Contact Region Thereafter, as shown in FIG. 6B, ion implantation of p-type impurities (for example, boron ions) is performed through the mask M1 while the mask M1 is attached. Do. This step is performed by implanting boron ions under conditions of a relatively low acceleration voltage (for example, 50 keV) and a relatively high dose (for example, 5 × 10 ¹⁵ cm ⁻² ).

(8) Ion Implantation Step for Forming Source Region Thereafter, as shown in FIG. 6C, the mask M1 is removed from the surface of the body layer 120, and a mask M2 is formed in a predetermined region on the surface of the body layer 120. After that, ion implantation of n-type impurities (for example, arsenic ions) is performed through the mask M2. This step is performed by implanting arsenic ions under conditions of a relatively low acceleration voltage (for example, 50 keV) and a relatively high dose (for example, 1 × 10 ¹⁵ cm ⁻² ).

(9) Impurity ion activation process Thereafter, the semiconductor substrate 110 is heat-treated to activate n-type impurities and p-type impurities. As a result, as shown in FIG. 7A, a source region 132 and a contact region 134 are formed in the body layer 120, and a buried region having a concentration profile as shown in FIG. 140 is formed.

(10) Step of forming a protective insulating film Thereafter, after removing the thermal oxide film 126 ′ on the surface of the body layer 120, the semiconductor substrate 110 is subjected to a heat treatment to form silicon on the surface of the body layer 120 and the inner peripheral surface of the upper portion of the groove 124. A thermal oxide film is formed, and then a PSG film is formed from the surface side of the body layer 120 by a vapor phase method to form a laminated film. Thereafter, the laminated film is etched by leaving the upper portion of the gate electrode layer 128. Remove. As a result, as shown in FIG. 7B, the protective insulating film 130 is formed on the gate electrode layer 128.

(11) Source electrode layer forming step and drain electrode layer forming step Thereafter, as shown in FIG. 7C, a source electrode layer 136 is formed so as to cover the body layer 120 and the protective insulating film 130, and an n ⁺ -type drain is formed. A drain electrode layer 138 is formed on the surface of the layer 112.

  As described above, the trench gate power semiconductor device 100 according to the first embodiment can be manufactured.

4). Method of Manufacturing Trench Gate Power Semiconductor Device 100a According to Comparative Example The trench gate power semiconductor device 100a according to the comparative example is different from the trench gate according to the first embodiment in steps other than the “ion implantation step for forming a buried layer”. The power semiconductor device 100 is manufactured by a method similar to the method for manufacturing the power semiconductor device 100. The “ion implantation step for forming the buried layer” is performed as follows.

(6 ′) Ion Implantation Step for Forming Buried Layer After that, a mask M1 is formed in a predetermined region on the surface of the body layer 120, and then, from the surface side of the n ⁻ -type epitaxial layer 113 through the mask M1. P-type impurities (for example, boron ions) are ion-implanted by the step ion implantation method. In this step, first, boron ions are implanted under conditions of a first acceleration voltage (for example, 600 keV) and a predetermined dose (for example, 3 × 10 ¹² cm ⁻² ), and then a second acceleration voltage (for example, 550 keV). Further, boron ions are implanted under the condition of the above-mentioned predetermined dose (for example, 3 × 10 ¹² cm ⁻² ), and then the third acceleration voltage (for example, 500 keV) and the above-mentioned predetermined dose (for example, 3 × 10 ¹²⁾ It is performed by implanting boron ions under the condition of cm ⁻² ).

[Embodiment 2]
FIG. 8 is a view for explaining the trench gate power semiconductor device 102 according to the second embodiment. FIG. 8A is a cross-sectional view of the trench gate power semiconductor device 102, and FIG. 8B is a diagram showing the concentration profiles of p and n impurities in the trench gate power semiconductor device 102. FIG. FIG. 9 is a view for explaining a method of manufacturing the trench gate power semiconductor device 102 according to the second embodiment. FIG. 9A to FIG. 9C are diagrams showing main steps. 9A corresponds to FIG. 5A, and FIG. 9C corresponds to FIG. 5B.

The trench gate power semiconductor device 102 according to the second embodiment has basically the same configuration as that of the trench gate power semiconductor device 100 according to the first embodiment. However, as shown in FIG. A trench gate power semiconductor device according to the first embodiment in that an n ⁺ -type semiconductor region 142 containing an n-type impurity at a concentration higher than that of the drift layer 114 is formed around the embedded region 140 so as to cover the buried region 140. 100 is different.

Thus, the trench gate power semiconductor device 102 according to the second embodiment is different from the trench gate power semiconductor device 100 according to the first embodiment in that the n ⁺ -type semiconductor region 142 as described above is formed. Similar to the trench gate power semiconductor device 100 according to the first embodiment, the trench gate power semiconductor device having the above-described embedded region 140 and having a high reverse breakdown voltage and a further lower on-resistance. It becomes.

Further, according to the trench gate power semiconductor device 102 according to the second embodiment, since the n ⁺ type semiconductor region 142 is formed so as to cover the buried region 140, a p-type impurity is present in the region where the on-current flows in the drift layer 114. Is suppressed as much as possible, and the on-resistance can be further reduced.

The trench gate power semiconductor device 102 according to the second embodiment is different from the trench gate power semiconductor device according to the first embodiment except that the n ⁺ type semiconductor region 142 is formed so as to cover the buried region 140. 100, the trench gate power semiconductor device 100 according to the first embodiment has a corresponding effect.

The trench gate power semiconductor device 102 according to the second embodiment can be manufactured by substantially the same process as the method for manufacturing the trench gate power semiconductor device 100 according to the first embodiment. However, as shown in FIG. 9, a region (a region slightly larger than the buried region 140) that covers the buried region 140 between the p-type body layer forming step and the ion implantation step for forming the buried layer. ) Further includes an ion implantation step for forming an n ⁺ type semiconductor region. The ion implantation step can be performed using a high energy ion implantation apparatus. Thereby, the trench gate power semiconductor device 102 according to the second embodiment shown in FIG. 8 can be manufactured.

[Embodiment 3]
FIG. 10 is a cross-sectional view of the trench gate power semiconductor device 104 according to the third embodiment. The trench gate power semiconductor device 104 according to the third embodiment basically has the same configuration as the trench gate power semiconductor device 100 according to the first embodiment, but the depth position of the bottom surface of the groove 124 is related to the first embodiment. Different from the trench gate power semiconductor device 100. That is, in the trench gate power semiconductor device 104 according to the third embodiment, as shown in FIG. 10, the depth position of the bottom surface of the groove 124 is located between the bottom surface of the body layer 120 and the bottom surface of the drift layer 114. Located deeper than the depth position.

  As described above, the trench gate power semiconductor device 104 according to the third embodiment differs from the trench gate power semiconductor device 100 according to the first embodiment in the depth position of the bottom surface of the groove 124, but the trench according to the first embodiment. Similar to the case of the gate power semiconductor device 100, since the buried region 140 having the above-described structure is provided, a trench gate power semiconductor device having a high reverse breakdown voltage and a further reduced on-resistance can be obtained.

  In addition, according to the trench gate power semiconductor device 102 according to the third embodiment, the depth position of the bottom surface of the groove 124 is deeper than the depth position located between the bottom surface of the body layer 120 and the bottom surface of the drift layer 114. Therefore, as in the case of the trench gate power semiconductor device 100 according to the first embodiment, the on-resistance can be further reduced as compared with the conventional case.

In the trench gate power semiconductor device 102 according to the third embodiment, the buried region 140 is covered around the buried region 140 in the drift layer 114 as in the case of the trench gate power semiconductor device 102 according to the second embodiment. As described above, an n ⁺ type semiconductor region 142 containing an n-type impurity at a concentration higher than that of the drift layer 114 may be formed. In this case, even if the depth position of the bottom surface of the groove 124 is set deeper than the depth position located between the bottom surface of the body layer 120 and the bottom surface of the drift layer 114, the reverse breakdown voltage is reduced. There is nothing.

  The trench gate power semiconductor device 104 according to the third embodiment has the same configuration as that of the trench gate power semiconductor device 100 according to the first embodiment except for the depth position of the bottom surface of the groove 124. 1 has a corresponding effect among the effects of the trench gate power semiconductor device 100 according to 1.

  As described above, the trench gate power semiconductor device of the present invention has been described based on the above embodiment, but the present invention is not limited to this, and can be implemented without departing from the scope of the present invention. The following modifications are also possible.

(1) In Embodiment 1 described above, the multi-stage ion implantation method is performed by three-stage ion implantation, but the present invention is not limited to this. The multistage ion implantation method may be performed by two-stage ion implantation, or the multistage ion implantation method may be performed by four or more stages of ion implantation.

(2) In each of the above-described embodiments, the trench gate power semiconductor device of the present invention has been described by taking the trench gate power MOSFET as an example. However, the present invention is not limited to this. FIG. 11 is a cross-sectional view of a trench gate power semiconductor device 200 according to a modification. As shown in FIG. 11, the present invention can be applied to, for example, a trench gate IGBT.

(3) In each of the above embodiments, the semiconductor device of the present invention has been described with the first conductivity type as n-type and the second conductivity type as p-type. However, the present invention is not limited to this. For example, the first conductivity type may be p-type and the second conductivity type may be n-type.

100, 102, 104, 200 ... trench gate power semiconductor device, 110, 210, 910 ... semiconductor substrate, 112, 912 ... drain layer, 113 ... n ^- type epitaxial layer, 114, 214, 914 ... drift layer, 120, 220 , 920 ... body layer, 124, 224, 924 ... groove, 126, 226, 926 ... gate insulating film, 126 '... silicon oxide film, 128' ... polysilicon layer, 128, 228, 928 ... gate electrode layer, 130, 230, 930 ... protective insulating film, 132, 932 ... source region, 134, 234, 934 ... contact region, 136, 936 ... source electrode layer, 138, 938 ... drain electrode layer, 140, 240 ... buried region, 142 ... n ⁺ Type semiconductor region 212 ... collector layer 232 emitter region 236 emitter current Polar layer, 238 ... collector electrode layer, 900 ... trench gate power MOSFET

Claims (5)

A first conductivity type drift layer;
A body layer of a second conductivity type located on the drift layer and opposite to the first conductivity type;
A groove formed by opening the body layer and reaching the drift layer;
A first semiconductor region of a first conductivity type disposed in the body layer and formed by exposing at least a part of the inner peripheral surface of the groove;
A gate insulating film formed on the inner peripheral surface of the groove;
A gate electrode film formed on the inner peripheral surface of the gate insulating film;
A first electrode layer that is insulated from the gate electrode film and formed in contact with the first semiconductor region;
In the region sandwiched between the adjacent grooves in the drift layer, a buried region of a second conductivity type extending deeper than the groove is formed so as to be in contact with the body layer,
A trench gate power semiconductor device in which a depth position where the second conductivity type impurity in the buried region has a maximum concentration is deeper than a depth position located between the bottom surface of the body layer and the bottom surface of the buried region. Because
Around the buried region in the drift layer, a high concentration first conductivity type semiconductor region containing a first conductivity type impurity having a concentration higher than that of the drift layer is formed so as to cover the buried region,
The trench gate power semiconductor device, wherein the high-concentration first conductivity type semiconductor region is formed around the buried region to suppress diffusion of the second conductivity type impurity into the drift layer . The trench gate power semiconductor device according to claim 1,
The trench gate power semiconductor device, wherein a depth position of the bottom surface of the groove is deeper than a depth position located between the bottom surface of the body layer and the bottom surface of the drift layer. In the trench gate power semiconductor device according to claim 1 or 2,
The trench gate power semiconductor device is a trench gate power MOSFET,
The first semiconductor region is a source region;
The first electrode layer is a source electrode layer;
The trench gate power semiconductor device, wherein the first conductivity type drift layer is disposed on the first conductivity type drain layer. In the trench gate power semiconductor device according to claim 1 or 2,
The trench gate power semiconductor device is a trench gate IGBT,
The first semiconductor region is an emitter region;
The first electrode layer is an emitter electrode layer;
The trench gate power semiconductor device, wherein the first conductivity type drift layer is disposed on a second conductivity type collector layer. A method of manufacturing a trench gate power semiconductor device for manufacturing the trench gate power semiconductor device according to claim 1,
The first conductivity type impurity is ion-implanted into the predetermined region of the drift layer by an ion implantation method using a high energy ion implantation apparatus, and the predetermined region of the drift layer is formed by a multi-stage ion implantation method using a high energy ion implantation apparatus. A method of manufacturing a trench gate power semiconductor device, wherein the second conductivity type impurity is ion-implanted to form the high-concentration first conductivity type semiconductor region and the buried region.

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