JP2007266133A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a technique for excellently establishing compatibility between avoiding damage of a semiconductor device and reduction of an ON-voltage. <P>SOLUTION: The semiconductor device 11 is provided with an n<SP>-</SP>-type drift region 25; an n<SP>+</SP>-type carrier accumulating region 26 contacting the drift region 25; a p<SP>-</SP>-type body region 27 contacting the carrier accumulating region 26; an n<SP>+</SP>-type emitter region 29 contacting the body region 27; and a trench gate electrode 34 opposing the body region 27 positioned between the drift region 25 and the emitter region 29, and the carrier accumulating region 26 via a gate insulating film 32. The semiconductor device 11 is further provided with floating body regions 41. The floating body regions 41 are formed on a region including one part of the carrier accumulating region 26. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a bipolar semiconductor device.

  A bipolar semiconductor device can handle a large current and is used, for example, for inverter control of a vehicle-mounted motor. An IGBT (Insulated Gate Bipolar Transistor) is known as an example of an in-vehicle semiconductor device. Patent Document 1 discloses a technique for activating IGBT conductivity modulation to reduce the on-voltage. FIG. 8 schematically shows a cross-sectional view of a main part of a semiconductor device 200 disclosed in Patent Document 1.

The semiconductor device 200 is formed using a silicon single crystal. The semiconductor device 200 includes a collector electrode 222, a p ⁺ -type collector region 223, and an n-type field stop region 224 on the back side. The semiconductor device 200 further includes an n ⁻ type drift region 225, an n type carrier storage region 226 formed on the drift region 225, and a p ⁻ type body formed on the carrier storage region 226. A region 227 and an n ⁺ -type emitter region 229 formed on the body region 227 are provided. A p ⁺ -type body contact region 228 is also formed on the body region 227. The emitter region 229 and the body contact region 228 are electrically connected to the emitter electrode 238. The semiconductor device 200 further includes a trench gate electrode 234 that is covered with a gate insulating film 232. Trench gate electrode 234 extends through body region 227 and carrier storage region 226 located between drift region 225 and emitter region 229, and gate insulating film 232 is formed in body region 227 and carrier storage region 226. Is facing through. The trench gate electrode 234 and the emitter electrode 238 are separated by an interlayer insulating film 236.

  The impurity concentration of the carrier accumulation region 226 is formed to be higher than the impurity concentration of the drift region 225. For this reason, the carrier accumulation region 226 can prevent holes injected from the collector region 223 on the back surface from moving to the body contact region 228 on the front surface. As a result, the carrier accumulation region 226 increases the hole concentration of the drift region 225 and activates conductivity modulation. The semiconductor device 200 can obtain a low on-voltage.

JP-A-8-316479

  Here, a transient period in which the semiconductor device 200 is turned off will be considered. When the semiconductor device 200 is turned off, holes accumulated in the drift region 225 are discharged from the body contact region 228. A carrier storage region 226 exists between the drift region 225 and the body contact region 228. For this reason, the holes accumulated in the drift region 225 are prevented from moving by the carrier accumulation region 226. The holes accumulated in the drift region 225 are attracted to the gate-off voltage (typically 0 V) applied to the trench gate electrode 234, and move inside the carrier accumulation region 226 along the side surface of the gate insulating film 232. Move (see FIG. 8). The holes that have broken through the carrier accumulation region 226 are discharged from the body contact region 228 through the body region 227.

  FIG. 9 shows a gate voltage in a transient period when the semiconductor device 200 is turned off. The semiconductor device 200 is turned off at the timing of T10, and the gate voltage drops from 15V to 0V. According to the study by the present inventors, it has been found that the gate voltage oscillates in a period immediately before it becomes 0 V as shown in FIG. This oscillation phenomenon is considered to be due to the fact that when the semiconductor device 200 is turned off, the gate capacitance fluctuates with time due to the holes moving along the side surface of the gate insulating film 232. The fluctuation of the gate voltage based on this oscillation phenomenon is large, and it instantaneously exceeds the gate threshold value or greatly fluctuates toward the negative voltage side.

When the gate voltage instantaneously exceeds the threshold value due to the oscillation phenomenon, it becomes a trigger, and the phenomenon that holes flow into the emitter region 229 is activated. For this reason, a latch-up phenomenon occurs and the semiconductor device 200 is destroyed. Further, when the gate voltage instantaneously swings to the negative voltage side due to an oscillation phenomenon, the breakdown voltage of the semiconductor device 200 is greatly reduced, and the semiconductor device 200 is destroyed.
If the impurity concentration of the carrier accumulation region 226 is formed thin, this type of problem may be avoided. However, if the impurity concentration of the carrier accumulation region 226 is thin, the hole accumulation effect is deteriorated. For this reason, the semiconductor device 200 cannot obtain a low on-voltage. That is, in the semiconductor device 200 having the conventional structure, it is difficult to satisfactorily provide both the avoidance of breakdown and the low on-voltage.

  The above problem is not limited to the case where the carrier accumulation region is in direct contact with the drift region. A similar problem may occur when the carrier accumulation region is formed in the body region (that is, when the carrier accumulation region is in a floating state).

  An object of the present invention is to provide a technique for satisfactorily providing both of avoidance of destruction of a semiconductor device and a low on-voltage.

  The present invention is characterized in that a semiconductor region having a conductivity type opposite to the carrier storage region is provided in a part of the region for storing carriers. As described above, it has been found by the inventors that many of the accumulated carriers move along the side surface of the gate insulating film during the transitional period in which the semiconductor device is turned off. As a result, it has been found that an oscillation phenomenon occurs in the gate voltage. Therefore, when the opposite conductivity type semiconductor region is provided in the carrier accumulation region, a part of the accumulated carriers can be moved via the opposite conductivity type semiconductor region. For this reason, carriers are suppressed from concentrating on the side surface of the gate insulating film, and the oscillation phenomenon of the gate voltage is also suppressed. Thereby, destruction of the semiconductor device is avoided. In addition, when the opposite conductivity type semiconductor region is provided in the carrier accumulation region, the carrier accumulation effect may seem to decrease. However, the combination of the opposite conductivity type with the carrier accumulation region forms a pn junction, and the electric field can be relaxed. For this reason, the impurity concentration of the carrier storage region can be increased while maintaining the breakdown voltage of the semiconductor device. By increasing the impurity concentration in the carrier accumulation region, the effect of accumulating carriers is improved, and the semiconductor device can obtain a low on-voltage. Therefore, according to the present invention, it is possible to satisfactorily provide both the avoidance of destruction of the semiconductor device and the low on-voltage.

One semiconductor device of the present invention includes a first semiconductor region containing a first conductivity type impurity at a low concentration. The semiconductor device of the present invention further includes a carrier storage region that is in contact with the first semiconductor region and contains a first conductivity type impurity at a high concentration. The semiconductor device of the present invention further includes a second semiconductor region in contact with the carrier storage region, separated from the first semiconductor region by the carrier storage region, and containing a second conductivity type impurity. The semiconductor device of the present invention further includes a third semiconductor region in contact with the second semiconductor region, separated from the carrier accumulation region by the second semiconductor region, and containing a first conductivity type impurity. The semiconductor device of the present invention further includes a gate electrode. The gate electrode is opposed to the second semiconductor region and the carrier storage region located between the first semiconductor region and the third semiconductor region via the gate insulating film. The semiconductor device of the present invention includes a fourth semiconductor region containing an impurity of the second conductivity type. The fourth semiconductor region is formed in a region including a part of the carrier accumulation region. In the semiconductor device of this embodiment, the case where the carrier accumulation region is in contact with the first semiconductor region is targeted.
The form in which it is considered that the fourth semiconductor region is formed in a region including a part of the carrier storage region includes a form in which it can be considered that the fourth semiconductor region is formed in the carrier storage region, and the fourth semiconductor. Includes forms that can be thought of as the region being formed between the carrier storage region and the first semiconductor region, and forms that can be thought of as the fourth semiconductor region being formed across the carrier storage region and the second semiconductor region It is.
When the fourth semiconductor region is provided, part of the accumulated carriers can be discharged through the fourth semiconductor region during a transitional period in which the semiconductor device is turned off. For this reason, carriers are suppressed from concentrating on the side surface of the gate insulating film, and the oscillation phenomenon of the gate voltage is also suppressed. Thereby, destruction of the semiconductor device is avoided.

The fourth semiconductor region may be electrically separated from the second semiconductor region by the carrier accumulation region. In this case, the fourth semiconductor region is in a floating state.
When the fourth semiconductor region is in a floating state, the fourth semiconductor region is not effectively involved in carrier movement during a period in which the semiconductor device is on. That is, carriers do not substantially move through the fourth semiconductor region. On the other hand, in a transitional period in which the semiconductor device is turned off, a strong electric field is applied to the fourth semiconductor region, so that carriers can move through the fourth semiconductor region. The fourth semiconductor region in the floating state can realize a phenomenon in which a phenomenon in which carriers are accumulated and a phenomenon in which carriers are discharged are contradictory in a period in which the semiconductor device is on and a transition period in which the semiconductor device is turned off.

The fourth semiconductor region is preferably separated from the first semiconductor region by the carrier accumulation region.
According to the above aspect, the carrier accumulation region is interposed between the first semiconductor region and the fourth semiconductor region. Therefore, the carrier accumulation region can prevent carriers present in the first semiconductor region from moving to the fourth semiconductor region during the period when the semiconductor device is on.

The distance between the fourth semiconductor region and the gate insulating film is preferably 1 μm or less. More preferably, the fourth semiconductor region is in contact with the gate insulating film.
When the distance between the fourth semiconductor region and the gate insulating film is shortened, a part of the accumulated carriers can move through the fourth semiconductor region in a transient period in which the semiconductor device is turned off. . As a result, the accumulated carriers are prevented from concentrating on the side surface of the gate insulating film. When the fourth semiconductor region and the gate insulating film approach to 1 μm or less, most of the accumulated carriers move through the fourth semiconductor region. When the fourth semiconductor region and the gate insulating film are in contact with each other, the above-described effect is reliably achieved, and the breakdown of the semiconductor device is significantly suppressed.

The impurity concentration of the fourth semiconductor region is preferably formed thinner than the impurity concentration of the second semiconductor region.
When the impurity concentration of the fourth semiconductor region is thin, when the semiconductor device is turned off, the fourth semiconductor region is depleted, and the fourth semiconductor region can relax the electric field. Therefore, the impurity concentration in the carrier accumulation region can be increased and the semiconductor device can obtain a low on-voltage.

Another semiconductor device of the present invention includes a first semiconductor region containing a first conductivity type impurity. The semiconductor device of the present invention further includes a second semiconductor region in contact with the first semiconductor region and containing an impurity of the second conductivity type. The semiconductor device of the present invention further includes a third semiconductor region in contact with the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and containing a first conductivity type impurity. The semiconductor device according to the present invention further includes a floating carrier accumulation region that is electrically separated from the first semiconductor region and the third semiconductor region by the second semiconductor region and contains the impurity of the first conductivity type. The present invention further includes a gate electrode. The gate electrode is opposed to the second semiconductor region and the floating carrier storage region located between the first semiconductor region and the third semiconductor region via a gate insulating film. The semiconductor device according to the present invention further includes a fifth semiconductor region containing an impurity of the second conductivity type. The fifth semiconductor region is formed in a region including a part of the floating carrier accumulation region. In this form of semiconductor device, the carrier accumulation region is separated from the first semiconductor region and is intended for the case where it is formed in the second semiconductor region.
In this case, the carrier accumulation region is in a floating state, and is particularly called a floating carrier accumulation region. The form in which the fifth semiconductor region is considered to be formed in a region including a part of the floating carrier storage region includes a form in which it can be considered that the fifth semiconductor region is formed in the floating carrier storage region, 5 includes a configuration in which it can be considered that the five semiconductor regions are formed over the floating carrier accumulation region and the second semiconductor region.
When the fifth semiconductor region is provided, part of the accumulated carriers can be discharged through the fifth semiconductor region during the transitional period in which the semiconductor device is turned off. For this reason, carriers are suppressed from concentrating on the side surface of the gate insulating film, and the oscillation phenomenon of the gate voltage is also suppressed. Thereby, destruction of the semiconductor device is avoided.

The fifth semiconductor region is preferably electrically separated from the second semiconductor region by the floating carrier storage region. In this case, the fifth semiconductor region is in a floating state. It can be considered that the fifth semiconductor region is buried in the floating carrier accumulation region.
When the fifth semiconductor region is embedded in the floating carrier accumulation region, the fifth semiconductor region is not effectively involved in carrier movement during the period when the semiconductor device is on. That is, the carrier does not substantially move through the fifth semiconductor region. The floating carrier accumulation region surrounding the fifth semiconductor region prevents carriers from moving, thereby accumulating carriers. On the other hand, in a transitional period in which the semiconductor device is turned off, a strong electric field is applied to the fifth semiconductor region, so that carriers can move through the fifth semiconductor region. The fifth semiconductor region in the floating state can realize a phenomenon in which a phenomenon in which carriers are accumulated and a phenomenon in which carriers are discharged are contradictory in a period in which the semiconductor device is on and a transition period in which the semiconductor device is turned off.

The distance between the fifth semiconductor region and the gate insulating film is preferably 1 μm or less. More preferably, the fifth semiconductor region is in contact with the gate insulating film.
When the distance between the fifth semiconductor region and the gate insulating film is shortened, a part of the accumulated carriers can move through the fifth semiconductor region in a transient period in which the semiconductor device is turned off. . For this reason, the accumulated carriers are suppressed from concentrating on the side surface of the gate insulating film. When the fifth semiconductor region and the gate insulating film approach to 1 μm or less, most of the accumulated carriers move through the fifth semiconductor region. When the fifth semiconductor region and the gate insulating film are in contact with each other, the above-described effect is reliably achieved, and the semiconductor device is significantly prevented from being destroyed.

It is preferable that the impurity concentration of the fifth semiconductor region is lower than the impurity concentration of the second semiconductor region.
When the impurity concentration of the fifth semiconductor region is thin, the fifth semiconductor region can be depleted and the electric field can be relaxed when the semiconductor device is turned off. Therefore, the impurity concentration in the carrier accumulation region can be increased and the semiconductor device can obtain a low on-voltage.

  The present invention can also be embodied in a vertical IGBT. The IGBT of the present invention includes a drift region containing a first conductivity type impurity at a low concentration. The IGBT of the present invention is formed on the drift region and includes a carrier accumulation region containing a first conductivity type impurity at a high concentration. The IGBT of the present invention is formed on the carrier accumulation region, and includes a body region containing a second conductivity type impurity. The IGBT of the present invention is further formed on the body region and includes an emitter region containing a first conductivity type impurity. The IGBT of the present invention includes a trench gate electrode. The trench gate electrode extends through a body region and a carrier storage region located between the drift region and the emitter region, and faces the body region and the carrier storage region via a gate insulating film. The IGBT of the present invention is characterized by including a second conductivity type semiconductor region containing a second conductivity type impurity. The second conductivity type semiconductor region is formed in a region including a part of the carrier accumulation region. In this form of IGBT, the case where the carrier accumulation region is in contact with the first semiconductor region is targeted.

The second conductive semiconductor region is preferably electrically separated from the body region by a carrier storage region.
Furthermore, it is preferable that the second conductivity type semiconductor region is separated from the drift region by a carrier accumulation region.

  The present invention can also be embodied in other types of vertical IGBTs. The IGBT of the present invention includes a drift region containing a first conductivity type impurity. The IGBT of the present invention is further formed on the drift region, and includes a body region containing a second conductivity type impurity. The IGBT of the present invention is further formed on the body region and includes an emitter region containing a first conductivity type impurity. The IGBT of the present invention further includes a floating carrier accumulation region that is electrically separated from the drift region and the emitter region by the body region, and includes a first conductivity type impurity. The IGBT of the present invention further includes a trench gate electrode. The trench gate electrode extends through the body region and the floating carrier storage region located between the drift region and the emitter region, and faces the body region and the floating carrier storage region via the gate insulating film. Yes. The IGBT of the present invention further includes a second conductivity type semiconductor region. The second conductivity type semiconductor region is formed in a region including a part of the floating carrier storage region. In this form of IGBT, the case where the floating carrier accumulation region is formed away from the first semiconductor region is targeted.

  The second conductive semiconductor region is preferably electrically separated from the body region by a floating carrier storage region.

  In the semiconductor device of the present invention, since a part of the region for accumulating carriers is provided with a semiconductor region having a conductivity type opposite to the carrier accumulation region, a part of the accumulated carriers is It can move via a semiconductor region of the opposite conductivity type. For this reason, carriers are suppressed from concentrating on the side surface of the gate insulating film, and the oscillation phenomenon of the gate voltage is also suppressed. Furthermore, in the semiconductor device of the present invention, the impurity concentration in the carrier accumulation region can be increased while maintaining the breakdown voltage of the semiconductor device. Therefore, according to the present invention, it is possible to satisfactorily provide both the avoidance of destruction of the semiconductor device and the low on-voltage.

Preferred forms of the present invention are listed.
(First Embodiment) The floating body region is formed below the emitter region when viewed in plan. The effect of suppressing the concentration of holes on the side surface of the trench gate electrode appears significantly.
(Second Embodiment) The floating body region is formed using an ion implantation technique.
(Third Embodiment) A plurality of floating body regions are formed in a dispersed manner in the vertical direction of the semiconductor device.

  Embodiments will be described in detail below with reference to the drawings. In the following embodiments, an example in which silicon is used as a semiconductor material will be described. However, other semiconductor materials may be used. For example, gallium nitride, silicon carbide, gallium arsenide, or the like may be used as the semiconductor material.

(First embodiment)
FIG. 1 schematically shows a cross-sectional view of a main part of the semiconductor device 11. The semiconductor device 11 is a vertical IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 11 includes a collector electrode 22 having a stack of aluminum, titanium, and nickel, a p ⁺ -type collector region 23, and an n-type field stop region 24 on the back surface side. The impurity concentration of the collector region 23 is approximately 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ and the thickness is 0.3 to 2 μm. The impurity concentration of the field stop region 24 is approximately 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and the thickness is 0.3 to 2 μm. The semiconductor device 11 is a punch-through type, but may be a non-punch-through type from which the field stop region 24 is removed. The semiconductor device 11 further includes an n ⁻ type drift region 25 (an example of a first semiconductor region) formed on the field stop region 24. The impurity concentration of the drift region 25 is approximately 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻³ and the thickness is 50 to 200 μm. The semiconductor device 11 further includes an n ⁺ type carrier accumulation region 26 formed on the drift region 25. The impurity concentration of the carrier accumulation region 26 is formed higher than the impurity concentration of the drift region 25. The impurity concentration of the carrier accumulation region 26 is approximately 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and the thickness is 0.5 to 10 μm. The semiconductor device 11 further includes a p ⁻ type body region 27 (an example of a second semiconductor region) formed on the carrier storage region 26. Body region 27 is separated from drift region 25 by carrier accumulation region 26. The impurity concentration of the body region 27 is approximately 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and the thickness is 1 to 8 μm.

The semiconductor device 11 includes an n ⁺ -type emitter region 29 (an example of a third semiconductor region) and a p ⁺ -type body contact region 28 on the surface portion of the body region 28. The emitter region 29 is separated from the carrier accumulation region 25 by the body region 27. The impurity concentration of the emitter region 29 is approximately 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The impurity concentration of the body contact region 28 is approximately 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The emitter region 29 and the body contact region 28 are electrically connected to the emitter electrode 38. Aluminum is used for the emitter electrode 38.

  The semiconductor device 11 further includes a trench gate electrode 34 made of polysilicon containing impurities. The trench gate electrode 34 is covered with a gate insulating film 32 of silicon oxide. The trench gate electrode 34 extends through the body region 27 and the carrier accumulation region 26 located between the drift region 25 and the emitter region 29, and the gate insulating film 32 is formed in the body region 27 and the carrier accumulation region 26. Is facing through. The trench gate electrode 34 and the emitter electrode 38 are separated by an interlayer insulating film 36. The trench gate electrode 34 preferably extends through the carrier accumulation region 26 and into the drift region 25. If the bottom surface of the trench gate electrode 34 penetrates into the drift region 25, it is possible to alleviate the concentration of an excessive electric field at the corner of the bottom surface.

The semiconductor device 11 includes a p ⁻ type floating body region 41 (an example of a fourth semiconductor region). The floating body region 41 is formed including a part of the carrier storage region 26. In this example, it can be considered that the floating body region 41 is embedded in the carrier accumulation region 26. That is, the floating body region 41 is electrically separated from the body region 27 by the carrier accumulation region 26 and is in a floating state. The floating body region 41 is formed by ion implantation and thermal diffusion.

Next, the operation of the semiconductor device 11 will be described.
When a positive voltage is applied to the collector electrode 22, the emitter electrode 38 is grounded, and a gate-on voltage (typically 15V) is applied to the trench gate electrode 34, the semiconductor device 11 is turned on. When the semiconductor device 11 is turned on, an inversion layer is formed in the body region 27 at a position along the side surface of the trench gate electrode 34. Electrons injected from the emitter region 29 are supplied to the carrier storage region 26 via the inversion layer. The electrons moving downward in the carrier storage region 26 are attracted to the gate-on voltage applied to the trench gate electrode 34, and therefore move along the side surface of the trench gate electrode 34. Electrons that have reached the drift region 25 beyond the carrier accumulation region 26 flow in a planar manner in the drift region 25 and reach the field stop region 24. On the other hand, holes injected from the collector region 22 move through the drift region 25 and reach the carrier accumulation region 26. Since the impurity concentration of the carrier accumulation region 26 is formed higher than the impurity concentration of the drift region 25, the carrier accumulation region 26 is a region having high resistance to holes. Holes are prevented from moving through the carrier accumulation region 26. The holes are attracted to electrons flowing along the side surface of the trench gate electrode 24 and gather near the side surface of the trench gate electrode 24. Thereby, the movement of holes in the carrier accumulation region 26 stays in the vicinity of the side surface of the trench gate electrode 24. For this reason, the carrier accumulation region 26 can prevent holes injected from the collector region 23 on the back surface from moving to the body contact region 28 on the front surface. Thereby, the carrier accumulation region 26 increases the hole concentration of the drift region 25 and activates the conductivity modulation. The semiconductor device 11 can obtain a low on-voltage.

When a gate-off voltage (typically 0 V) is applied to the trench gate electrode 34 from the above state, the semiconductor device 11 is turned off. When the semiconductor device 11 is turned off, the inversion layer disappears and the injection of electrons from the emitter region 29 is stopped.
The holes accumulated in the drift region 25 are discharged through the carrier accumulation region 26, the body region 27, and the body contact region 28. At this time, since the carrier accumulation region 26 exists between the drift region 25 and the body contact region 28, the smooth movement of holes is prevented. The semiconductor device 11 includes at least the following two hole discharge paths. One discharge path is that holes attracted to the gate-off voltage (typically 0 V) applied to the trench gate electrode 34 are moved upward in the carrier accumulation region 26 along the side surface of the trench gate electrode 34. It is a route to move toward. The holes that broke through the carrier accumulation region 26 are discharged through the body region 27 and the body contact region 28. Another discharge path is a path through which some of the holes accumulated in the drift region 25 are discharged to the body region 27 and the body contact region 28 via the floating body region 41.

The conventional semiconductor device does not include the floating body contact region 41. For this reason, the conventional semiconductor device does not include the latter discharge path. Therefore, as shown in FIG. 9, the accumulated holes are concentrated in the vicinity of the side surface of the trench gate electrode during the transitional period when the semiconductor device is turned off. For this reason, the gate capacitance fluctuates with time, an oscillation phenomenon appears in the gate voltage, and the semiconductor device is destroyed.
On the other hand, the semiconductor device 11 includes the latter discharge path. Therefore, some of the holes accumulated in the drift region 25 can be discharged via the floating body region 41. For this reason, since the holes accumulated in the drift region 25 are dispersed and discharged, the excessive concentration of holes in the former discharge path is suppressed. Thereby, in the semiconductor device 11, the oscillation phenomenon of the gate voltage is also suppressed and the destruction of the semiconductor device 11 is avoided.

  Further, in the semiconductor device 11, a pn junction is formed between the floating body region 41 and the carrier accumulation region 26. For this reason, when the semiconductor device 11 is turned off, the floating body region 41 is substantially depleted, and the floating body region 41 can relax the electric field. For this reason, the breakdown voltage of the semiconductor device 11 can be maintained even if the impurity concentration of the carrier storage region 26 is increased. When the impurity concentration of the carrier accumulation region 26 is increased, the effect of accumulating holes is improved, and the semiconductor device 11 can obtain a low on-voltage. Therefore, according to the semiconductor device 11, it is possible to satisfactorily have both the avoidance of destruction of the semiconductor device 11 and the low on-voltage.

  Further, the floating body region 41 is surrounded by the carrier accumulation region 26. For this reason, during the period when the semiconductor device 11 is on, holes are effectively prevented from moving between the drift region 25 and the body region 27 via the floating body region 41. On the other hand, in a transitional period in which the semiconductor device 11 is turned off, a strong electric field is applied to the floating body region 41, so that holes can move through the floating body region 41. The body region 41 in the floating state can realize a phenomenon in which the phenomenon of accumulating holes and the phenomenon of expelling holes are contradictory in a period in which the semiconductor device 11 is on and a period in which the semiconductor device 11 is turned off. .

The semiconductor device 11 has the following other features.
(1) The distance L10 between the floating body region 41 and the gate insulating film 32 is preferably short. When the distance L10 between the floating body region 41 and the gate insulating film 32 is shortened, the accumulated holes may be concentrated on the side surface of the gate insulating film 32 during a transient period in which the semiconductor device 11 is turned off. It is suppressed. When the phenomenon of concentrating holes is suppressed, the breakdown voltage of the semiconductor device 11 is improved. Therefore, the impurity concentration of the carrier storage region 26 can be increased, and the on-voltage of the semiconductor device 11 can be reduced. On the other hand, when the distance L10 between the floating body region 41 and the gate insulating film 32 is shortened, the channel resistance is increased. However, the decrease in the on-voltage due to the increase in the impurity concentration of the carrier accumulation region 26 can offset the increase in channel resistance. For this reason, the distance L10 between the floating body region 41 and the gate insulating film 32 is preferably formed short. In particular, when the distance L10 between the floating body region 41 and the gate insulating film 32 is 1 μm or less, a path through which holes are discharged through the floating body region 41 is activated, and the breakdown of the semiconductor device 11 is remarkably suppressed. Is done.
(2) In the semiconductor device 11, the impurity concentration of the floating body region 41 is formed thinner than the impurity concentration of the body region 27. If the impurity concentration of the floating body region 41 is thin, the floating body region 41 is substantially depleted during the period when the semiconductor device 11 is off, and the floating body region 41 can relax the electric field. . For this reason, the impurity concentration of the carrier storage region 26 can be increased, and the semiconductor device 11 can obtain a low on-voltage.

(Modification of Semiconductor Device 11)
FIG. 2 schematically shows a cross-sectional view of the main part of the semiconductor device 12. Components that are practically the same as those of the semiconductor device 11 are given the same reference numerals, and descriptions thereof are omitted. The same treatment is applied to the other modified examples described below.
In the semiconductor device 12, the floating body region 42 is in contact with the gate insulating film 32. When the floating body region 42 and the gate insulating film 32 are in contact, most of the holes are discharged through the floating body region 41. For this reason, the destruction of the semiconductor device 12 is remarkably suppressed.
Furthermore, when the floating body region 42 is in contact with the gate insulating film 32, the potential of the floating body region 42 is easily affected by the gate voltage applied to the trench gate electrode 34. For this reason, in the transitional period in which the semiconductor device 12 is turned off, the potential of the floating body region 42 is close to the gate-off voltage (typically 0 V). As a result, the holes accumulated in the drift region 25 are attracted to the potential of the floating body region 42, so that most of the holes are discharged to the body region 27 and the body contact region 28 via the floating body region 42. The In a transitional period in which the semiconductor device 12 is turned off, the phenomenon that holes are concentrated on the side surface of the trench gate electrode 34 is suppressed, the oscillation phenomenon of the gate voltage is suppressed, and the breakdown of the semiconductor device 12 is suppressed.

FIG. 3 schematically shows a cross-sectional view of the main part of the semiconductor device 13.
In the semiconductor device 13, the floating body region 43 is not embedded and formed in the carrier accumulation region 26. A part of the floating body region 43 is formed in the drift region 25. It can be considered that the floating body region 43 is formed across the carrier accumulation region 26 and the drift region 25. The floating body region 43 is electrically separated from the body region 27 by the carrier accumulation region 25 and is in a floating state. Similarly, in the semiconductor device 13, part of the holes accumulated in the drift region 25 are discharged from the body region 27 and the body contact region 28 via the floating body region 43. For this reason, it is suppressed that a hole concentrates on the side surface of the trench gate electrode 34, the oscillation phenomenon of a gate voltage is suppressed, and destruction of the semiconductor device 13 is suppressed.

FIG. 4 schematically shows a cross-sectional view of the main part of the semiconductor device 14.
In the semiconductor device 14, a part of the p ⁻ type semiconductor region 44 is formed in the body region 27. The p ⁻ type semiconductor region 44 is in contact with the body region 27 and is not in a floating state. It can be considered that the p ⁻ type semiconductor region 44 is formed across the carrier accumulation region 26 and the body region 27. However, the impurity concentration of the p ⁻ type semiconductor region 44 is formed thinner than the impurity concentration of the body region 27, and is clearly a region different from the body region 27. Also in the semiconductor device 14, some of the holes accumulated in the drift region 25 are discharged from the body region 27 and the body contact region 28 via the p ⁻ type semiconductor region 44. For this reason, it is suppressed that a hole concentrates on the side surface of the trench gate electrode 34, the oscillation phenomenon of a gate voltage is suppressed, and destruction of the semiconductor device 14 is suppressed.
Further, a part of the p ⁻ type semiconductor region 44 is formed in the carrier storage region 26. Since the impurity concentration of the p ⁻ type semiconductor region 44 is low, the p ⁻ type semiconductor region 44 is substantially depleted during a period in which the semiconductor device 14 is off. For this reason, the breakdown voltage of the semiconductor device 14 is maintained even if the impurity concentration of the carrier storage region 26 is increased. While maintaining the breakdown voltage of the semiconductor device 14, a low on-voltage can be achieved.

FIG. 5 schematically shows a cross-sectional view of the main part of the semiconductor device 15.
In the semiconductor device 15, an n ⁺ type semiconductor region for accumulating holes is electrically separated from the emitter region 29 and the drift region 25 by the body region 27. This semiconductor region is referred to as a floating carrier storage region 56. The floating carrier accumulation region 56 is formed at a shallow position of the body region 27, and improves the hole concentration in the body region 27 and consequently the hole concentration in the drift region 25. In general, it is known that the drop in hole concentration in the body region 27 is the largest. The floating carrier accumulation region 56 is extremely useful in that it can improve the drop in hole concentration in the body region 27. The semiconductor device 15 includes a floating body region 45 (an example of a fifth semiconductor region) formed in the floating carrier storage region 56. The floating body region 45 is electrically separated from the body region 27 by the floating body region 45. Similarly, in the semiconductor device 15, some of the holes accumulated in the drift region 25 and the lower body region 27 pass through the floating body region 45 and the upper body region 27 and the body contact region 28. Discharged. Therefore, the concentration of holes on the side surface of the trench gate electrode 34 is suppressed, the oscillation phenomenon of the gate voltage is suppressed, and the breakdown of the semiconductor device 15 is suppressed.
The semiconductor device 15 is distinguished from each of the semiconductor devices described above in that it includes a floating carrier storage region 56. Other technical ideas relating to the semiconductor devices described above can be applied to the semiconductor device 15.

(Second embodiment)
FIG. 6 schematically shows a cross-sectional view of the main part of the semiconductor device 100. The semiconductor device 100 is a vertical IGBT (Insulated Gate Bipolar Transistor). The semiconductor device 100 is different from the semiconductor devices of the first embodiment having the trench gate electrode 34 in that the planar gate electrode 134 is provided. However, the semiconductor device 100 also has a problem that holes are concentrated along the gate insulating film 132 during a transient period in which the semiconductor device 100 is turned off. Therefore, the problem can be solved also for the semiconductor device 100 based on the same technical idea as the first embodiment.

The semiconductor device 100 includes a collector electrode 122 having a stack of aluminum, titanium, and nickel, a p ⁺ -type collector region 123, and an n-type field stop region 124 on the back surface side. The impurity concentration of the collector region 123 is approximately 1 × 10 ¹⁷ to 1 × 10 ²⁰ cm ⁻³ and the thickness is 0.3 to 2 μm. The impurity concentration of the field stop region 124 is approximately 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ and the thickness is 0.3 to 2 μm. The semiconductor device 100 is a punch-through type, but may be a non-punch-through type from which the field stop region 124 is removed.
The semiconductor device 100 further includes an n ⁻ type drift region 125 (an example of a first semiconductor region) formed on the field stop region 124. The impurity concentration of the drift region 125 is approximately 1 × 10 ¹³ to 1 × 10 ¹⁵ cm ⁻³ and the thickness is 50 to 200 μm. The semiconductor device 100 further includes an n ⁺ -type carrier storage region 126 formed in contact with the drift region 125. The carrier accumulation region 126 is formed in a distributed manner on the surface portion of the drift region 125. The impurity concentration of the carrier accumulation region 126 is formed higher than the impurity concentration of the drift region 125. The impurity concentration of the carrier accumulation region 126 is approximately 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ . The semiconductor device 100 further includes a p ⁻ type body region 127 (an example of a second semiconductor region) formed in contact with the carrier storage region 126. The body region 127 is surrounded by the carrier accumulation region 126 and is separated from the drift region 125 by the carrier accumulation region 126. The impurity concentration of the body region 127 is approximately 1 × 10 ¹⁶ to 1 × 10 ¹⁸ cm ⁻³ .

The semiconductor device 100 includes an n ⁺ -type emitter region 129 (an example of a third semiconductor region) and a p ⁺ -type body contact region 128 on the surface of the body region 128. Emitter region 129 is separated from carrier accumulation region 126 by body region 127. The impurity concentration of the emitter region 129 is approximately 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The impurity concentration of the body contact region 128 is approximately 1 × 10 ¹⁸ to 1 × 10 ²⁰ cm ⁻³ . The emitter region 129 and the body contact region 128 are electrically connected to the emitter electrode 138. Aluminum is used for the emitter electrode 138.

  The semiconductor device 100 further includes a planar gate electrode 134 made of polysilicon containing impurities. The planar gate electrode 134 is covered with a gate insulating film 132 made of silicon oxide. The planar gate electrode 134 faces the body region 127 and the carrier storage region 126 located between the drift region 125 and the emitter region 129 with the gate insulating film 132 interposed therebetween.

The semiconductor device 100 includes a p ⁻ type floating body region 141 (an example of a fourth semiconductor region). The floating body region 141 is formed including a part of the carrier accumulation region 126. In the semiconductor device 100, it can be considered that the floating body region 141 is formed so as to be embedded in the carrier accumulation region 126. That is, the floating body region 141 is electrically separated from the body region 127 by the carrier accumulation region 126 and is in a floating state. The floating body region 141 is formed by ion implantation and thermal diffusion.

Next, the operation of the semiconductor device 100 will be described.
When a positive voltage is applied to the collector electrode 122, the emitter electrode 138 is grounded, and a gate-on voltage (typically 15V) is applied to the planar gate electrode 134, the semiconductor device 100 is turned on. When the semiconductor device 100 is turned on, an inversion layer is formed in a part of the body region 127 at a position along the side surface of the planar gate electrode 134. Electrons injected from the emitter region 129 are supplied to the carrier accumulation region 126 via the inversion layer. The electrons that move in the carrier storage region 126 in the lateral direction are attracted to the gate-on voltage applied to the planar gate electrode 134 and therefore move along the bottom surface of the planar gate electrode 134. The electrons that reach the drift region 125 beyond the carrier accumulation region 126 flow in a planar manner in the drift region 125 and reach the field stop region 124. On the other hand, holes injected from the collector region 122 move through the drift region 125 and reach the carrier accumulation region 126. Since the carrier accumulation region 126 has a high impurity concentration and is formed higher than the impurity concentration of the drift region 125, the carrier accumulation region 126 is a region having high resistance to holes. Holes are prevented from moving through the carrier accumulation region 126. The holes are attracted to electrons flowing along the bottom surface of the planar gate electrode 124 and gather near the bottom surface of the planar gate electrode 124. As a result, the movement of holes in the carrier accumulation region 126 stays in the vicinity of the bottom surface of the planar gate electrode 124. For this reason, the carrier accumulation region 126 can prevent the holes injected from the collector region 123 on the back surface from moving to the body contact region 128 on the front surface. Thereby, the carrier accumulation region 126 increases the hole concentration of the drift region 125 and activates conductivity modulation. The semiconductor device 100 can obtain a low on-voltage.

When a gate-off voltage (typically 0 V) is applied to the planar gate electrode 134 from the above state, the semiconductor device 100 is turned off. When the semiconductor device 100 is turned off, the inversion layer disappears and the injection of electrons from the emitter region 129 stops.
The holes accumulated in the drift region 125 are discharged through the carrier accumulation region 126, the body region 127, and the body contact region 128. At this time, since the carrier accumulation region 126 exists between the drift region 125 and the body contact region 128, the smooth movement of holes is prevented. The semiconductor device 100 is characterized by including at least the following two hole discharge paths. One discharge path is a path through which holes attracted to a gate-off voltage (typically 0 V) applied to the planar gate electrode 134 move through the carrier accumulation region 126 along the bottom surface of the planar gate electrode 134. It is. The holes that broke through the carrier accumulation region 126 are discharged through the body region 127 and the body contact region 128. Another discharge path is a path through which some of the holes accumulated in the drift region 125 are discharged to the body region 127 and the body contact region 128 via the floating body region 141.

The conventional semiconductor device does not include the floating body contact region 141. For this reason, the conventional semiconductor device does not include the latter discharge path. Therefore, as shown in FIG. 9, the accumulated holes are concentrated in the vicinity of the lower surface of the planar gate electrode during the transitional period when the semiconductor device is turned off. For this reason, the gate capacitance fluctuates with time, an oscillation phenomenon appears in the gate voltage, and the semiconductor device is destroyed.
On the other hand, the semiconductor device 100 includes the latter discharge path. Accordingly, some of the holes accumulated in the drift region 125 are discharged via the floating body region 141. For this reason, since the holes accumulated in the drift region 125 are dispersed and discharged, the excessive concentration of holes in the former discharge path is suppressed. Thereby, in the semiconductor device 100, the oscillation phenomenon of the gate voltage is also suppressed, and the destruction of the semiconductor device 100 is avoided.

  Further, in the semiconductor device 100, a pn junction is formed between the floating body region 141 and the carrier accumulation region 126. For this reason, when semiconductor device 100 is turned off, floating body region 141 is substantially depleted, and floating body region 141 can relax the electric field. For this reason, the breakdown voltage of the semiconductor device 100 can be maintained even if the impurity concentration of the carrier accumulation region 126 is increased. When the impurity concentration of the carrier accumulation region 126 is increased, the effect of accumulating holes is improved, and the semiconductor device 100 can obtain a low on-voltage. Therefore, according to the semiconductor device 100, it is possible to satisfactorily have both the avoidance of destruction of the semiconductor device 100 and the low on-voltage.

  Further, the floating body region 141 is surrounded by the carrier accumulation region 126. For this reason, when the semiconductor device 100 is on, holes are effectively prevented from moving between the drift region 125 and the body region 127 via the floating body region 141. On the other hand, in a transitional period in which the semiconductor device 100 is turned off, a strong electric field is applied to the floating body region 141, so that holes can move through the floating body region 141. The body region 141 in the floating state can realize a phenomenon in which the phenomenon of accumulating holes and the phenomenon of expelling holes are contradictory in a period in which the semiconductor device 100 is on and a transition period in which the semiconductor device 100 is turned off. .

The semiconductor device 100 has the following other features.
(1) The distance L100 between the floating body region 141 and the gate insulating film 132 is preferably short. When the distance L100 between the floating body region 141 and the gate insulating film 132 is shortened, the accumulated holes may be concentrated on the bottom surface of the gate insulating film 132 during the transitional period when the semiconductor device 100 is turned off. It is suppressed. When the phenomenon of concentrating holes is suppressed, the breakdown voltage of the semiconductor device 100 is improved. Therefore, the impurity concentration of the carrier accumulation region 126 can be increased, and the on-voltage of the semiconductor device 100 can be reduced. On the other hand, when the distance L100 between the floating body region 141 and the gate insulating film 132 is shortened, the channel resistance is increased. However, the reduction in the on-voltage based on the increase in the impurity concentration of the carrier accumulation region 126 can cancel the increase in channel resistance. For this reason, it is preferable that the distance L100 between the floating body region 141 and the gate insulating film 132 be short. In particular, when the distance L100 between the floating body region 141 and the gate insulating film 132 is 1 μm or less, the path for discharging holes through the floating body region 141 is activated, and the breakdown of the semiconductor device 100 is remarkably suppressed. Is done.
(2) In the semiconductor device 100, the impurity concentration of the floating body region 141 is formed to be lower than the impurity concentration of the body region 127. If the impurity concentration of the floating body region 141 is thin, the floating body region 141 is substantially depleted when the semiconductor device 100 is turned off, and the floating body region 141 can relax the electric field. . Therefore, the impurity concentration of the carrier accumulation region 126 can be increased, and the semiconductor device 100 can obtain a low on-voltage.

(Modification of Semiconductor Device 100)
FIG. 7 is a schematic cross-sectional view of the main part of the semiconductor device 110. Note that components that are practically the same as those of the semiconductor device 100 are denoted by the same reference numerals and description thereof is omitted.
In the semiconductor device 110, the floating body region 142 is in contact with the gate insulating film 132. When the floating body region 142 and the gate insulating film 132 are in contact with each other, most of the holes are discharged through the floating body region 141. For this reason, destruction of the semiconductor device 110 is significantly suppressed.
Further, when the floating body region 142 is in contact with the gate insulating film 132, the potential of the floating body region 142 is easily affected by the gate voltage applied to the planar gate electrode 134. For this reason, in the transitional period in which the semiconductor device 110 is turned off, the potential of the floating body region 142 becomes a value close to the gate-off voltage (typically 0 V). As a result, holes accumulated in the drift region 125 are attracted to the potential of the floating body region 142, so that most of the holes are discharged to the body region 127 and the body contact region 128 via the floating body region 142. The In a transitional period in which the semiconductor device 110 is turned off, the phenomenon that holes are concentrated on the bottom surface of the planar gate electrode 134 is suppressed, the oscillation phenomenon of the gate voltage is suppressed, and the breakdown of the semiconductor device 110 is suppressed.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part sectional drawing of the semiconductor device of 1st Example is typically shown. The principal part sectional drawing of one modification of the semiconductor device of 1st Example is typically shown. The principal part sectional drawing of the other one modification of the semiconductor device of 1st Example is typically shown. The principal part sectional drawing of the other one modification of the semiconductor device of 1st Example is typically shown. The principal part sectional drawing of the other one modification of the semiconductor device of 1st Example is typically shown. The principal part sectional drawing of the semiconductor device of 2nd Example is shown typically. The principal part sectional drawing of one modification of the semiconductor device of 2nd Example is shown typically. The principal part sectional drawing of the conventional semiconductor device is shown typically. The fluctuation with time of the gate voltage of the conventional semiconductor device is shown.

Explanation of symbols

22, 122: Collector electrode 23, 123: Collector region 24, 124: Field stop region 25, 125: Drift region 26, 126: Carrier storage region 27, 127: Body region 28, 128: Body contact region 29, 129: Emitter Regions 32 and 132: Gate insulating film 34: Trench gate electrode 134: Planar gate electrode 36: Interlayer insulating films 41, 42, 43, 45, 141, 142: Floating body region 44: P ^- type semiconductor region 56: Floating carrier Accumulation area

Claims (16)

A semiconductor device,
A first semiconductor region containing a first conductivity type impurity at a low concentration;
A carrier accumulation region in contact with the first semiconductor region and containing a first conductivity type impurity at a high concentration;
A second semiconductor region in contact with the carrier storage region, separated from the first semiconductor region by the carrier storage region, and containing a second conductivity type impurity;
A third semiconductor region in contact with the second semiconductor region, separated from the carrier accumulation region by the second semiconductor region, and containing a first conductivity type impurity;
A gate electrode facing the second semiconductor region and the carrier storage region located between the first semiconductor region and the third semiconductor region via a gate insulating film;
A fourth semiconductor region formed in a region including a part of the carrier accumulation region, and including a second conductivity type impurity;
A semiconductor device comprising:   The semiconductor device according to claim 1, wherein the fourth semiconductor region is electrically separated from the second semiconductor region by a carrier accumulation region.   The semiconductor device according to claim 1, wherein the fourth semiconductor region is separated from the first semiconductor region by a carrier accumulation region.   The semiconductor device according to claim 1, wherein a distance between the fourth semiconductor region and the gate insulating film is 1 μm or less.   The semiconductor device according to claim 4, wherein the fourth semiconductor region is in contact with the gate insulating film.   6. The semiconductor device according to claim 1, wherein the impurity concentration of the fourth semiconductor region is lower than the impurity concentration of the second semiconductor region. A semiconductor device,
A first semiconductor region containing an impurity of a first conductivity type;
A second semiconductor region in contact with the first semiconductor region and containing an impurity of a second conductivity type;
A third semiconductor region in contact with the second semiconductor region, separated from the first semiconductor region by the second semiconductor region, and containing a first conductivity type impurity;
A floating carrier storage region electrically isolated from the first semiconductor region and the third semiconductor region by the second semiconductor region and including an impurity of the first conductivity type;
A gate electrode facing the second semiconductor region and the floating carrier storage region located between the first semiconductor region and the third semiconductor region via a gate insulating film;
A fifth semiconductor region formed in a region including a part of the floating carrier accumulation region, and including a second conductivity type impurity;
A semiconductor device comprising:   8. The semiconductor device according to claim 7, wherein the fifth semiconductor region is electrically separated from the second semiconductor region by a floating carrier accumulation region.   9. The semiconductor device according to claim 7, wherein a distance between the fifth semiconductor region and the gate insulating film is 1 μm or less.   The semiconductor device according to claim 9, wherein the fifth semiconductor region is in contact with the gate insulating film.   11. The semiconductor device according to claim 7, wherein the impurity concentration of the fifth semiconductor region is lower than the impurity concentration of the second semiconductor region. A vertical IGBT,
A drift region containing a first conductivity type impurity in a low concentration;
A carrier accumulation region formed on the drift region and containing a high concentration of impurities of the first conductivity type;
A body region formed on the carrier accumulation region and containing a second conductivity type impurity;
An emitter region formed on the body region and including an impurity of a first conductivity type;
A trench gate electrode extending through a body region and a carrier storage region located between the drift region and the emitter region, and facing the body region and the carrier storage region via a gate insulating film;
A second conductivity type semiconductor region formed in a region including a part of the carrier accumulation region, and including a second conductivity type impurity;
IGBT equipped with.   The IGBT according to claim 12, wherein the second conductivity type semiconductor region is electrically separated from the body region by a carrier accumulation region.   14. The IGBT according to claim 12, wherein the second conductivity type semiconductor region is separated from the drift region by a carrier accumulation region. A drift region that is a vertical IGBT and includes a first conductivity type impurity;
A body region formed on the drift region and containing a second conductivity type impurity;
An emitter region formed on the body region and including an impurity of a first conductivity type;
A floating carrier storage region electrically isolated from the drift region and the emitter region by the body region, and including a first conductivity type impurity;
A trench gate electrode extending through a body region and a floating carrier storage region located between the drift region and the emitter region, and facing the body region and the floating carrier storage region via a gate insulating film; ,
A second conductivity type semiconductor region formed in a region including a part of the floating carrier accumulation region, and containing a second conductivity type impurity;
IGBT equipped with.   14. The IGBT according to claim 13, wherein the second conductivity type semiconductor region is electrically separated from the body region by a floating carrier storage region.

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