JPH0778978A - Vertical mosfet transistor - Google Patents
Vertical mosfet transistorInfo
- Publication number
- JPH0778978A JPH0778978A JP5246434A JP24643493A JPH0778978A JP H0778978 A JPH0778978 A JP H0778978A JP 5246434 A JP5246434 A JP 5246434A JP 24643493 A JP24643493 A JP 24643493A JP H0778978 A JPH0778978 A JP H0778978A
- Authority
- JP
- Japan
- Prior art keywords
- region
- type
- body region
- gate electrode
- epitaxial layer
- Prior art date
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- 210000000746 body region Anatomy 0.000 claims abstract description 68
- 239000004065 semiconductor Substances 0.000 claims abstract description 26
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 230000005669 field effect Effects 0.000 claims description 48
- 230000015556 catabolic process Effects 0.000 abstract description 42
- 230000003071 parasitic effect Effects 0.000 abstract description 19
- 238000009413 insulation Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 description 11
- 230000005684 electric field Effects 0.000 description 6
- 230000006378 damage Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 2
- 239000012535 impurity Substances 0.000 description 2
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- 239000012141 concentrate Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 230000003763 resistance to breakage Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、アバランシェ降伏によ
る破壊耐量を増大した縦型ＭＯＳ電界効果トランジスタ
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a vertical MOS field effect transistor having increased breakdown resistance due to avalanche breakdown.
【０００２】[0002]
【従来の技術】従来より、縦型ＭＯＳ電界効果トランジ
スタは、大電流の高速スイッチングが可能なので、モー
タ制御、スイッチングレギュレータ、ＣＲＴ偏向用とし
て多用されている。2. Description of the Related Art Conventionally, vertical MOS field effect transistors have been widely used for motor control, switching regulators, and CRT deflection because they enable high-current high-speed switching.
【０００３】図３には、従来の縦型ＭＯＳ電界効果トラ
ンジスタの１セルの模型断面図が示されている。この従
来の縦型ＭＯＳ電界効果トランジスタ１００は、シリコ
ン基板の裏面側の高濃度Ｎ＋型領域をドレイン領域１０
１とし、裏面にドレイン電極１０２が形成されている。
また、表面側には、Ｎ−型エピタキシャル層１０３が形
成され、その表面上に所定の間隔で酸化膜１０７を介し
た多結晶シリコンによる絶縁ゲート電極１０８が配置さ
れている。FIG. 3 shows a model cross-sectional view of one cell of a conventional vertical MOS field effect transistor. In this conventional vertical type MOS field effect transistor 100, a high concentration N + type region on the back surface side of a silicon substrate is formed into a drain region 10.
1, and the drain electrode 102 is formed on the back surface.
Further, an N − type epitaxial layer 103 is formed on the front surface side, and an insulated gate electrode 108 made of polycrystalline silicon with an oxide film 107 interposed therebetween is disposed on the surface at a predetermined interval.
【０００４】このゲート電極１０８の周縁直下にチャネ
ル領域１０５を形成するように、Ｎ−型エピタキシャル
層１０３表面にＰ型ボディー領域１０４とＮ＋型ソース
領域１０６とが形成されている。そして、このＰ型ボデ
ィー領域１０４とＮ＋型ソース領域１０６を電気的に短
絡させるようにアルミニウムによるソース電極１０９が
形成されている。A P type body region 104 and an N + type source region 106 are formed on the surface of the N − type epitaxial layer 103 so as to form a channel region 105 just below the periphery of the gate electrode 108. A source electrode 109 made of aluminum is formed so as to electrically short the P type body region 104 and the N + type source region 106.
【０００５】この従来の縦型ＭＯＳ電界効果トランジス
タ１００は、ゲート電極１０８に電圧を印加することに
より、ゲート電極１０８下のＰ型ボディー領域１０４表
面のチャネル領域１０５をＮ型に反転させ、ここを通る
ドレイン電流をゲート電極１０８に印加する電圧値で制
御するように動作させるものである。In this conventional vertical MOS field effect transistor 100, by applying a voltage to the gate electrode 108, the channel region 105 on the surface of the P-type body region 104 under the gate electrode 108 is inverted to N-type, and It is operated so that the drain current passing therethrough is controlled by the voltage value applied to the gate electrode 108.
【０００６】前述の縦型ＭＯＳ電界効果トランジスタの
製造方法に関して詳述しているものとしては、特開昭６
３−２６０１７６号公報がある。Japanese Unexamined Patent Publication (Kokai) No. Sho 6-61 is a detailed description of a method for manufacturing the above-mentioned vertical MOS field effect transistor.
There is a publication of 3-260176.
【０００７】図４（Ａ）には、従来の縦型ＭＯＳ電界効
果トランジスタ１００を用いたスイッチング回路の一例
が示され、図４（Ｂ）には回路各部の電圧波形が模擬的
に示されている。FIG. 4A shows an example of a switching circuit using a conventional vertical MOS field effect transistor 100, and FIG. 4B schematically shows voltage waveforms at various parts of the circuit. There is.
【０００８】インダクタンス負荷４０１を縦型ＭＯＳ電
界効果トランジスタ１００でスイッチングする場合、図
４（Ｂ）に示すように、インダクタンス負荷４０１を遮
断した瞬間に高い電流変化率で大きなサージ電圧４０３
が発生し、このサージ電圧４０３が縦型ＭＯＳ電界効果
トランジスタ１００のソース・ドレイン間に印加され
る。When the inductance load 401 is switched by the vertical MOS field effect transistor 100, as shown in FIG. 4B, a large surge voltage 403 is generated at a high current change rate at the moment when the inductance load 401 is cut off.
And the surge voltage 403 is applied between the source and drain of the vertical MOS field effect transistor 100.
【０００９】従来の縦型ＭＯＳ電界効果トランジスタ１
００は、このようなサージ電圧４０３によりアバランシ
ェ降伏が発生し、素子が破壊されやすいという問題があ
った。Conventional vertical MOS field effect transistor 1
No. 00 had a problem that such a surge voltage 403 causes avalanche breakdown and the element is easily broken.
【００１０】この問題を、図５を用いて、以下に詳述す
る。図５は、従来の縦型ＭＯＳ電界効果トランジスタ１
００の主な寄生素子を示す断面図である。This problem will be described in detail below with reference to FIG. FIG. 5 shows a conventional vertical MOS field effect transistor 1
It is sectional drawing which shows the main parasitic element of 00.
【００１１】サージ電圧４０３が縦型ＭＯＳ電界効果ト
ランジスタ１００のソース・ドレイン間に印加された状
態においては、Ｐ型ボディー領域１０４とＮ−型エピタ
キシャル層１０３とが形成するＰＮ接合部（これが寄生
の接合ダイオード５０３として機能する）に逆バイアス
がかかることになる。When the surge voltage 403 is applied between the source and drain of the vertical MOS field effect transistor 100, a PN junction portion formed by the P type body region 104 and the N − type epitaxial layer 103 (this is a parasitic (Functioning as junction diode 503) will be reverse biased.
【００１２】つまり、寄生の接合ダイオード５０３に逆
バイアスがかかることになり、この寄生ダイオード５０
３が降伏して電流が流れる。これにより、縦型ＭＯＳ電
界効果トランジスタ１００は、サージ電圧４０３として
素子に加えられたエネルギーを吸収しようとする。That is, the parasitic junction diode 503 is reversely biased, and the parasitic diode 50
3 breaks down and a current flows. As a result, the vertical MOS field effect transistor 100 tries to absorb the energy applied to the element as the surge voltage 403.
【００１３】この時の降伏状態はアバランシェ（電子な
だれ）降伏と呼ばれる。これに関して簡単に説明する。The breakdown state at this time is called avalanche (electron avalanche) breakdown. This will be briefly described.
【００１４】ＰＮ接合に逆バイアスがかかると、空乏層
が広がり空乏層内に高電界がかかる。空乏層内で発生し
た電子・正孔対は、高電界によって加速され、バンドギ
ャップの１．５倍以上のエネルギーを持つようになる。
すると、そのエネルギーの一部を価電子帯の電子に与
え、この電子が伝導帯に励起される事により、新たに電
子・正孔対が生じる。この電子・正孔対も加速されるこ
とにより、別の電子・正孔対が生成される。この現象が
繰り返されることにより、高電界の空乏層内でなだれの
様に急速な電荷の増加が起こり降伏状態となる。これが
アバランシェ降伏である。When a reverse bias is applied to the PN junction, the depletion layer expands and a high electric field is applied in the depletion layer. The electron-hole pairs generated in the depletion layer are accelerated by the high electric field and have an energy of 1.5 times the band gap or more.
Then, a part of the energy is given to the electron in the valence band, and this electron is excited in the conduction band to newly generate an electron-hole pair. This electron / hole pair is also accelerated to generate another electron / hole pair. By repeating this phenomenon, a rapid increase in charge occurs like avalanche in the high electric field depletion layer, and a breakdown state occurs. This is the avalanche surrender.
【００１５】ところで、アバランシェ降伏は前述の性質
上、ＰＮ接合の中でも高電界がかかるところで起こりや
すい。特に、縦型ＭＯＳ電界効果トランジスタ１００
は、Ｐ型ボディー領域１０４の周辺部のＰＮ接合領域が
曲率を持っているために、この曲率部分１１０に電界が
集中する。By the way, avalanche breakdown is likely to occur in a PN junction where a high electric field is applied due to the above-mentioned property. In particular, the vertical MOS field effect transistor 100
Since the PN junction region around the P-type body region 104 has a curvature, the electric field concentrates on this curvature portion 110.
【００１６】よって、アバランシェ降伏は主にＰ型ボデ
ィー領域１０４の周辺接合部の曲率部分１１０で起こ
る。そして降伏による電流は、Ｐ型ボディー領域１０４
の周辺接合部の曲率部分１１０より、Ｎ＋型ソース領域
１０６の底部のＰ型ボディー領域１０４にある寄生抵抗
５０７を通り、ソース電極１０９へと流れる。降伏によ
る電流が寄生抵抗５０７を通るため、そこで電圧降下が
生じる。よって、Ｐ型ボディー領域１０４の周辺接合部
の曲率部分１１０がソース電極１０９に比べ電位が高く
なる。Therefore, the avalanche breakdown mainly occurs at the curved portion 110 of the peripheral junction of the P-type body region 104. The current due to the breakdown is applied to the P type body region 104.
Flows from the curved portion 110 of the peripheral junction portion to the source electrode 109 through the parasitic resistance 507 in the P type body region 104 at the bottom of the N + type source region 106. Since the current due to breakdown passes through the parasitic resistance 507, a voltage drop occurs there. Therefore, the potential of the curved portion 110 of the peripheral junction of the P-type body region 104 becomes higher than that of the source electrode 109.
【００１７】ソース電極１０９とＮ＋型ソース領域１０
６とは同電位であるため、結果としてＰ型ボディー領域
１０４の周辺接合部の曲率部分１１０とＮ＋型ソース領
域１０６とが形成するＰＮ接合には順バイアスがかかる
ことになる。Source electrode 109 and N + type source region 10
Since 6 has the same potential, as a result, a forward bias is applied to the PN junction formed by the curved portion 110 of the peripheral junction of the P type body region 104 and the N + type source region 106.
【００１８】この状態はＮ＋型ソース領域１０６をエミ
ッタ、Ｐ型ボディー領域１０４をベース、Ｎ−型エピタ
キシャル層１０３をコレクタとする寄生バイポーラトラ
ンジスタ５０５を導通させる条件に等しい。This state is equivalent to the condition that the parasitic bipolar transistor 505 having the N + type source region 106 as the emitter, the P type body region 104 as the base, and the N − type epitaxial layer 103 as the collector is made conductive.
【００１９】これより、一旦寄生バイポーラトランジス
タ５０５が導通してしまうと、アバランシェ降伏による
電流は、制御不可能な状態となって寄生バイポーラトラ
ンジスタ５０５を通って流れ（すなわち、電流はドレイ
ン領域１０１からＮ−型エピタキシャル層１０３を通り
Ｐ型ボディー領域１０４の周辺接合部の曲率部分１１０
を流れＮ＋型ソース領域１０６に至る）、結果的に縦型
ＭＯＳ電界効果トランジスタ１００が破壊されてしま
う。Therefore, once the parasitic bipolar transistor 505 becomes conductive, the current due to the avalanche breakdown flows in an uncontrollable state through the parasitic bipolar transistor 505 (that is, the current flows from the drain region 101 to the N region). A curved portion 110 passing through the − type epitaxial layer 103 and a peripheral junction of the P type body region 104.
Flowing to the N + type source region 106), resulting in destruction of the vertical MOS field effect transistor 100.
【００２０】[0020]
【発明が解決しようとする課題】前述したように、従来
の縦型ＭＯＳ電界効果トランジスタ１００は、ソース・
ドレイン間に高電圧が印加された場合に、アバランシェ
降伏は主にＰ型ボディー領域１０４の周辺接合部の曲率
部分１１０で起こり、電流はＮ＋型ソース領域１０６の
底部のＰ型ボディー領域１０４を通りソース電極１０９
へと流れる。As described above, the conventional vertical MOS field effect transistor 100 has
When a high voltage is applied between the drains, the avalanche breakdown mainly occurs at the curved portion 110 of the peripheral junction of the P type body region 104, and the current flows through the P type body region 104 at the bottom of the N + type source region 106. Street source electrode 109
Flows to.
【００２１】このため、Ｐ型ボディー領域１０４の周辺
接合部の曲率部分１１０とソース電極１０９との間に、
寄生抵抗５０７による電圧降下により電位差が生じ、寄
生バイポーラトランジスタ５０５が導通し、これにより
素子が破壊されてしまう。このように従来の縦型ＭＯＳ
電界効果トランジスタ１００は、アバランシェ降伏に対
して無防備で破壊に至り易い欠点があった。Therefore, between the curved portion 110 of the peripheral junction of the P-type body region 104 and the source electrode 109,
A potential difference occurs due to the voltage drop due to the parasitic resistance 507, and the parasitic bipolar transistor 505 becomes conductive, which destroys the element. Thus, the conventional vertical MOS
The field-effect transistor 100 has a defect that it is vulnerable to avalanche breakdown and is easily damaged.
【００２２】本発明は、このような従来の課題に鑑みな
されたものであり、その目的は、アバランシェ降伏時に
素子で消費可能な最大エネルギーであるアバランシェ耐
量が大きく、破壊に対する耐性の高い縦型ＭＯＳ電界効
果トランジスタを得ることにある。The present invention has been made in view of the above conventional problems, and an object thereof is a vertical MOS having a large avalanche withstand capacity, which is the maximum energy that can be consumed by an element at the time of avalanche breakdown, and has a high resistance to breakage. To obtain a field effect transistor.
【００２３】[0023]
【課題を解決するための手段及び作用】請求項１の発明 前記目的を達成するため、本発明の縦型ＭＯＳ電界効果
トランジスタは、半導体基板の一面側に形成された第１
の導電型のドレイン領域と、前記ドレイン領域の表面に
形成されたドレイン電極と、前記半導体基板の他面側に
形成された第１の導電型のエピタキシャル層と、前記エ
ピタキシャル層の表面に絶縁膜を介して形成されたゲー
ト電極と、前記ゲート電極裏面側の前記エピタキシャル
層領域を挟みかつその一部が前記ゲート電極裏面側に位
置するよう、前記エピタキシャル層に形成された第２の
導電型のボディー領域と、前記ボディー領域の表面側の
一部に形成された第１の導電型のソース領域と、前記ソ
ース領域を含むボディー領域の表面に形成されたソース
電極と、前記ゲート電極裏面側の前記ボディー領域の表
面側のチャネル領域と、前記ボディー領域に挾まれた前
記エピタキシャル層中に形成された第２の導電型の半導
体領域とを含むことを特徴とする。Means and operation for solving the problems] To achieve the invention the object of claim 1, a vertical type MOS field-effect transistor of the present invention, first formed on one surface side of the semiconductor substrate
Conductive type drain region, a drain electrode formed on the surface of the drain region, a first conductive type epitaxial layer formed on the other surface side of the semiconductor substrate, and an insulating film on the surface of the epitaxial layer. Of the second conductivity type formed in the epitaxial layer so that the gate electrode formed via the gate electrode and the epitaxial layer region on the back side of the gate electrode are sandwiched and a part of the region is located on the back side of the gate electrode. A body region, a first conductivity type source region formed on a part of the front surface side of the body region, a source electrode formed on the surface of the body region including the source region, and a gate electrode rear surface side A channel region on the surface side of the body region and a second conductivity type semiconductor region formed in the epitaxial layer sandwiched by the body region. The features.
【００２４】本発明によれば、図６に示すようにＰ−型
半導体領域１２０を形成することにより、逆バイアス時
では、ゲート電極１０８下のＰ型ボディー領域１０４と
Ｎ−型エピタキシャル層１０３との間（以下、これをＰ
型ボディー領域１０４周辺の接合部１１０と呼ぶ）の空
乏層６０１の幅ｄ1 が、ソース電極１０９下のＰ型ボデ
ィー領域１０４とＮ−型エピタキシャル層１０３との間
（以下、これをＰ型ボディー領域１０４中央の接合部１
１２と呼ぶ）の空乏層６０１の幅ｄ2 よりも広くなる。According to the present invention, by forming the P − type semiconductor region 120 as shown in FIG. 6, the P type body region 104 and the N − type epitaxial layer 103 under the gate electrode 108 are reverse-biased. Between (hereinafter, P
The width d1 of the depletion layer 601 at the junction 110 around the type body region 104 is between the P type body region 104 and the N − type epitaxial layer 103 below the source electrode 109 (hereinafter, this is the P type body region). 104 central junction 1
(12) of the depletion layer 601.
【００２５】この様子は図６中の破線６０４で示され
る。これは逆バイアス時のＰ型ボディー領域１０４及び
Ｐ−型半導体領域１２０とＮ−型エピタキシャル層１０
３との間に生じる空乏層の内、Ｎ−型エピタキシャル層
１０３側の空乏層端６０４を示したものである。This state is shown by a broken line 604 in FIG. This is because the P-type body region 104 and the P − type semiconductor region 120 and the N − type epitaxial layer 10 are reverse biased.
3 shows the depletion layer edge 604 on the N − type epitaxial layer 103 side among the depletion layers generated between the depletion layer 3 and the depletion layer 3.
【００２６】これにより、Ｐ型ボディー領域１０４周辺
の接合部１１０への電界集中が緩和されるので、Ｐ型ボ
ディー領域１０４中央の接合部１１２のアバランシェ降
伏電圧はＰ型ボディー領域１０４周辺の接合部１１０の
アバランシェ降伏電圧より小さくできる。これにより、
アバランシェ降伏はＰ型ボディー領域１０４中央の接合
部１１２で起こる。As a result, the electric field concentration on the junction 110 around the P-type body region 104 is relaxed, so that the avalanche breakdown voltage of the junction 112 at the center of the P-type body region 104 is the junction around the P-type body region 104. It can be smaller than the avalanche breakdown voltage of 110. This allows
Avalanche breakdown occurs at the junction 112 in the center of the P-type body region 104.
【００２７】ここで、アバランシェ降伏が起こる場所に
よる違いを、アバランシェ降伏による電流（太い矢印で
示す）の流れる形態によって考える。Here, the difference depending on the place where the avalanche breakdown occurs is considered by the form of the current (shown by a thick arrow) due to the avalanche breakdown.
【００２８】従来の縦型ＭＯＳ電界効果トランジスタ
は、Ｐ型ボディー領域１０４周辺の接合部１１０のＡ
点、Ｂ点で降伏が起こり、Ｎ＋型ソース領域１０６裏面
側を降伏電流が流れることにより、寄生バイポーラトラ
ンジスタが動作して破壊してしまう。In the conventional vertical MOS field effect transistor, the A of the junction 110 around the P-type body region 104 is used.
Breakdown occurs at points B and B, and a breakdown current flows through the back surface side of the N + type source region 106, causing the parasitic bipolar transistor to operate and be destroyed.
【００２９】しかし、Ｐ−型半導体領域１２０の存在す
ることによって、Ｐ型ボディー領域１０４中央の接合部
１１２においてアバランシェ降伏が発生し、その降伏に
よる電流はＰ型ボディー領域１０４中央の接合部１１２
のＣ点を起点として流れる。つまり、降伏電流はＮ＋型
ソース領域１０６下を通ること無くＰ型ボディー領域１
０４を介してソース電極１０９に流れる。However, the presence of the P -- type semiconductor region 120 causes an avalanche breakdown at the junction 112 at the center of the P-type body region 104, and the current due to the breakdown causes a current to occur at the junction 112 at the center of the P-type body region 104.
Flow starts from point C of. That is, the breakdown current does not pass under the N + type source region 106, and the P type body region 1
Flowing to the source electrode 109 via 04.
【００３０】このためＰ型ボディー領域１０４の周辺部
１１０とソース電極１０９との間の寄生抵抗による電圧
降下が発生せず、順バイアスされる電位差が生じないの
で、寄生バイポーラトランジスタは導通することが無
い。Therefore, a voltage drop due to a parasitic resistance between the peripheral portion 110 of the P-type body region 104 and the source electrode 109 does not occur, and a potential difference for forward bias does not occur, so that the parasitic bipolar transistor can be turned on. There is no.
【００３１】このように、アバランシェ降伏による電流
を積極的にＰ型ボディー領域１０４中央の接合部１１２
からソース電極１０９に流すことによって、素子にサー
ジ電圧として加えられたエネルギーを消費するため、縦
型ＭＯＳ電界効果トランジスタ１００のアバランシェ降
伏による破壊を防止できる。Thus, the current due to the avalanche breakdown is positively applied to the junction 112 at the center of the P-type body region 104.
Since the energy applied as a surge voltage to the element is consumed by flowing the current from the source electrode 109 to the source electrode 109, the breakdown of the vertical MOS field effect transistor 100 due to the avalanche breakdown can be prevented.
【００３２】[0032]
【発明の効果】以上に説明したように、本発明によれ
ば、縦型ＭＯＳ電界効果トランジスタセルの寄生バイポ
ーラトランジスタを導通させることが無くなり、素子を
破壊から保護することができ、特にインダクタンス負荷
下での素子動作時の破壊に対する耐性が向上するという
利点を有する。As described above, according to the present invention, the parasitic bipolar transistor of the vertical MOS field effect transistor cell is not made conductive, and the element can be protected from destruction, especially under the inductance load. This has the advantage that the resistance to destruction during the operation of the device is improved.
【００３３】請求項２の発明 請求項２の発明の縦型ＭＯＳ電界効果トランジスタは、
請求項１において、前記第２の導電型の半導体領域がゲ
ート電極裏面側の前記エピタキシャル層の表面に接して
いないことを特徴とする。[0033]Invention of Claim 2 The vertical MOS field effect transistor according to the invention of claim 2 is
The semiconductor region of the second conductivity type according to claim 1, wherein
Contact the surface of the epitaxial layer on the back side of the gate electrode
It is characterized by not having.
【００３４】これにより、前記第２の導電型の半導体領
域を狭くし、電子がここを通るときに生じる抵抗成分を
小さくでき、この結果、素子のオン抵抗をより小さく抑
さえることができる。As a result, the second-conductivity-type semiconductor region can be narrowed, and the resistance component generated when electrons pass therethrough can be reduced. As a result, the on-resistance of the device can be suppressed to a smaller value.
【００３５】[0035]
【実施例】以下に本発明を適用した実施例を図１、図２
を参照しながら詳細に説明する。なお、前述した従来技
術と対応する部材には、同一符号を付し、その説明は省
略する。第１実施例 図１は、本発明の第１の実施例であるＮチャネル縦型Ｍ
ＯＳ電界効果トランジスタ１００の１セルの模型断面図
である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The embodiments to which the present invention is applied are shown in FIGS.
Will be described in detail with reference to. The members corresponding to those of the above-described conventional technique are designated by the same reference numerals, and the description thereof will be omitted. First Embodiment FIG. 1 shows an N-channel vertical type M which is a first embodiment of the present invention.
2 is a model cross-sectional view of one cell of the OS field effect transistor 100. FIG.
【００３６】この縦型ＭＯＳ電界効果トランジスタ１０
０は、その半導体基板のＮ＋型領域である裏面側をドレ
イン領域１０１として使用し、裏面にはドレイン電極１
０２が形成されている。This vertical MOS field effect transistor 10
0 uses the back surface side which is the N + type area of the semiconductor substrate as the drain area 101, and the back surface has the drain electrode 1
02 is formed.
【００３７】また、半導体基板の表面側にはＮ−型エピ
タキシャル層１０３が形成されている。このＮ−型エピ
タキシャル層１０３の表面には、シリコン酸化膜からな
るゲート酸化膜１０７を介して多結晶シリコンのゲート
電極１０８が配置されている。さらに、前記Ｎ−型エピ
タキシャル１０３の表面側の一部に、前記ゲート電極１
０８の直下の領域を挾むようにしてＰ型ボディー領域１
０４が形成されている。このＰ型ボディー領域１０４は
その表面側の一部にＮ＋型ソース領域１０６が形成さ
れ、これによりゲート電極１０８の周縁直下に位置する
Ｐ型ボディー領域１０４の表面側の領域が、チャネル領
域１０５として機能するように構成されている。そし
て、Ｐ型ボディー領域１０４とＮ＋型ソース領域１０６
の両方にコンタクトするよう、それらの表面にはソース
電極１０９が形成されている。An N -- type epitaxial layer 103 is formed on the front surface side of the semiconductor substrate. A gate electrode 108 made of polycrystalline silicon is arranged on the surface of the N − type epitaxial layer 103 via a gate oxide film 107 made of a silicon oxide film. Further, the gate electrode 1 is formed on a part of the surface side of the N − type epitaxial layer 103.
P-type body region 1 so as to sandwich the region immediately below 08
04 are formed. An N + type source region 106 is formed on a part of the surface side of the P type body region 104, so that the region on the surface side of the P type body region 104 located immediately below the peripheral edge of the gate electrode 108 is the channel region 105. Is configured to function as. Then, the P type body region 104 and the N + type source region 106
Source electrodes 109 are formed on their surfaces so as to contact both of them.
【００３８】また、この縦型ＭＯＳ電界効果トランジス
タ１００には、ゲート電極１０８直下のＮ−型エピタキ
シャル層１０３表面より、左右のＰ型ボディー領域１０
４から等距離になるようにＰ−型半導体領域１２０が形
成され、このＰ−型半導体領域１２０にはＰ型ボディー
領域１０４に比べて低濃度に不純物がドープされてい
る。このような構成とすることにより、逆バイアス時に
は、図６に示すようにＰ型ボディー領域１０４周辺の接
合部１１０の空乏層６０１の幅が、Ｐ型ボディー領域１
０４中央の接合部１１２の空乏層６０１の幅よりも広く
なる。In the vertical MOS field effect transistor 100, the P-type body regions 10 on the left and right of the surface of the N -- type epitaxial layer 103 immediately below the gate electrode 108 are also included.
P 4 to be equidistant - -type semiconductor region 120 is formed, the P - The type semiconductor region 120 is an impurity in the low concentration doped than the P-type body region 104. With such a configuration, when the reverse bias is applied, the width of the depletion layer 601 of the junction 110 around the P-type body region 104 becomes smaller than that of the P-type body region 1 as shown in FIG.
04 The width is wider than the width of the depletion layer 601 of the central junction 112.
【００３９】よって、Ｐ型ボディー領域１０４中央の接
合部１１２のアバランシェ降伏電圧はＰ型ボディー領域
１０４周辺の接合部１１０のアバランシェ降伏電圧より
小さくできる。Therefore, the avalanche breakdown voltage of the junction 112 at the center of the P-type body region 104 can be made smaller than the avalanche breakdown voltage of the junction 110 around the P-type body region 104.
【００４０】すると、アバランシェ降伏はＰ型ボディー
領域１０４中央の接合部１１２で発生し、その降伏によ
る電流は、Ｎ＋型ソース領域１０６下を通ること無くＰ
型ボディー領域１０４を介してソース電極１０９に流れ
る。Then, the avalanche breakdown occurs at the junction 112 at the center of the P-type body region 104, and the current due to the breakdown does not pass under the N + -type source region 106.
It flows to the source electrode 109 through the mold body region 104.
【００４１】このため、Ｐ型ボディー領域１０４の周辺
部１１０とソース電極１０９との間の電圧降下が発生せ
ず、順バイアスされる電位差が生じないので寄生バイポ
ーラトランジスタ（図５参照）は導通することが無い。For this reason, no voltage drop occurs between the peripheral portion 110 of the P-type body region 104 and the source electrode 109, and a potential difference for forward bias does not occur, so that the parasitic bipolar transistor (see FIG. 5) becomes conductive. There is nothing.
【００４２】このように、アバランシェ降伏による電流
を、積極的にＮ＋型ソース領域１０６下でないＰ型ボデ
ィー領域１０４から、ソース電極１０９に流すことによ
って、縦型ＭＯＳ電界効果トランジスタ１００はアバラ
ンシェ降伏による破壊に至ることはない。As described above, by positively flowing the current due to the avalanche breakdown from the P type body region 104 not under the N + type source region 106 to the source electrode 109, the vertical MOS field effect transistor 100 is caused by the avalanche breakdown. There is no destruction.
【００４３】従来の、縦型ＭＯＳ電界効果トランジスタ
のゲートがオン状態の場合の電子の流れは、Ｎ＋型ソー
ス領域１０６からＰ型ボディー領域１０４周辺部分に形
成されるチャネル領域１０５を通りＮ−型エピタキシャ
ル層１０３内を放射状に流れてドレインに至る。The flow of electrons when the gate of the conventional vertical MOS field effect transistor is in the ON state passes from the N + type source region 106 to the channel region 105 formed in the peripheral portion of the P type body region 104 and N −. It flows radially in the type epitaxial layer 103 to reach the drain.
【００４４】ところで、第１実施例の場合、Ｐ−型半導
体領域１２０が電子の流れを妨げる事がない程度に低濃
度であるので、Ｐ−型半導体領域１２０の存在によって
も、電子はＰ−型半導体領域１２０を通りＮ−型エピタ
キシャル層１０３内を放射状に近い状態で流れてドレイ
ンに至る。この時、Ｐ−型半導体領域１２０の抵抗成分
により、若干オン抵抗が増加するが、オン状態の素子特
性は、従来の縦型ＭＯＳ電界効果トランジスタに比べ変
化が少ない。By the way, in the case of the first embodiment, since the P − type semiconductor region 120 has such a low concentration that it does not hinder the flow of electrons, the presence of the P − type semiconductor region 120 causes the electrons to be P −. It flows through the type semiconductor region 120 in the N − type epitaxial layer 103 in a state close to a radial state and reaches the drain. At this time, the on-resistance is slightly increased due to the resistance component of the P − type semiconductor region 120, but the device characteristics in the on-state change less than those of the conventional vertical MOS field effect transistor.
【００４５】この第１実施例では、Ｐ−型半導体領域１
２０を形成することにより、アバランシェ降伏時に素子
で消費可能な最大エネルギーであるアバランシェ耐量
は、従来の縦型ＭＯＳ電界効果トランジスタに比べて、
約２倍の増大が見られた。In the first embodiment, the P -- type semiconductor region 1 is used.
By forming 20, the avalanche withstand capability, which is the maximum energy that can be consumed by the element at the time of avalanche breakdown, is higher than that of the conventional vertical MOS field effect transistor.
An approximately 2-fold increase was seen.
【００４６】以上の説明では、Ｎチャネル縦型ＭＯＳ電
界効果トランジスタについて記述してあるが、この発明
はＰチャネル縦型ＭＯＳ電界効果トランジスタにも同様
にして適用できることは明らかである。第２実施例 図２は本発明の第２の実施例であるＮチャネル縦型ＭＯ
Ｓ電界効果トランジスタの１セルの模型断面図である。
なお、前記第１実施例と対応する部材には、同一符号を
付し、その説明は省略する。In the above description, the N-channel vertical MOS field effect transistor is described, but it is obvious that the present invention can be similarly applied to the P-channel vertical MOS field effect transistor. Second Embodiment FIG. 2 is an N-channel vertical MO that is a second embodiment of the present invention.
It is a model cross section of 1 cell of an S field effect transistor.
The members corresponding to those in the first embodiment are designated by the same reference numerals, and the description thereof will be omitted.
【００４７】本実施例の縦型ＭＯＳ電界効果トランジス
タ１００には、Ｐ−型埋め込み層２１０が、ゲート電極
１０８とＮ＋型ドレイン領域１０１との間のＮ−型エピ
タキシャル層１０３内で、左右のＰ型ボディー領域１０
５から等距離で、かつ底部がほぼＰ型ボディー領域１０
４の底部と等しくなるように形成されている。このＰ−
型埋め込み層２１０には、Ｐ型ボディー領域１０４に比
べて低濃度に不純物がドープされている。In the vertical MOS field effect transistor 100 of this embodiment, the P − type buried layer 210 is formed on the left and right sides in the N − type epitaxial layer 103 between the gate electrode 108 and the N + type drain region 101. P-type body region 10
5 is equidistant and the bottom is substantially P-type body region 10
4 is formed so as to be equal to the bottom portion. The P -
The type buried layer 210 is doped with impurities at a lower concentration than the P type body region 104.
【００４８】従来の縦型ＭＯＳ電界効果トランジスタ
は、Ｐ型ボディー領域１０４周辺の接合部１１０で降伏
が起こり、Ｎ＋型ソース領域１０６直下をアバランシェ
降伏による電流が流れて寄生バイポーラトランジスタが
動作して破壊してしまう。In the conventional vertical MOS field effect transistor, breakdown occurs at the junction 110 around the P type body region 104, and a current due to avalanche breakdown flows just below the N + type source region 106 to operate the parasitic bipolar transistor. Will destroy.
【００４９】しかしＰ−型埋め込み層２１０の存在する
ことによって、Ｐ型ボディー領域１０４周辺の接合部１
１０の空乏層幅が、Ｐ型ボディー領域１０４中央の接合
部１１２の空乏層幅に比べて広くなる。However, due to the presence of the P -- type buried layer 210, the junction 1 around the P-type body region 104 is formed.
The width of the depletion layer 10 is wider than that of the junction 112 at the center of the P-type body region 104.
【００５０】これにより、Ｐ型ボディー領域１０４中央
の接合部１１２においてアバランシェ降伏が発生し、そ
の降伏による電流はＮ＋型ソース領域１０６下を通るこ
と無くＰ型ボディー領域１０４を介してソース電極１０
９に流れる。つまり、降伏電流はＰ型ボディー領域１０
４中央の接合部１１２を起点として流れるので、素子を
破壊に至らせることはない。As a result, avalanche breakdown occurs at the junction 112 in the center of the P-type body region 104, and the current due to the breakdown does not pass under the N + -type source region 106, but through the P-type body region 104.
It flows to 9. That is, the breakdown current is the P-type body region 10
4 Since the flow starts from the junction 112 at the center, the element will not be destroyed.
【００５１】なお、第２実施例の縦型ＭＯＳ電界効果ト
ランジスタのゲートがオン状態の場合、Ｐ−型埋め込み
層２１０が電子の流れを妨げる事がない程度に低濃度で
あるので、Ｐ−型埋め込み層２１０の存在によっても電
子はＮ−型エピタキシャル層１０３内を放射状に近い状
態で流れてドレインに至る。この時、第１実施例のＰ−
型半導体領域１２０に比べ第２実施例のＰ−型埋め込み
層２１０はＰ−型半導体の領域が狭いため、電子がここ
を通るときに生じる抵抗成分も小さくなる。[0051] Incidentally, when the gate of the vertical MOS field effect transistor of the second embodiment is on, P - since -type buried layer 210 is at a low concentration to the extent it is not to impede the flow of electrons, P - -type Due to the presence of the buried layer 210, the electrons flow in the N − type epitaxial layer 103 in a nearly radial state and reach the drain. At this time, P − of the first embodiment
-Type semiconductor region 120 P of the second embodiment compared with the - type buried layer 210 is P - for type semiconductor region is narrow, also decreases the resistance component generated when electrons pass through here.
【００５２】よって素子のオン抵抗は、第１実施例の場
合に比べて小さく抑さえることができる。これによりオ
ン状態の素子特性は、第１実施例に比べ変化が少なく、
従来の縦型ＭＯＳ電界効果トランジスタに近づく。Therefore, the on-resistance of the element can be suppressed smaller than that of the first embodiment. As a result, the element characteristics in the ON state are less changed than in the first embodiment,
It approaches a conventional vertical MOS field effect transistor.
【００５３】この第２実施例では、Ｐ−型埋め込み層２
１０を形成することにより、アバランシェ降伏時に素子
で消費可能な最大エネルギーであるアバランシェ耐量
は、従来の縦型ＭＯＳ電界効果トランジスタに比べて約
２倍の増大が見られた。In the second embodiment, the P -- type buried layer 2 is used.
By forming No. 10, the avalanche withstand capability, which is the maximum energy that can be consumed by the device at the time of avalanche breakdown, was found to be about twice as large as that of the conventional vertical MOS field effect transistor.
【００５４】以上の説明ではＮチャネル縦型ＭＯＳ電界
効果トランジスタについて記述してあるが、この発明は
Ｐチャネル縦型ＭＯＳ電界効果トランジスタにも同様に
して適用できることは明らかである。Although the above description has described the N-channel vertical MOS field effect transistor, it is obvious that the present invention can be similarly applied to the P-channel vertical MOS field effect transistor.
【図１】図１は本発明の第１実施例の縦型ＭＯＳ電界効
果トランジスタの断面図である。FIG. 1 is a sectional view of a vertical MOS field effect transistor according to a first embodiment of the present invention.
【図２】図２は本発明の第２実施例の縦型ＭＯＳ電界効
果トランジスタの断面図である。FIG. 2 is a sectional view of a vertical MOS field effect transistor according to a second embodiment of the present invention.
【図３】図３は従来の縦型ＭＯＳ電界効果トランジスタ
の例を示す断面図である。FIG. 3 is a sectional view showing an example of a conventional vertical MOS field effect transistor.
【図４】図４は縦型ＭＯＳ電界効果トランジスタを用い
たスイッチング回路の一例を示す図である。FIG. 4 is a diagram showing an example of a switching circuit using a vertical MOS field effect transistor.
【図５】図５は従来の縦型ＭＯＳ電界効果トランジスタ
の寄生素子を示す断面図である。FIG. 5 is a sectional view showing a parasitic element of a conventional vertical MOS field effect transistor.
【図６】図６は、本発明の縦型ＭＯＳ電界効果トランジ
スタの動作説明図である。FIG. 6 is an operation explanatory diagram of the vertical MOS field effect transistor of the present invention.
１０１ Ｎ＋型ドレイン領域 １０２ ドレイン電極 １０３ Ｎ−型エピタキシャル層 １０４ Ｐ型ボディー領域 １０５ チャネル領域 １０６ Ｎ＋型ソース領域 １０７ ゲート絶縁膜 １０８ ゲート電極 １０９ ソース電極 １２０ Ｐ−型半導体領域 ２１０ Ｐ−型埋め込み層101 N + type drain region 102 Drain electrode 103 N − type epitaxial layer 104 P type body region 105 Channel region 106 N + type source region 107 Gate insulating film 108 Gate electrode 109 Source electrode 120 P − type semiconductor region 210 P − type buried layer
Claims (2)
導電型のドレイン領域と、 前記ドレイン領域の表面に形成されたドレイン電極と、 前記半導体基板の他面側に形成された第１の導電型のエ
ピタキシャル層と、 前記エピタキシャル層の表面に絶縁膜を介して形成され
たゲート電極と、 前記ゲート電極裏面側の前記エピタキシャル層領域を挟
みかつその一部が前記ゲート電極裏面側に位置するよ
う、前記エピタキシャル層に形成された第２の導電型の
ボディー領域と、 前記ボディー領域の表面側の一部に形成された第１の導
電型のソース領域と、 前記ソース領域を含むボディー領域の表面に形成された
ソース電極と、 前記ゲート電極裏面側の前記ボディー領域の表面側のチ
ャネル領域と、 前記ボディー領域に挾まれた前記エピタキシャル層中に
形成された第２の導電型の半導体領域とを含むことを特
徴とする縦型ＭＯＳ電界効果トランジスタ。1. A drain region of a first conductivity type formed on one side of a semiconductor substrate, a drain electrode formed on the surface of the drain region, and a first region formed on the other side of the semiconductor substrate. A conductive-type epitaxial layer, a gate electrode formed on the surface of the epitaxial layer via an insulating film, and the epitaxial layer region on the back side of the gate electrode is sandwiched and a part thereof is located on the back side of the gate electrode. A second conductivity type body region formed in the epitaxial layer, a first conductivity type source region formed in a part of the body region on the surface side, and a body region including the source region. A source electrode formed on the surface of the gate electrode, a channel region on the front surface side of the body region on the back surface side of the gate electrode, and the epitaxial layer sandwiched by the body region. Vertical MOS field effect transistor, characterized in that it comprises a second conductivity type semiconductor region formed in the layer.
記エピタキシャル層の表面に接していないことを特徴と
する縦型ＭＯＳ電界効果トランジスタ。2. The vertical MOS field effect transistor according to claim 1, wherein the second conductive type semiconductor region is not in contact with the surface of the epitaxial layer on the back surface side of the gate electrode.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5246434A JPH0778978A (en) | 1993-09-07 | 1993-09-07 | Vertical mosfet transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP5246434A JPH0778978A (en) | 1993-09-07 | 1993-09-07 | Vertical mosfet transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0778978A true JPH0778978A (en) | 1995-03-20 |
Family
ID=17148426
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP5246434A Withdrawn JPH0778978A (en) | 1993-09-07 | 1993-09-07 | Vertical mosfet transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0778978A (en) |
Cited By (19)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998038681A1 (en) * | 1997-02-25 | 1998-09-03 | Siemens Aktiengesellschaft | Field effect controllable semiconductor component |
| JP2006019553A (en) * | 2004-07-02 | 2006-01-19 | Matsushita Electric Ind Co Ltd | Vertical semiconductor device |
| JP2007266133A (en) * | 2006-03-27 | 2007-10-11 | Toyota Central Res & Dev Lab Inc | Semiconductor device |
| JP2009099714A (en) * | 2007-10-16 | 2009-05-07 | Oki Semiconductor Co Ltd | Semiconductor apparatus and method of manufacturing the same |
| JP2009194164A (en) * | 2008-02-14 | 2009-08-27 | Sumitomo Electric Ind Ltd | Insulation gate type field-effect transistor and manufacturing method therefor |
| JP2011204711A (en) * | 2010-03-24 | 2011-10-13 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| JP2011258640A (en) * | 2010-06-07 | 2011-12-22 | Mitsubishi Electric Corp | Semiconductor device |
| WO2014105372A1 (en) * | 2012-12-28 | 2014-07-03 | Cree, Inc. | Semiconductor devices having reduced electric field at a gate oxide layer |
| JP2015015493A (en) * | 2014-09-12 | 2015-01-22 | ローム株式会社 | Semiconductor device |
| JP2015057851A (en) * | 2014-11-19 | 2015-03-26 | 三菱電機株式会社 | Semiconductor device |
| CN105118862A (en) * | 2015-08-24 | 2015-12-02 | 电子科技大学 | VDMOS device with anti-SEU effect |
| JP2015233141A (en) * | 2014-06-09 | 2015-12-24 | インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ | Power semiconductor device |
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| JP6237845B1 (en) * | 2016-08-24 | 2017-11-29 | 富士電機株式会社 | Vertical MOSFET and manufacturing method of vertical MOSFET |
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-
1993
- 1993-09-07 JP JP5246434A patent/JPH0778978A/en not_active Withdrawn
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1998038681A1 (en) * | 1997-02-25 | 1998-09-03 | Siemens Aktiengesellschaft | Field effect controllable semiconductor component |
| US6147381A (en) * | 1997-02-25 | 2000-11-14 | Infineon Technologies Ag | Field effect-controllable semiconductor component |
| JP2006019553A (en) * | 2004-07-02 | 2006-01-19 | Matsushita Electric Ind Co Ltd | Vertical semiconductor device |
| JP2007266133A (en) * | 2006-03-27 | 2007-10-11 | Toyota Central Res & Dev Lab Inc | Semiconductor device |
| JP2009099714A (en) * | 2007-10-16 | 2009-05-07 | Oki Semiconductor Co Ltd | Semiconductor apparatus and method of manufacturing the same |
| JP2009194164A (en) * | 2008-02-14 | 2009-08-27 | Sumitomo Electric Ind Ltd | Insulation gate type field-effect transistor and manufacturing method therefor |
| JP2011204711A (en) * | 2010-03-24 | 2011-10-13 | Toshiba Corp | Semiconductor device and method of manufacturing the same |
| US10727318B2 (en) | 2010-03-30 | 2020-07-28 | Rohm Co., Ltd. | Semiconductor device VDMOS having a gate insulating film having a high dielectric constant portion contacting the drift region for relaxing an electric field generated in the gate insulating film |
| JP2011258640A (en) * | 2010-06-07 | 2011-12-22 | Mitsubishi Electric Corp | Semiconductor device |
| US9530844B2 (en) | 2012-12-28 | 2016-12-27 | Cree, Inc. | Transistor structures having reduced electrical field at the gate oxide and methods for making same |
| US10115815B2 (en) | 2012-12-28 | 2018-10-30 | Cree, Inc. | Transistor structures having a deep recessed P+ junction and methods for making same |
| US10886396B2 (en) | 2012-12-28 | 2021-01-05 | Cree, Inc. | Transistor structures having a deep recessed P+ junction and methods for making same |
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| WO2014105372A1 (en) * | 2012-12-28 | 2014-07-03 | Cree, Inc. | Semiconductor devices having reduced electric field at a gate oxide layer |
| JP2015233141A (en) * | 2014-06-09 | 2015-12-24 | インフィネオン テクノロジーズ アーゲーＩｎｆｉｎｅｏｎ Ｔｅｃｈｎｏｌｏｇｉｅｓ Ａｇ | Power semiconductor device |
| US9577080B2 (en) | 2014-06-09 | 2017-02-21 | Infineon Technologies Ag | Power semiconductor device |
| JP2015015493A (en) * | 2014-09-12 | 2015-01-22 | ローム株式会社 | Semiconductor device |
| JP2015057851A (en) * | 2014-11-19 | 2015-03-26 | 三菱電機株式会社 | Semiconductor device |
| CN105118862A (en) * | 2015-08-24 | 2015-12-02 | 电子科技大学 | VDMOS device with anti-SEU effect |
| JP2018032741A (en) * | 2016-08-24 | 2018-03-01 | 富士電機株式会社 | Vertical mosfet and manufacturing method of vertical mosfet |
| JP6237845B1 (en) * | 2016-08-24 | 2017-11-29 | 富士電機株式会社 | Vertical MOSFET and manufacturing method of vertical MOSFET |
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