JP3491049B2 - Rectifier and driving method thereof - Google Patents

Description

Detailed Description of the Invention

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor rectifying device used for power conversion equipment and the like, and more particularly to a rectifying device applicable to high breakdown voltage and a driving method thereof.

2. Description of the Related Art Rectifiers used in power conversion equipment are required to have low on-voltage and high speed in order to reduce loss. As an element for low withstand voltage application, a Schottky diode has this characteristic and is generally used. However, when a Schottky diode is applied to a high breakdown voltage application, it becomes an element having a very high on-voltage and the loss due to the leakage current increases. Therefore, a pin type diode is usually used for a high breakdown voltage application. used. Since this pin diode utilizes the so-called conductivity modulation effect, it is possible to realize a low on-voltage even in a high breakdown voltage element. However, in the pin diode, a large reverse recovery current flows due to excess carriers due to conductivity modulation during reverse recovery. FIG. 6A shows an example of an inductive load switching circuit in which a pin type diode is applied to a free wheel diode, and FIG. 6B shows a current change during reverse recovery. In FIG. 6A, an insulated gate bipolar transistor (hereinafter referred to as an IGBT) 12 as a switching element is connected in series with the main power supply 18 and the load inductor 17. A freewheel diode pin diode 11 is connected in parallel with the load inductor 17. 13 is an IGBT drive circuit, 20
Is the stray inductance Ls of the circuit. Now, for example, when the IGBT 12 is turned on for a certain period of time, the load inductor 1
A current I _L determined by the inductance of 7, the voltage of the main power supply and the ON period flows. Here, when the IGBT 12 is turned off, the current flowing in the load inductor 17 is maintained by the inductive effect of the load inductor 17, and the diode 1
A forward current I _F flows in 1. That is, this diode 11
Operates as a freewheel diode. Figure 6 (b)
Indicates the change in current when the IGBT 12 is turned on again from this state, and the solid line indicates the current I of the diode 11.
_F and the broken line show the waveform of the current I _C of the IGBT 12. Now, when the IGBT 12 is turned on at time t ₀ , a part of the current flowing in the diode 11 until now is
12 and IGBT 12 at the current increase rate (di / dt) determined by the stray inductance 20 of the circuit. After the current I _F of the diode 11 becomes 0 at time t ₁ , a reverse current does not flow if it is an ideal diode, but in reality, since excess carriers exist inside the pin diode 11, a large reverse recovery occurs. A current I _rr flows. This reverse recovery current I _rr flows through the IGBT 12 in an overlapping manner with the current flowing through the load inductor 17, so that not only the loss in the diode 11 increases, but also the loss in the IGBT 12 increases. The reverse recovery current I _rr is shown in FIG.
As shown in (b), when there is no excess carrier in the diode 11, the diode abruptly attenuates.
A large electromotive force is generated in the stray inductance L _S of the wiring by i / dt. Therefore, the IGBT 12 may malfunction, and in the worst case, the IGBT 12 or the like may be destroyed. In response to such a problem, when turned on, pi
Operates as an n-diode, realizes a low on-voltage even with a high breakdown voltage element due to the conductivity modulation effect, and stops the conductivity modulation effect immediately before reverse recovery, and operates as a Schottky diode without excess carriers. As a result, the applicant of the present invention has applied for a rectifying element having a small reverse recovery current and capable of operating at high speed. [Japanese Patent Application 4-
No. 263946] FIG. 7 is a cross-sectional view of the structural example. An n layer 2 is stacked on an n ⁺ substrate 1 having a high impurity concentration,
An n epitaxial layer 62 is formed sandwiching the p buried layer 61 formed in a partial region of the layer 2. Also,
The central portion of the p buried layer 61 is connected to the p drain region 64 formed in the surface layer of the n epitaxial layer 62. Furthermore, p where the p drain region 64 is not formed
In the portion of the n epitaxial layer 62 above the buried layer 61, the p source region 63 is formed in the surface layer of the n epitaxial layer 62 with a certain distance from the p drain region 64. A gate electrode 7 made of polycrystalline silicon is provided on the surface of the n epitaxial layer 62 sandwiched between the p drain region 64 and the p source region 63 with the gate oxide film 6 interposed therebetween. The anode electrode 8 of Al alloy is ohmic-connected to the surface of the p source region 63, and p
A Schottky junction 19 is formed and connected to the surface of the n epitaxial layer 62 on the portion where the buried layer 61 is not formed. On the back surface of the n ⁺ substrate 1,
The l-alloy cathode electrode 10 is ohmic-connected. The operation of this element will be briefly described below. In a normal ON state in which the anode electrode 8 is positively biased and the cathode electrode 10 is negatively biased, a voltage is applied to the gate electrode 7 so that an inversion layer is formed on the surface of the n epitaxial layer 62 immediately below the gate electrode 7. Therefore, the p drain region 64 is electrically connected to the p source region 63. At this time, an electron current flows through the Schottky junction 19 due to the voltage applied between the anode electrode 8 and the cathode electrode 10, but the n-epitaxial layer 62 and the p-embedded layer 61 are formed.
Due to the voltage drop in the n layer 2 immediately below, the pn junction between the n layer 2 and the p buried layer 61 is forward biased, and holes are injected from the p buried layer 61 to the n layer 2. The injected holes cause so-called conductivity modulation in the n-layer 2, the concentrations of both electrons and holes increase, and the on-voltage of the rectifying element significantly decreases. On the other hand, prior to the reverse recovery process starting from t _o in FIG. 6, when a voltage is applied to the gate electrode 7 so that the inversion layer disappears from the surface of the n epitaxial layer 62 directly below the gate electrode 7, the positive voltage from the p buried layer 61 is removed. The excess carriers (electrons and holes) stopped by hole injection and increased by the conductivity modulation effect disappear by recombination. If the lifetime of the device and the timing of the voltage applied to the gate are set so that the excess carriers almost completely disappear by time t ₁ when the device is reverse biased, the reverse recovery characteristic of this device is equivalent to that of a Schottky barrier diode. Therefore, only a small reverse recovery current flows through, and switching loss can be significantly reduced. That is, it is possible to realize a low on-voltage by the bipolar operation at the time of ON and a high-speed switching characteristic by the unipolar operation at the time of OFF (reverse recovery). P buried layer 6 in FIG.
1 prevents forward biasing of the pn junction between the p source region 63 and the n-epitaxial layer 62 due to the lateral current flowing immediately below the p source region 63 during the unipolar operation. It is possible to maintain unipolar operation.

Element of Figure 7 [SUMMARY OF THE INVENTION] is effective in realizing a low on-voltage and high speed, sometimes unipolar operation (Schottky diode operation), bipolar operation by injection of minority carriers (pi n diode operation)
The structure having the p-embedded region 61 is applied in order to prevent the above process. Therefore, it is difficult to reduce the manufacturing cost. Further, since the MOSFET for controlling the injection of minority carriers is formed on the high-resistivity semiconductor layer for maintaining the device breakdown voltage, M
Punch-through of the channel part of the OSFET easily occurs,
The injection of holes starts from the p-embedded region 61, and the bipolar operation is likely to occur. In order to prevent this, measures such as introducing another impurity introduction region into the channel portion and increasing the channel length are necessary, but the former increases the process cost, and the latter increases the amount of minority carrier injection during ON. There is a drawback in that the limitation is caused and the on-voltage is increased. In view of the above problems, an object of the present invention is a rectifying element that can switch between bipolar operation and unipolar operation in order to reduce switching loss, has a structure that is easy to manufacture, and is stable in operation. And to provide a driving method thereof.

In order to solve the above problems, the rectifying device of the present invention is formed on a part of a surface layer of one main surface of a first conductivity type semiconductor layer forming a part of a semiconductor substrate. A second conductivity type well, a first conductivity type well formed in a part of the surface layer of the second conductivity type well, and a high concentration of a high concentration formed in a part of the surface layer of the first conductivity type well region. A second conductive type source region, a gate electrode formed on the surface of the first conductive type well sandwiched between the second conductive type well and the second conductive type source region via a gate insulating film, A first main electrode provided in common contact with the surfaces of the one conductivity type well and the second conductivity type source region, and a first conductivity type region in contact with the first conductivity type semiconductor layer and forming a part of a semiconductor substrate. And a second main electrode that makes ohmic contact with the surface of the It said first conductivity type semiconductor layer does not
Is the first main electrode shall be in contact to form a Schottky junction on one major surface portion. If a structure such as its, by the voltage applied to the gate electrode, it is possible to switch between bipolar operation and unipolar operation, moreover, there is no buried layer as in the conventional ones, it is easy to manufacture. In particular, a part of the surface layer of one main surface of the first conductivity type semiconductor layer in which the second conductivity type well is not formed is provided with a high-concentration second conductivity type auxiliary region, and a second conductivity type well is formed. The maximum length of the exposed surface portion of the first conductivity type semiconductor layer sandwiched between the second conductivity type auxiliary regions and between the second conductivity type auxiliary regions may be 20 μm or less. With such a structure,
The depletion layer easily spreads, and the leakage current when reverse bias is applied is small. As a driving method of the rectifying element, such as above SL, pn junction between the first conductive type semiconductor layer and the second conductivity type well,
In the case where the forward bias is constantly applied, a voltage is applied to the gate electrode so that an inversion layer is formed immediately below the gate electrode, and a predetermined time immediately before the pn junction is reverse biased from the forward direction. , A voltage is applied to the gate electrode so that the inversion layer immediately below the gate electrode disappears, and in particular,
It is important that the certain time is not less than the lifetime of minority carriers in the first conductivity type semiconductor layer. If such a method is adopted, the injected minority carriers disappear before the reverse bias is applied, and the reverse recovery current becomes small. Well
Further, in an inductive load circuit having at least four insulated gate semiconductor switching elements bridge- connected and each of the above-mentioned rectifying elements connected in antiparallel to each other, a gate and a rectifier of the insulated gate semiconductor switching element are provided. The gate of the device shall be driven by the gate drive outputs that are mutually inverted. By adopting such a method, it is possible to add an inverter and make it one that also serves as the gate drive output of both elements.

In order to solve the above-mentioned problems, the present invention provides a second conductivity type well formed in the surface layer of a first conductivity type semiconductor layer and can be turned on / off by a MOSFET structure.
It is intended to use a low on-voltage for bipolar operation and a fast reverse recovery for unipolar operation as a rectifying element that forms an in-diode and a Schottky junction on the surface of the first conductivity type semiconductor layer, and can switch them appropriately. It is intended to, a MOSFET for controlling the injection formed in the well, as well as separated from the high resistivity layer for maintaining the device breakdown voltage, the even p ⁺ source region in a large current density under even no buried layer structure It is possible to stop the injection of minority carriers. The details and the driving method thereof will be described.

Embodiments of the present invention will be described below with reference to the drawings. Note that the layers and regions bearing n and p mean layers and regions having majority carriers of electrons and holes, respectively. Example 1 FIG. 1 shows a sectional view of a rectifying element in a first example of the present invention. In FIG. 1, an n layer 22 is laminated on an n ⁺ substrate 21. A p-well 23 is formed on a part of the surface layer of the n-layer 22.
Is formed, and an n well 24 is further formed in a part of the surface layer of the p well 23. In addition, the n-well 24
A p source region 25 is formed in a part of the surface layer of. A gate electrode 27 is formed on the surface of the n well 24 sandwiched between the p source region 25 and the p well 23 with a gate oxide film 26 interposed therebetween. An anode electrode 28 is electrically connected to the surfaces of the p source region 25 and the n well 24. At the same time, the anode electrode 28 is connected to the surface of the n layer 22 by a Schottky junction 39. As the metal film forming the Schottky junction 39, Cr, T
i, W, etc. are used. Actually, a composite film is formed by stacking an Al alloy film on the metal film. On the back surface of the n ⁺ substrate 21,
A cathode electrode 30 made of Al alloy is formed.
Reference numeral 29 is a phosphor glass insulating film that insulates between the gate electrode 27 and the anode electrode 28. The p auxiliary region 31 formed in a part of the surface layer of the n region 22 has the p auxiliary region 31 and the p well 23 when a reverse bias is applied to this element.
The depletion layer extending from the pinch off the Schottky junction 39 to reduce the leakage current, and is not always necessary when the width of the Schottky junction 39 is small. Further, when it is desired to increase the width of the Schottky junction 39 for the purpose of reducing the on-voltage during the unipolar operation, it is effective to increase the number of p auxiliary regions 31. The width of the p auxiliary region 31 is the Schottky junction 3
In order not to reduce the effective area of the 9th part and to prevent the injection of minority carriers from the p auxiliary region 31 due to the voltage drop in the n layer 22 due to the electron current flowing directly under the p auxiliary region 31, it is made small. It is necessary. Further, the spacing between the p auxiliary region 31 and the p well 23 and between the p auxiliary regions 31 is 20 μm or less in order to pinch off the Schottky junction 39 by the depletion layer when a reverse voltage is applied and reduce the leakage current, Desirably 5 μm
The following is recommended. In the above rectifying element, the specific resistance of the channel region just below the gate electrode is low, punch-through of the channel of the MOSFET is hard to occur, and the channel length can be shortened sufficiently. Therefore, the injection of minority carriers at the time of ON can be increased, and the ON voltage can be reduced. Even with a structure without a buried layer, injection of minority carriers from the p source region 25 can be stopped under a large current density. The cost can be reduced by adopting a structure having no buried layer. FIG. 2 is an example in which the rectifying element of FIG. 1 is applied to a PWM inverter, and IGBT 12-1
.. 12-4 and the gates of the rectifying elements 11-1 to 11-4 of FIG. 1, drive circuits 13-1 to 13-4 and 14-1 driven by the same control circuits 16-1 to 16-4.
Driven by ~ 14-4. IGBT12-1 ~ 12
-4 and the drive circuits of the rectifying elements 11-1 to 11-4 in FIG. 1 are effective because one of them is directly connected and the other is connected via inverters 15-1 to 15-4 that invert signals. The polarity and drive timing can be obtained. FIG. 3 shows an example of this drive timing.
Easy to explain the behavior below. 3A is a gate signal of the IGBT 12-1 in FIG. 2, that is, an output signal of the drive circuit 13-1, FIG. 3B is a gate signal of the IGBT 12-2, that is, an output signal of the drive circuit 13-2, and FIG. )
Indicates the gate signal of the rectifying element 11-2, that is, the output signal of the drive circuit 14-2, and both are ± 15V.
Has an amplitude of. When the upper arm IGBT12-1 and the lower arm IGBT12-2 are turned on at the same time, the main circuit power supply is short-circuited by the two elements, so it can be seen by comparing FIG. 3 (a) and FIG. 3 (b). And usually two IGB
The gate signal of T has a period (dead time) in which both elements are turned off. This dead time is used as the transition time from the bipolar mode to the unipolar mode in the rectifying device of this embodiment. Therefore, this dead time may be set longer than the lifetime of the minority carrier. In FIG. 2, the IGBT 12-1 and the IGBT 12 are now
Consider the case where -4 is on. In this case, the power source 18
To IGBT 12-1 and 12-4 through load inductor (in actual application, inductance of motor, etc.) 1
Current flows to 7. Next, when the IGBT 12-1 is turned off, a forward current flows through the rectifying element 11-2 to maintain the current flowing through the load inductor 17. In this case, the gate voltage of the rectifying element 11-2 is IGBT12-1.
Except for a small dead time period after turning off and a small dead time before turning on the IGBT 12-1, since -15V is applied, the bipolar mode in which the on voltage is low is set. Next, when the IGBT 12-1 is turned on again, the rectifying element 11
The forward current that was flowing through the -1 is a constant current increase rate (d that is determined by the characteristics of the IGBT 12-1 and the stray inductance of the circuit as the IGBT 12-1 is turned on (d
i / dt) is transferred to the IGBT 12-1. After all the current is commutated to the IGBT12-1, the rectifying element 11-2
A reverse voltage is applied to the rectifier element 11-2 and a reverse recovery current flows through the rectifier element 11-2. However, as shown in FIG.
Since the rectifying element 11-2 is in the unipolar mode before the dead time before -1 is turned on again, excess carriers disappear and the reverse recovery current becomes a very small value. That is, the dead time period can be used as an extinguishing period due to carrier recombination. Usually, the dead time is about 1 to 4 μs, and it is not necessary to extremely shorten the lifetime of the rectifying element of this embodiment. Therefore, as compared to conventional pin diode shortened lifetime to speed, on-voltage of the rectifier device of the first embodiment of FIG. 1 can be sufficiently low. Therefore,
By controlling the carrier lifetime by adjusting the amount of the lifetime killer introduced in accordance with the dead time and the switching frequency, it becomes possible to manufacture a rectifying element with a minimum total loss. Reference Example FIG. 4 is a cross-sectional view of a rectifying device of a reference example of the present invention. The difference from the first embodiment shown in FIG. 1 is that there is no n well in the p well 43 and the n drain region. 55, n source region 52, and p ⁺ contact region 53 are formed. Further, n source region 52 and p ⁺ contact region 53
Are electrically short-circuited by the ohmic electrode 54 formed on the surface. A gate electrode 47 is formed on the surface of the p well 43 sandwiched between the n drain region 55 and the n source region 52 with a gate oxide film 46 interposed therebetween. The anode electrode 48 makes ohmic contact with the surface of the n drain region 55 and also makes contact with the surface of the n layer 42 by forming a Schottky junction 59. A p auxiliary region 51 is formed between the p wells 43 to promote the expansion of the depletion layer when a reverse bias is applied. The operation of the rectifying element is a bipolar operation at the time of ON, and a unipolar operation immediately before the reverse recovery period, whereby the concept of realizing low ON voltage and high speed switching (low reverse recovery current) is the same. However, the difference is that the MOSFET for switching between the unipolar mode and the bipolar mode is a p-channel type or an n-channel type. In the p-channel type of the first embodiment, the source region is connected to the anode electrode, whereas the n-channel type has a slight difference in operation in that the drain region is connected to the anode electrode. That is, in the p-channel type, the gate potential can be applied to the anode potential, whereas in the n-channel type, the potential of the gate electrode 47 basically needs to be applied to the floating ohmic electrode 54. different. For this reason, the p-channel type has three terminal elements, whereas the n-channel type has four terminal elements, which has a drawback that the driving circuit is complicated in application. In the case of the n-channel type, this is during the unipolar operation, that is, the n-channel MOSF.
When ET is off and the p-well 43 is in a floating state, the electron current flowing immediately below the p-well 43 causes n
When a voltage drop occurs in the layer 42, the potential of the p-well 43, that is, the potential of the source region 52 of the n-channel MOSFET follows this and decreases with respect to the potential of the anode electrode 48.
MOSF between gate and source of n-channel MOSFET
This is because the voltage is such that ET is turned on. When this phenomenon occurs, the rectifying element of this embodiment cannot maintain the unipolar operation, and the minority carrier injection is small, but the bipolar operation is performed. However, this drawback can also be avoided by proper design. Now, let V _{DROP be} the voltage drop generated in the n layer 42 immediately below the p well at the maximum current used, and n
When the gate threshold of the channel MOSFET and V _TH, if V _DROP <V _TH n-channel MO
The SFET does not turn on and can maintain unipolar operation. V _TH is applied to the gate for bipolar operation.
The above voltage may be applied. It is also possible to prevent unwanted bipolar operation by applying a negative voltage to the gate. In such a case, it can be used as a three-terminal element as in the first embodiment. FIG. 5 shows an example in which the rectifying element of this embodiment is used as a three-terminal element and is applied to a PWM inverter as in the case of FIG. In this application example, IGBTs 12-5 to 12-8
The gates of the rectifying elements 11-5 to 11-8 of this reference example are driven by the same control circuits 16-5 to 16-8 and the same drive circuits 13-5 to 13-8. Since the gate voltage for conducting the n-channel MOSFET is opposite to that of the p-channel type, there is an advantage that the drive circuits 13-5 to 13-8 of the IGBT and the rectifying element can be shared. Also in this case, the operation described with reference to FIG. 3 can be realized except that the logic of the signal applied to the gate is different. Further, as described above, if the element is designed so that V _DROP <V _TH , the signal potential of the drive circuit becomes
It can be driven only by positive voltage, not necessarily by positive and negative voltage. It can be said that this method is preferable as compared with the first embodiment because the driving voltage of the IGBT has recently been driven only by the positive voltage instead of the positive and negative voltages. Although the embodiment has been described above in the case where the substrate is the n-type, it goes without saying that it is possible to form it on the p-type substrate by exchanging p and n. It goes without saying that it is possible to form the n ⁺ layer on one surface side and the p well or the like on the other surface by diffusion of impurities using the n layer as the substrate. Further, in the reference example , the n drain region 55
Is arranged in the center of the p well 43, and the n source region 52 and the p ⁺ contact region 53 are arranged in the periphery. However, it is clear that the same effect can be obtained by reversing the structure. There are various modified structures that can achieve the same effect. Further, in the above-mentioned embodiment, the vertical electrode in which the anode electrode and the cathode electrode are formed on different main surfaces of the semiconductor substrate is shown, but it is also applicable to a so-called horizontal element in which both are formed on the same main surface. Needless to say.

As described above, according to the present invention, the second-conductivity-type well is formed in a part of the surface layer of the first-conductivity-type semiconductor layer, and the first-conductivity-type well is formed in the well. A second conductivity type source region is formed on the first conductivity type well, a gate electrode via a gate oxide film is provided on the surface of the first conductivity type well, and the second conductivity type source region and the first conductivity type well surface are commonly contacted. an anode electrode Ri by the forming the first conductivity type semiconductor layer surface and the Schottky junction may be a bipolar operation with low on-voltage, a smaller unipolar operation and rectifying element is switched to the reverse recovery current. The rectifying element of the present invention has a low specific resistance in the channel region immediately below the gate electrode,
Since punch through hardly occurs, the channel length can be shortened sufficiently. As a result, the injection of minority carriers at the time of ON can be increased, and the ON voltage can be reduced. Further, the cost can be reduced by adopting a structure that can be manufactured without complicated steps such as a buried layer. Further, as a driving method of the rectifying element of the present invention, pn
When the junction is constantly forward-biased, a voltage is applied to the gate electrode so that an inversion layer is formed immediately below the gate electrode, and the pn junction is forward biased from the forward direction for a predetermined time. Before, a voltage is applied to the gate electrode so that the inversion layer immediately below the gate electrode disappears after a certain time longer than the lifetime of minority carriers of the first conductivity type semiconductor layer. If such a method is adopted, the injected minority carriers disappear before the application of the reverse bias, so that the reverse recovery current can be reduced and the switching loss can be greatly reduced.

[Brief description of drawings]

FIG. 1 is a sectional view of a rectifying device according to a first embodiment of the present invention.

FIG. 2 is a PWM inverter circuit diagram using the rectifying element of the first embodiment.

FIG. 3 is a diagram of driving signals for an IGBT and a rectifying element in the circuit of FIG.

FIG. 4 is a sectional view of a rectifying element according to a reference example of the present invention.

FIG. 5 is a PWM inverter circuit diagram using a rectifying element of a reference example.

6A is a diagram of an inductive load circuit, and FIG. 6B is a diagram of waveforms of currents flowing in the pin diode and the switching element of FIG. 6A.

FIG. 7 is a cross-sectional view of a conventional rectifier that can switch between bipolar operation and unipolar operation.

[Explanation of symbols]

1, 21, 41 n ⁺ Substrate 2, 22, 42 n Layer 6, 26, 46 Gate oxide film 7, 27, 47 Gate electrode 8, 28, 48 Anode electrode 10, 30, 50 Cathode electrode 11 Pin diode 11-1 -11-8 Rectifying element 12 of this invention 12, 12-1 to 12-8 IGBT 13, 13-1 to 13-8 IGBT drive circuit 14-1 to 14-4 Rectifying element drive circuit 15-1 to 15- 4 inverters 16-1 to 16-8 control circuit 17 load inductor 18 main power supply 19, 39, 59 Schottky junction 20 stray inductance 23, 43 p well 24 n well 25 p source region 29 insulating film 31, 51 p auxiliary region 52 n source region 53 p ⁺ contact region 54 ohmic electrode 55 n drain region 61 p buried region 62 n epitaxial layer 63 The source region 64 p drain region

Front page continued (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 29/47 H01L 29/872 H01L 29/78 654 H01L 29/78 655

Claims (6)

(57) [Claims] 1. A well of a second conductivity type formed in a part of a surface layer of one main surface of a first conductivity type semiconductor layer forming a part of a semiconductor substrate, and a surface layer of the second conductivity type well. A first conductivity type well formed in a part, a high-concentration second conductivity type source region formed in a part of the surface layer of the first conductivity type well region, the second conductivity type well and the second region A gate electrode formed via a gate insulating film on the surface of the first conductivity type well sandwiched between the conductivity type source region and the surface of the first conductivity type well and the second conductivity type source region in common. A first main electrode provided in contact with, and a second main electrode in ohmic contact on the surface of the first conductivity type region that is in contact with the first conductivity type semiconductor layer and forms a part of the semiconductor substrate, on the one <br/> main surface portion of the first conductive type semiconductor layer where the second conductive well is not formed first Rectifying element characterized in that the main electrode is in contact to form a Schottky junction. 2. A high-concentration second-conductivity-type auxiliary region is provided in a part of the surface layer of one main surface of the first-conductivity-type semiconductor layer in which the second-conductivity-type well is not formed. Claims to
1. The rectifying element according to 1 . 3. The maximum length of the exposed surface portion of the first conductivity type semiconductor layer sandwiched between the second conductivity type well and the second conductivity type auxiliary region and between the second conductivity type auxiliary regions is 20 μm. The rectifying element according to claim 2 , wherein: 4. A gate such that an inversion layer is formed immediately below a gate electrode when a pn junction between a first conductivity type semiconductor layer and a second conductivity type well is constantly forward biased. A voltage is applied to the electrode, and a voltage is applied to the gate electrode so that the inversion layer immediately below the gate electrode disappears a certain time before the pn junction is reverse biased from the forward direction. the driving method of the rectifying element according to any one of claims 1 to 3. 5. The method of driving a rectifying device according to claim 4 , wherein the certain period of time is equal to or longer than the lifetime of minority carriers of the first conductivity type semiconductor layer. 6. A bridge-connected at least four insulated gate semiconductor switching devices, the inductive load circuit having a rectifying device according to any one of claims 1 to 3 connected in reverse parallel to each A method for driving a rectifying element, characterized in that the gate of the insulated gate semiconductor switching element and the gate of the rectifying element are driven by mutually inverted gate drive outputs.