CN105895679A - Structure and manufacturing method of insulated gate bipolar transistor - Google Patents
Structure and manufacturing method of insulated gate bipolar transistor Download PDFInfo
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- CN105895679A CN105895679A CN201510035348.9A CN201510035348A CN105895679A CN 105895679 A CN105895679 A CN 105895679A CN 201510035348 A CN201510035348 A CN 201510035348A CN 105895679 A CN105895679 A CN 105895679A
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Abstract
The invention discloses a cellular structure of an insulated gate bipolar transistor. The cellular structure at least comprises an emitter region, a collector region, a trench, a trench gate oxidation film, a polysilicon gate, a first conductivity type semiconductor drift region, a second conductivity type semiconductor well region, first conductivity type semiconductor enhanced accumulation regions arranged between the first conductivity type semiconductor drift region and the second conductivity type semiconductor well region, and second conductivity type semiconductor charge compensation regions each arranged between the adjacent first conductivity type semiconductor enhanced accumulation regions. By introducing the second conductivity type semiconductor charge compensation regions and the first conductivity type semiconductor enhanced accumulation regions, power consumption of the insulated gate bipolar transistor when the insulated gate bipolar transistor is turned on is further reduced under the condition that identical blocking voltage of the insulated gate bipolar transistor is obtained, and turn off characteristic of the device is improved. The invention further discloses a manufacturing method of the insulated gate bipolar transistor.
Description
Technical field
The present invention relates to semiconductor integrated circuit and manufacture field, particularly relate to a kind of insulated gate bipolar brilliant
The structure of body pipe；The invention still further relates to the manufacture method of a kind of igbt.
Background technology
Igbt (insulated gate bipolar transistor, IGBT) device is skilful
Achieve mos field effect transistor (Metal-Oxide-Semiconductor wonderfully
Field-Effect Transistor, MOSFET) and bipolar junction transistor (Bipolar
Junction Transistor, BJT) optimum organization, have simultaneously low energy consumption, high pressure, greatly electricity
Stream, high efficiency feature.IGBT device had become a kind of irreplaceable power electronic devices already at present,
It is widely used in the frequency conversion part in the fields, such as air-conditioning such as industry, traffic, the energy, solar energy
Electricity converts assembly, the igniter needed in automotive electronics, high pressure high-energy current transmission equipment etc..
In terms of the technology development course of IGBT device, its gone through epitaxial silicon chip punch (punch through,
PT), thin slice technique and zone melting and refining silicon non-punch (Non punch through, NPT), field cut-off type
Technological evolvement such as (field-stop, FS), device architecture also develops into groove-shaped from plane.Groove
Grid IGBT device (sees Fig. 1), due to its conducting time groove in polysilicon gate to the electricity around groove
Son is applied with a positive bias, electronically forms an accumulation area around groove, so that this region
Carrier concentration increase, reduce the conducting resistance of IGBT.
IGBT device is typically made up of electric charge flow region and termination environment, by the unit much repeated in electric charge flow region
Born of the same parents form (if the part in Fig. 1 dotted line square frame is exactly a cellular).
Fig. 1 is that (one by N-type MOSFET and a PNP for a basic structure example of cut-off type trench gate IGBT
The IGBT of bipolar transistor mixing, so corresponding to the content in claims, claims
Described in the first conduction type be here N-type, described in claims, the second conduction type is at this
In be p-type), its structure cell includes: N-type drift region 1-2, groove 3, and gate oxidation films 4 is many
Crystal silicon grid 5, p-type trap 2-1, P+ (high concentration P) injection region 2-2, N+ (high concentration N) launch site 6 (MOSFET
Source region), deielectric-coating 7, contact hole 8, front metal 9, N-type field cutoff layer 1-1, P+ (high concentration
P) collecting zone 2-3, back metal 10.P+ injection region 2-2 and N+ launch site 6 is carried out by metal electrode
Short circuit, suppression NPNP thyristor can not work, thus ensures the normal work of IGBT.
The metal electrode connecting P+ injection region 2-2 and N+ launch site 6 is emitter stage, is connected with P+ collecting zone 2-3
Back metal electrode 10 is colelctor electrode.
Fig. 2 is the foreign ion scattergram in the different areas in Fig. 1 along AA ' direction, and in figure, X-axis represents edge
The regional in AA ' direction, Y-axis represents the impurity concentration of corresponding region.P in figure, N represent corresponding district
The semiconductor type in territory.
Fig. 3 is the foreign ion scattergram in the different areas in Fig. 1 along BB ' direction, and in figure, X-axis represents edge
The regional in BB ' direction, Y-axis represents the impurity concentration of corresponding region.P in figure, N represent corresponding district
The semiconductor type in territory.
In this device architecture, in the on-state, N drift region is operated in big injection condition, minority carrier
The concentration in hole is much larger than the doping content of drift region itself, in order to keep electric neutrality, and electricity in this region
Sub-concentration is equal to hole concentration.Trench gate area below A1 the most in FIG, owing to grid is to groove
N-type drift region around applies positive bias, and the carrier concentration around groove is higher, therefore ends from field
To in the region, whole drift region around groove at layer and the knot of drift region, the overall density of carrier is relatively
High.
But for the region beyond under trench gate, such as p-type trap area below A2 in Fig. 1, due in conducting
Under state, the knot of p-type trap-N drift region is in reverse-bias state, and the carrier concentration at this knot is
Zero, this boundary condition makes in the A2 of region, and carrier concentration is from the knot (J1) of field cutoff layer Yu drift region
Locate to knot (J2) place of p-type trap-N drift region quickly to decline (shown in Figure 10-1, carrier in drift region
Concentration is distributed as shown in the inclination dotted line in 1-2 region in figure) so that the conducting resistance in this region raises,
Add the conducting power consumption of device.
In order to improve this characteristic, H.Takahashi et al. proposes a kind of charge storage type trench gate
(Carrier Stored Trench-Gate bipolar transistor, CSTBT), by P
One layer of doping content is added higher than the N-type of doping content in N-type drift region between type trap and N-type drift region
Layer (as shown in Figure 4, adds high concentration N-type layer 1-3, along AA ', BB ' direction on the basis of Fig. 1
Impurities concentration distribution is as shown in Fig. 5 and Fig. 6).In the on-state, one is formed in the region of 1-3 layer
Higher electric field intensity so that hole is near high concentration N-type layer 1-3 of N-type drift region 1-2
Accumulation, improves the carrier concentration in this region, thus improve carrier concentration in the A2 of region (as
Figure 10-2, in drift region, carrier concentration profile is as shown in the inclination dotted line in 1-2 region in figure), reduce
The conducting resistance of device.
But this device architecture has following problem, and one is as the raising of the doping content of N-type layer 1-3, device
The blocking voltage of part can decline, and therefore the raising to the impurity concentration of this layer has certain restriction, another
Aspect, due to p-type trap, (mid portion of p-type trap may have higher than the p type impurity concentration of groove adnexa
P type impurity concentration) and N-type drift region between there is N-type layer 1-3 of higher concentration, at IGBT from leading
During leading to shutoff, during conducting, in N-type drift region, p-type quickly can not be passed through in the hole of accumulation
District, to contact hole, have impact on the turn-off performance of device.
Summary of the invention
The technical problem to be solved is to provide the structure cell of a kind of IGBT, obtain same exhausted
In the case of the blocking voltage of edge grid bipolar transistor, reduce igbt further and leading
Power consumption time logical, and improve the turn-off characteristic of device.To this end, the invention also discloses a kind of insulated gate
The manufacture method of bipolar transistor.
For solving the problems referred to above, in the structure cell of the IGBT device of the present invention, including at least launching
District, collecting zone, groove, trench gate oxide-film, polysilicon gate, the quasiconductor of the first conduction type
Drift region, the quasiconductor well region of the second conduction type, it is placed in partly leading of the first conduction type described
The first conduction type between the quasiconductor well region of body drift region and described the second conduction type
Semiconductor enhancement mode accumulation area, the semiconductor enhancement mode accumulation area of adjacent the first conduction type described
Between the quasiconductor electric charge compensating region of the second conduction type.
The impurity of the first type of the semiconductor enhancement mode accumulation area of the first conduction type described is mixed
Miscellaneous concentration is more than or equal to the first conductive-type in the drift semiconductor district of the first conduction type described
2 times of the impurity doping concentration of type；
The setting of the impurity doping concentration in the quasiconductor electric charge compensating region of described the second conduction type,
Ensure impurity doping total amount and the institute of surrounding of the second conduction type of this described electric charge compensating region
State the difference of impurity doping total amount of the first conduction type of enhancement mode accumulation area less than or equal to institute
State electric charge compensating region the second conduction type impurity doping total amount 15%, again smaller than equal to week
The 15% of the impurity doping total amount of the first conduction type of the described enhancement mode accumulation area enclosed.
By the formation of the enhancement mode accumulation area of the first conduction type of this high-dopant concentration, make device
Part in the on-state, the half of the first conduction type described of described enhancement mode accumulation area area below
In conductor drift region, carrier concentration improves, thus reduces the conducting resistance of device；Meanwhile, by adopting
With the enhancement mode accumulation area of the first conduction type of high-dopant concentration so that in IGBT device
Accumulation area (1-3 ', AcAREA in Fig. 7) resistance of MOSFET reduces, and same help reduces IGBT
The conducting resistance of device.
By being formed between the semiconductor enhancement mode accumulation area of the first conduction type described in adjacent
The quasiconductor electric charge compensating region (2-4, CbAREA in Fig. 7) of the second conduction type so that device work
Make when blocking state, the electric charge compensating region of this second type and the first conduction type of surrounding
Semiconductor enhancement mode accumulation area is in reverse-bias state, will produce a transverse electric field, it is achieved PN
The having lateral depletion of knot, thus the semiconductor enhancement mode reducing the first conduction type of high-dopant concentration amasss
Tired district is to the longitudinal electric field intensity at the well region of the second conduction type and the knot of this enhancement mode accumulation area
Impact, make simultaneously the electric field intensity of this enhancement mode accumulation area and the relation of position be one trapezoidal,
Ensure that the blocking voltage of device is not because using the enhancing of the first conduction type of high-dopant concentration
Type accumulation area and reduce.Further, by controlling the quasiconductor electric charge of described the second conduction type
The semiconductor enhancement mode accumulation area of the first conduction type of impurity doping and surrounding in compensating basin
The difference of impurity doping, can amass at the semiconductor enhancement mode using the first conduction type higher
In the case of the impurity concentration in tired district, the still blocking voltage of retainer member.
By between the semiconductor enhancement mode accumulation area of the first conduction type described in adjacent
The quasiconductor electric charge compensating region of two kinds of conduction types so that device is conducting state cutting to off state
During changing, second accumulated in the drift semiconductor district of the first conduction type in the on-state
The carrier planting conduction type can be arrived by the quasiconductor electric charge compensating region of this second conduction type
Reach the contact point (at the Ohmic contact of metal and silicon) of emitter stage, reduce the shutoff energy consumption of device, change
The turn-off characteristic of kind device.
Further improve and be, the first of the semiconductor enhancement mode accumulation area of the first conduction type described
Plant the impurity doping concentration quasiconductor drift more than or equal to the first conduction type described of conduction type
5 times of the impurity doping concentration of the first conduction type in shifting district, which further increases conducting shape
Carrier concentration in the drift semiconductor district of the first conduction type and the accumulation area of MOSFET under state
Resistance, reduce the conducting resistance of device；
Further improving is that the quasiconductor electric charge compensating region of described the second conduction type can pass through
The region of the semiconductor enhancement mode accumulation area of the first conduction type described, with the first conductive-type described
The drift semiconductor district of type directly contacts；So make device in the switching of conducting state to off state
During, the second of accumulation in the drift semiconductor district of the first conduction type in the on-state
The carrier of conduction type can be easier to the quasiconductor charge compensation by this second conduction type
District arrives the contact point (at the Ohmic contact of metal and silicon) of emitter stage, reduces the pass of device further
Disconnected energy consumption, improves the turn-off characteristic of device.
Further improving is that the quasiconductor electric charge compensating region of described the second conduction type is placed in first
Among the region of the semiconductor enhancement mode accumulation area planting conduction type, partly do not lead with the first type described
The drift region of body directly contacts, and adds under conducting state below this electric charge compensating region greatly
Carrier concentration in drift region, simultaneously works as improving the effect of turn-off performance, preferably obtains conducting
Loss and the balance of switching loss, improve the motility of device design.
The manufacture method of the first igbt that the present invention provides, comprises below step:
Step one, the front deposit of silicon substrate in the drift semiconductor district with the first conduction type
One layer of epitaxial layer as the semiconductor enhancement mode accumulation area of the first conduction type；Continue deposit first
Plant the epitaxial layer of conduction type to the thickness needed；
Step 2, the epitaxial layer with the first conduction type formed in step one silicon chip on, logical
Cross photoetching and etching forms groove, then deposit gate oxidation films and polysilicon, form trench gate；
Step 3, by ion implanting and annealing formed the second conduction type quasiconductor well region；
Step 4, formed the launch site of the first conduction type by photoetching and ion implanting, and pass through
Photoetching and ion implanting form the quasiconductor electric charge compensating region of the second conduction type；
Step 5, at front side of silicon wafer deposition dielectric film, form contact hole by chemical wet etching, by from
Son injects the quasiconductor injection region forming the second conduction type；Deposit metal afterwards, then pass through photoetching
It is etched in front side of silicon wafer and forms gate electrode and emitter electrode；Deposition dielectric film being carved by photoetching subsequently
Erosion forms metal gasket；
Step 6, silicon chip is carried out thinning back side, and the back side after thinning carries out the first conductive-type
The injection of the foreign ion of type, then carry out the injection of the foreign ion of the second conduction type overleaf；
By thermal process, the ion that the back side is injected is activated afterwards
Step 7, in silicon chip back side deposited metal, form collecting zone electrode
By manufacturing process above, complete the manufacture of the device cellular of the present invention.
Further improve and be, the electricity of the second conduction type in step 4 in the first manufacture method
Injecting of lotus compensating basin includes at least the high energy ion implantation that primary energy is higher than 1MeV；By using high energy
Inject and reach the injection degree of depth needed, reduce and reach to need the thermal diffusion process needed for Impurity Distribution,
Thus reduce the manufacture process of the electric charge compensating region of the second conduction type to well region especially proximate to
The impact (directly affecting threshold voltage) of the well region impurity concentration near MOSFET channel, expands work
Skill window, improves the concordance of device.
The manufacture method of the second igbt that the present invention provides, comprises below step:
Step one, on the silicon substrate in drift semiconductor district with the first conduction type, pass through photoetching
Form groove with etching, then deposit gate oxidation films and polysilicon, form trench gate；
Step 2, by ion implanting and annealing formed the second conduction type quasiconductor well region；
Step 3, formed the launch site of the first conduction type by photoetching and ion implanting, and pass through
Photoetching and ion implanting form the quasiconductor electric charge compensating region of the second conduction type；Again by photoetching and
Ion implanting forms the semiconductor enhancement mode accumulation area of the first conduction type；
Step 4, at front side of silicon wafer deposition dielectric film, form contact hole by chemical wet etching, by from
Son injects the quasiconductor injection region forming the second conduction type, deposits metal afterwards, then passes through
Chemical wet etching forms gate electrode and emitter electrode at front side of silicon wafer；Deposition dielectric film pass through light subsequently
Etching forms metal gasket；
Step 5, silicon chip is carried out thinning back side, and the back side after thinning carries out the first conductive-type
The injection of the foreign ion of type, then carry out the injection of the foreign ion of the second conduction type overleaf；
By thermal process, the ion that the back side is injected is activated afterwards
Step 6, in silicon chip back side deposited metal, form collecting zone electrode
Further improve and be, the electricity of the second conduction type in the step 3 of the second manufacture method
Injecting of lotus compensating basin includes at least the high energy ion implantation that primary energy is higher than 1MeV；By using high energy
Inject and reach the injection degree of depth needed, reduce and reach to need the thermal diffusion process needed for Impurity Distribution,
Thus reduce the manufacture process of the electric charge compensating region of the second conduction type to well region especially proximate to
The impact (directly affecting threshold voltage) of the well region impurity concentration near MOSFET channel, expands work
Skill window, improves the concordance of device.
Further improve and be, the increasing of the first conduction type in the step 3 of the second manufacture method
The ion of strong type accumulation area uses the energy high energy ion implantation higher than 1MeV.So, high energy ion implantation is passed through
By the ion implanting of the enhancement mode accumulation area of the first type to needing near region, reduce formation
The technique of the enhancement mode accumulation area of the first type is to miscellaneous in the well region of the second conduction type of device
The impact of matter concentration, thus decrease the impact of foreign ion distribution near raceway groove, expand technique
Window, improves the concordance of device.
The manufacture method of the third igbt that the present invention provides, comprises below step:
Step one, the front deposit of silicon substrate in the drift semiconductor district with the first conduction type
One layer of epitaxial layer as the semiconductor enhancement mode accumulation area of the first conduction type；Continue deposit first
Plant the epitaxial layer of conduction type to the thickness needed；
Step 2, step one formed the epitaxial layer with the first type silicon chip on, by light
Carve and etching forms groove, then deposit gate oxidation films and polysilicon, form trench gate；
Step 3, by ion implanting and annealing formed the second conduction type quasiconductor well region；
Step 4, formed the launch site of the first conduction type by photoetching and ion implanting；
Step 5, at front side of silicon wafer deposition dielectric film, form contact hole by chemical wet etching, by from
Son injects the quasiconductor electric charge compensating region forming the second conduction type, forms one by ion implanting
The quasiconductor injection region of the second conduction type, deposits metal afterwards, then by chemical wet etching at silicon chip
Front forms gate electrode and emitter electrode；Deposition dielectric film form metal by chemical wet etching subsequently
Liner；
Step 6, silicon chip is carried out thinning back side, and the back side after thinning carries out the first conductive-type
The injection of the foreign ion of type, then carry out the injection of the foreign ion of the second conduction type overleaf；
By thermal process, the ion that the back side is injected is activated afterwards
Step 7, in silicon chip back side deposited metal, form collecting zone electrode
By contact hole, self-registered technology is utilized to form the quasiconductor charge compensation of the second conduction type
District, simplifies technique, has saved cost.Simultaneously, it is simple to adjust in the well region of the second conduction type
The concentration of the foreign ion of the second conduction type of the heart, improves the power of resisting voltaic impingement of device.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings, by readding
Read the following drawings detailed description that non-limiting embodiments is done, make the present invention and feature thereof, profile and
Advantage becomes readily apparent from.Sign identical in whole accompanying drawings represents identical part.Accompanying drawing is not
It is drawn to scale, it is preferred that emphasis is represent the purport of the present invention:
Fig. 1 is the structural representation of the field cut-off type IGBT of a kind of existing routine；
Fig. 2 is dopant species and the concentration distribution schematic diagram in Fig. 1 along AA '；
Fig. 3 is dopant species and the concentration distribution schematic diagram in Fig. 1 along BB '；
Fig. 4 is the structural representation of the field cut-off type IGBT of a kind of existing charge accumulation type；
Fig. 5 is dopant species and the concentration distribution schematic diagram in Fig. 4 along AA '；
Fig. 6 is dopant species and the concentration distribution schematic diagram in Fig. 4 along BB '；
Fig. 7 is the structural representation of a kind of IGBT of the embodiment of the present invention one；
Fig. 8 is dopant species and the concentration distribution schematic diagram in Fig. 7 along AA '；
Fig. 9 is dopant species and the concentration distribution schematic diagram in Fig. 7 along BB '；
Figure 10-1 is in Fig. 1 below the well region of device the second conduction type in the on-state
A kind of carrier concentration profile schematic diagram in the drift region of conduction type；
Figure 10-2 is in Fig. 4 below the well region of device the second conduction type in the on-state
A kind of carrier concentration profile schematic diagram in the drift region of conduction type；
Figure 11 is the embodiment of the present invention one device architecture (Fig. 7) the second in the on-state conduction
In the drift region of the first conduction type below the well region of type along from ' carrier concentration profile
Schematic diagram；
Figure 12 is the embodiment of the present invention one device architecture (Fig. 7) the second in the on-state conduction
Along the carrier concentration profile of BB ' in the drift region of the first conduction type below the well region of type
Schematic diagram；
Figure 13 is the structural representation of a kind of IGBT of the embodiment of the present invention two；
Figure 14 is dopant species and the concentration distribution schematic diagram in Figure 13 along AA '；
Figure 15 is dopant species and the concentration distribution schematic diagram in Figure 13 along BB '；
Figure 16 is the structural representation of a kind of IGBT of the embodiment of the present invention three；
Figure 17 is the structural representation of a kind of IGBT of the embodiment of the present invention four；
Detailed description of the invention
As it is shown in fig. 7, be the structure cell schematic diagram of a kind of IGBT semiconductor device of the embodiment of the present invention one.
It is that (IGBT is generally used in electricity with blocking voltage as 1200V that the present invention implements the IGBT semiconductor device of
The first quartile of stream-voltage curve, therefore blocking voltage refers at grid and emitter stage short circuit, colelctor electrode
The maximum voltage that can bear when connecing forward bias), there is N-type drift region 1-2, N-type cutoff layer 1-1,
Illustrating as a example by p-type collecting zone 2-3, therefore N-type is corresponding to claims and part described above
The first conduction type, p-type corresponds to claims and the second conductive-type of part described above
Type.This device structure cell also comprises groove 3, gate oxidation films 4, polysilicon gate 5, p-type trap 2-1,
P+ (high concentration P) injection region 2-2, N+ (high concentration N) launch site 6 (source region of MOSFET), P+
Collecting zone 2-3, deielectric-coating 7, contact hole 8, front metal 9, back metal 10.P+ injection region 2-2
Carrying out short circuit with source region 6 by metal electrode, suppression NPNP thyristor can not work, thus ensure IGBT
Normal work.The metal electrode connecting P+ injection region 2-2 and source region 6 is emitter stage, with trench gate phase
The metal electrode connected is grid (not shown), and the back metal electrode 10 being connected with collecting zone 2-3 is
Colelctor electrode.Notice that the emitter and collector of IGBT described here is at the internal work risen of IGBT structure
With having different from this appellation, if the colelctor electrode 10 of IGBT is at the bipolar transistor PNP within IGBT structure
In be the effect of emitter stage, the emitter stage of IGBT connects bipolar transistor PNP inside IGBT structure
In P+ injection region 2-2 (the collecting zone p-type trap 2-1 of PNP is drawn), rise in this PNP bipolar transistor
The effect of colelctor electrode, the emitter stage of IGBT has been simultaneously connected with inside IGBT structure the most not work
The N+ launch site 6 of the bipolar transistor NPN made.But owing to historical reasons keep this nomenclature, at this
No longer describe in detail.
As the feature of embodiments of the invention, it is being placed in N-type semiconductor drift region 1-2 and p-type trap
N-type enhancement mode accumulation area 1-3 ', adjacent enhancement mode accumulation area 1-3 ' is added between district 2-1
Between add p-type electric charge compensating region 2-4.
In a kind of more particular embodiment, the thickness of regional and impurity concentration do following setting:
The impurity concentration of P+ collecting zone is 1 × 1019atoms/cm3-5×1019atoms/cm3, thickness is about
0.5-1.5 micron；The thickness of N-type field cutoff layer 1-1 is 1-10 micron, and impurity concentration is 5 × 1016
atoms/cm3-1×1017atoms/cm3；The thickness of N-type drift region 1-2 is 100-120 micron,
Doping content is～5 × 1013atoms/cm3；The thickness of N-type enhancement mode accumulation area 1-3 ' is 0.5-2
Micron, minimum widith is more than 0.5 micron, and doping content is 1 × 1014atoms/cm3-3×1014
atoms/cm3；Impurity concentration in p-type electric charge compensating region 2-4, width, the degree of depth setting by N
The width of type enhancement mode accumulation area 1-3 ', thickness and doping content set, and target is to ensure that this
The N of the enhancement mode accumulation area 1-3 ' of the p type impurity total amount of described electric charge compensating region 2-4 and surrounding
The 15% of the difference of the type total impurities p type impurity total amount less than or equal to described electric charge compensating region 2-4,
15% of N-type impurity total amount again smaller than the enhancement mode accumulation area 1-3 ' equal to surrounding.P-type trap
Impurity concentration is 1 × 1017atoms/cm3-5×1017atoms/cm3, vertical depth is (from silicon face
Start to calculate) 3-4.5 micron, the surface concentration 1 × 10 of N+ launch site20atoms/cm3-5×1020
atoms/cm3, vertical depth (starting to calculate from silicon face) 0.5-1 micron.Degree of depth 6-7 of groove
Micron, width 1-2 micron.
In order to further illustrate the ginseng of N-type enhancement mode accumulation area 1-3 ' and p-type electric charge compensating region 2-4
The setting of number, provides example as follows:
First example be the spacing between trench gate be 6 microns, it increases near the N-type of trenched side-wall
The thickness of strong type accumulation area 1-3 ' is 2 microns, and N-type impurity concentration is 1 × 1014atoms/cm3,
Width is 2 microns, then be placed in the p-type electric charge in the middle of two N-type enhancement mode accumulation area 1-3 '
Width in compensating basin 2-4 can be set as 2 microns, thickness 2 microns, impurity concentration 2 × 1014
atoms/cm3, reach the optimal of N-type enhancement mode accumulation area 1-3 ' and p-type electric charge compensating region 2-4
Charge balance.In view of the change of technique, p-type electric charge compensating region impurity concentration is 1.7 × 1014
atoms/cm3-2.3×1014atoms/cm3During change, it is also possible to obtain preferable device performance.
Second example be the spacing between trench gate be 6 microns, it increases near the N-type of trenched side-wall
The thickness of strong type accumulation area 1-3 ' is 2 microns, and N-type impurity concentration is 3 × 1014atoms/cm3,
Width is 2 microns, then be placed in the p-type electric charge in the middle of two N-type enhancement mode accumulation area 1-3 '
Width in compensating basin 2-4 can be set as 2 microns, thickness 2 microns, impurity concentration 6 × 1014
atoms/em3, reach the optimal of N-type enhancement mode accumulation area 1-3 ' and p-type electric charge compensating region 2-4
Charge balance.In view of the change of technique, p-type electric charge compensating region impurity concentration is 5.1 × 1014
atoms/cm3-6.9×1014atoms/cm3During change, it is also possible to obtain preferable device performance.
So, by the formation of the N-type enhancement mode accumulation area of this high-dopant concentration, device is made to lead
Under logical state, at the quasiconductor of the first conduction type described in described enhancement mode accumulation area area below
In drift region, carrier concentration improves (shown in Figure 12, in drift region in carrier concentration profile such as figure
Shown in the inclination dotted line in 1-2 region), thus reduce the conducting resistance of device；Meanwhile, by using
The N-type enhancement mode accumulation area of high-dopant concentration so that the N-type accumulation area of MOSFET in IGBT device
(the Ac AREA shown in Fig. 7) resistance reduces, and same help reduces IGBT device electric conduction
Resistance.
By introducing p-type electric charge compensating region between adjacent described N-type enhancement mode accumulation area 1-3 '
2-4 so that device is working in the bar state, this p-type electric charge compensating region 2-4 and the N of surrounding
Type enhancement mode accumulation area 1-3 ' is in reverse-bias state, produces a transverse electric field, it is achieved PN
The having lateral depletion of knot, thus reduce at the knot to P type trap zone 2-1 and this enhancement mode accumulation area 1-3 '
The impact of longitudinal electric field intensity, make the electric field intensity of this enhancement mode accumulation area and the pass of position simultaneously
System be one trapezoidal, it is ensured that the blocking voltage of device not because use high-dopant concentration N-type strengthen
Type accumulation area and reduce.Further, by controlling doping in described p-type electric charge compensating region 2-4
With the difference of the impurity level of the N-type enhancement mode accumulation area 1-3 ' of surrounding, higher N can used
In the case of the impurity concentration of type enhancement mode accumulation area, the still blocking voltage of retainer member.
By adding P-type semiconductor electricity between adjacent N-type semiconductor enhancement mode accumulation area 1-3 '
Lotus compensating basin 2-4 so that device is in conducting state to the handoff procedure of off state, at conducting shape
Under state, in the 1-2 of N-type semiconductor drift region, the p-type carrier of accumulation can be by this P-type semiconductor
Electric charge compensating region 2-4, p-well region 2-1 and P+ injection region 2-2 arrive the contact point (metal of emitter stage
At the Ohmic contact of silicon), reduce the shutoff energy consumption of device, improve the turn-off characteristic of device.Improve
Owing to increasing the shadow to turn-off characteristic that charge accumulating layer causes in charge accumulated type IGBT (Fig. 3)
Ring.
It is that the quasiconductor electric charge compensating region 2-4 of p-type can be saturating to further improving of embodiment one
Cross the region of described N-type semiconductor enhancement mode accumulation area 1-3 ', the quasiconductor electric charge compensating region of p-type
The bottom of 2-4 can be concordant with N-type semiconductor enhancement mode accumulation area 1-3 ', it is also possible to prominent (prominent
Artificial situation is not shown), directly contact with described N-type semiconductor drift region；Device is so made to lead
Logical state is in the handoff procedure of off state, tired in N-type semiconductor drift region in the on-state
Long-pending p-type carrier can be easier to arrive emitter stage by this P-type semiconductor electric charge compensating region 2-4
Contact point (at the Ohmic contact of metal and silicon), reduce the shutoff energy consumption of device further, improve
The turn-off characteristic of device.
In superincumbent explanation, the impurity concentration in any one region, refer to is all certain of this region
The net concentration of conductive type impurity, such as the quasiconductor electric charge compensating region 2-4 to p-type, its formation
Can be to be obtained by implanting p-type impurity diffusion in N-type extension, then the P in described above
The impurity concentration of type quasiconductor electric charge compensating region 2-4 is exactly to inject outside the p type impurity subduction N-type formed
Value after the N-type impurity of Yanzhong.The most too.
During practical devices manufactures, owing to the ion distribution after ion implanting is a kind of Gauss distribution, therefore
Ion distribution in one region has certain change.In order to the purport of the present invention is had more specific
Illustrating, the impurity concentration in each region is simplified to represent with data in the above description.This
The most too.
Embodiment two:
(Figure 14 and Figure 15 is the dopant species along AA ' and BB ' and concentration respectively as shown in figure 13
Distribution schematic diagram), with being a difference in that of embodiment one, described P-type semiconductor electric charge compensating region 2-4
It is placed among the region of semiconductor enhancement mode accumulation area 1-3 ' of N-type, not with the drift of N-type semiconductor
Move district directly to contact, so can increase the drift region under P-type semiconductor electric charge compensating region 2-4
Carrier concentration in 1-2, reduces conducting resistance, more preferable acquirement conduction loss and switching loss
Balance, improves the motility of device design.When at described P-type semiconductor electric charge compensating region 2-4
The distance of bottom of semiconductor enhancement mode accumulation area 1-3 ' of bottom and N-type less than p type impurity
In the case of diffusion length, still can play the effect improving turn-off performance.
Embodiment three:
As shown in figure 16, unlike embodiment two, described P-type semiconductor electric charge compensating region 2-4
It is placed among the region of semiconductor enhancement mode accumulation area 1-3 ' of N-type, not with the trap of P-type semiconductor
District 2-1 directly contacts, and so improves the motility of device design.Mend at described P-type semiconductor electric charge
Repay the distance of the top of district 2-4 and the bottom of the P type trap zone 2-1 diffusion length less than p type impurity
In the case of, still can play the effect improving turn-off performance.
Embodiment four:
As shown in figure 17, with being a difference in that of embodiment one, described P-type semiconductor charge compensation
District 2-4 uses different impurity concentrations in zones of different, at the semiconductor enhancement mode accumulation area with N-type
Among the close region of 1-3 ', the semiconductor enhancement mode accumulation area charge balance of selection and N-type
Set, in P type trap zone territory thereon, use the ratio p-type higher impurity concentration of trap concentration, so
(light shield same for P-type semiconductor electric charge compensating region 2-4 is used on the premise of not increasing manufacturing cost
And photoetching process), improve the ability of antiparasitic NPNP thyristor, improve the anti-breech lock energy of device
Power.
The manufacture method of the first igbt that the present invention provides, comprises below step
(with reference to Fig. 7):
Step one, deposit one layer as N-type half in the front of the silicon substrate with N-type drift region 1-2
The epitaxial layer 1-3 ' of conductor enhancement mode accumulation area；Continue deposit N-type epitaxy layer to the thickness needed.
Silicon substrate can be zone melting and refining silicon silicon chip, it is also possible to be pulling of crystals silicon chip.
The impurity concentration of the N-type epitaxy layer in 1-3 ' not the most very strict requirements, mainly thickness and
The requirement of defect device to be met.
Step 2, on the silicon chip of the N-type epitaxy layer of step one, by photoetching and etching formed groove
3, then deposit gate oxidation films 4 and polysilicon gate 5, form trench gate；
Gash depth 6-7 micron, width 1-2 micron, gate oxidation films 800-1200 angstrom, polysilicon
Being highly doped N-type polycrystalline silicon, general deposition temperature is at 580-620 degree Celsius.
Step 3, by ion implanting and annealing formed P type trap zone 2-1；
Step 4, the N-type source region 6 that formed by photoetching and ion implanting, and by photoetching and ion note
Enter to be formed P-type semiconductor electric charge compensating region 2-4；
The injection ion of N-type source region 6 is typically arsenic or phosphorus, or combinations thereof.
The injection of P-type semiconductor electric charge compensating region 2-4 is typically to inject boron.
Step 5, at front side of silicon wafer deposition dielectric film 7, form contact hole 8 by chemical wet etching, logical
Cross ion implanting and form P-type semiconductor injection region 2-2；Deposit metal afterwards, then pass through chemical wet etching
Gate electrode and emitter electrode is formed at front side of silicon wafer；Deposition dielectric film by chemical wet etching shape subsequently
Become metal gasket；
Step 6, silicon chip is carried out thinning back side, and the back side after thinning carries out N-type impurity ion
Injection to form N-type cutoff layer 1-1, then carry out the injection of p type impurity ion overleaf, with shape
Become P+ collecting zone 2-3；By thermal process, the ion that the back side is injected is activated afterwards.
It can be phosphorus that described N-type impurity is injected, it is also possible to be hydrogen.
Described thermal process can be to be realized by furnace process, it is also possible to is to be realized by laser annealing,
Or combinations thereof realizes.
Step 7, in silicon chip back side deposited metal, form collecting zone electrode
Further improve and be, the electric charge compensating region of the p-type in step 4 in the first manufacture method
Inject the high energy ion implantation being higher than 1MeV including at least primary energy；The high-energy boron of such as 1.5-3MeV
Inject so that the maximum concentration of implanted dopant is distributed in away from the 4-5 micron of front side of silicon wafer surface, reduce
Impact on the ion concentration in p-type trap 2-1, does not particularly interfere with the P near groove
The concentration of type impurity, in order to avoid impacting the threshold voltage of device, expands process window, improves
The concordance of device.
The manufacture method of the second igbt that the present invention provides, comprises below step:
Step one, on the silicon substrate have N-type drift region 1-2 by photoetching and etching formed groove
3, then deposit gate oxidation films 4 and polysilicon gate 5, form trench gate；
Step 2, by ion implanting and annealing formed P-type semiconductor well region 2-1；
Step 3, the source region 6 of N-type of being formed by photoetching and ion implanting, and by photoetching and ion
Inject the electric charge compensating region 2-4 forming P-type semiconductor；N-type is formed again by photoetching and ion implanting
Semiconductor enhancement mode accumulation area 1-3 '；
Step 4, at front side of silicon wafer deposition dielectric film 7, form contact hole 8 by chemical wet etching, logical
Cross ion implanting and form a P-type semiconductor injection region 2-2, afterwards deposit metal 9, then pass through light
It is etched in front side of silicon wafer quarter and forms gate electrode and emitter electrode；Deposition dielectric film pass through photoetching subsequently
Etching forms metal gasket；
Step 5, silicon chip is carried out thinning back side, and the back side after thinning carry out the impurity of N-type from
The injection of son, then carry out the injection of p type impurity ion overleaf；By thermal process, the back side is noted afterwards
The ion entered activates
Step 6, in silicon chip back side deposited metal, form collecting zone electrode
Parameter in above-mentioned manufacturing step is referred to the setting in the first manufacture method substantially, it
Further improving is that the second manufacture method enhancement mode accumulation area 1-3 ' is not by extension shape
Becoming, two is to increase ion implanting by the N-type in step 3 to realize, and uses energy (big higher than 3-5MeV
In 1MeV) high energy phosphorus inject, by the ion implanting of N-type enhancement mode accumulation area to needing region
Near, the technique reducing the enhancement mode accumulation area forming N-type is dense to impurity in the P type trap zone of device
The impact of degree, thus decrease the impact of foreign ion distribution near raceway groove, expand process window,
Improve the concordance of device.
It is same as the improvement in the first manufacture method, the p-type in the step 3 of the second manufacture method
Injecting of electric charge compensating region includes at least the high-energy boron injection that primary energy is higher than 1MeV, such as 1.5-3
The high-energy boron of MeV is injected so that the maximum concentration of implanted dopant is distributed in from front side of silicon wafer surface 4-5
At Wei meter, reduce the impact on the ion concentration in p-type trap 2-1, particularly do not interfere with close
The concentration of the p type impurity near groove, in order to avoid impacting the threshold voltage of device.
The manufacture method of the third igbt that the present invention provides, comprises below step:
Step one, deposit one layer as N-type half in the front of the silicon substrate with N-type drift region 1-2
The epitaxial layer of conductor enhancement mode accumulation area 1-3 '；The epitaxial layer continuing to deposit the first conduction type arrives
The thickness needed；
Step 2, step one formed the epitaxial layer with the first type silicon chip on, by light
Carve and etching forms groove 3, then deposit gate oxidation films 4 and polysilicon gate 5, form trench gate；
Step 3, by ion implanting and annealing formed P-type semiconductor well region 2-1；
Step 4, the source region 6 of N-type of being formed by photoetching and ion implanting；
Step 5, at front side of silicon wafer deposition dielectric film 7, form contact hole 8 by chemical wet etching, logical
Cross ion implanting and form P-type semiconductor electric charge compensating region 2-4, form p-type by ion implanting and partly lead
Body injection region 2-2, afterwards deposit metal 9, then form gate electrode by chemical wet etching at front side of silicon wafer
And emitter electrode；Deposition dielectric film form metal gasket by chemical wet etching subsequently；
Step 6, silicon chip is carried out thinning back side, and the back side after thinning carry out the impurity of N-type from
The injection of son, then carry out the injection of p type impurity ion overleaf；By thermal process, the back side is noted afterwards
The ion entered activates
Step 7, in silicon chip back side deposited metal, form collecting zone electrode
Parameter in the third manufacture method is referred to the setting in the first manufacture method substantially, it
Further to improve be that the formation of P-type semiconductor electric charge compensating region 2-4 is after contact hole is formed
Carry out, by contact hole, utilize self-registered technology to form the quasiconductor electric charge of the second conduction type
Compensating basin, simplifies technique, has saved cost.Simultaneously, it is simple to adjust the trap of the second conduction type
The concentration of the foreign ion of the second conduction type of district center, improves the anti-current impact energy of device
Power.
In described above of the present invention, if N being changing into P, P be changing into N, just become p-type
The IGBT device that MOSFET and bipolar transistor NPN are formed, is full symmetric (at this moment first
Planting conduction type is p-type, and the second conduction type is N-type).
Above by specific embodiment, the present invention has been described in detail, but these not constitute right
The restriction of the present invention.Without departing from the principles of the present invention, those skilled in the art also can do
Going out many deformation and improve, these also should be regarded as protection scope of the present invention.
Claims (10)
1. the structure cell of an igbt, it is characterized in that: including at least launch site in described structure cell, collecting zone, groove, trench gate oxide-film, polysilicon gate, the drift semiconductor district of the first conduction type, the quasiconductor well region of the second conduction type, the semiconductor enhancement mode accumulation area of the first conduction type being placed between drift semiconductor district and the quasiconductor well region of described the second conduction type of the first conduction type described, the quasiconductor electric charge compensating region of the second conduction type between the semiconductor enhancement mode accumulation area of adjacent the first conduction type described.
The impurity doping concentration of the first conduction type of the semiconductor enhancement mode accumulation area of the first conduction type described is more than or equal to 2 times of the impurity doping concentration of the first conduction type in the drift semiconductor district of the first conduction type described；
The setting of the impurity doping concentration in the quasiconductor electric charge compensating region of described the second conduction type, ensure the first conduction type of the described enhancement mode accumulation area of impurity doping total amount and the surrounding of the second conduction type of this described electric charge compensating region impurity doping total amount difference less than or equal to the second conduction type of described electric charge compensating region impurity doping total amount 15%, again smaller than the described enhancement mode accumulation area equal to surrounding the first conduction type impurity doping total amount 15%.
2. the structure cell of igbt as claimed in claim 1, it is characterised in that: the impurity doping concentration of the first conduction type of the semiconductor enhancement mode accumulation area of the first conduction type described is more than or equal to 5 times of the impurity doping concentration of the first conduction type in the drift semiconductor district of the first conduction type described.
3. the structure cell of igbt as claimed in claim 1, it is characterized in that: the quasiconductor electric charge compensating region of described the second conduction type directly can contact with the drift semiconductor district of the first conduction type described through the region of the semiconductor enhancement mode accumulation area of the first conduction type described.
4. the structure cell of igbt as claimed in claim 1, it is characterized in that: the quasiconductor electric charge compensating region of described the second conduction type is placed among the region of semiconductor enhancement mode accumulation area of the first conduction type, and the drift region with the first type semiconductor described does not directly contact.
5. the manufacture method of an igbt, it is characterised in that comprise below step:
Step one, silicon substrate in the drift semiconductor district with the first conduction type front deposit one floor as the epitaxial layer of the semiconductor enhancement mode accumulation area of the first conduction type；Continue the epitaxial layer depositing the first conduction type to the thickness needed；
Step 2, the epitaxial layer with the first conduction type formed in step one silicon chip on, form groove by photoetching and etching, then deposit gate oxidation films and polysilicon, form trench gate；
Step 3, by ion implanting and annealing formed the second conduction type quasiconductor well region；
Step 4, formed the launch site of the first conduction type by photoetching and ion implanting, and formed the quasiconductor electric charge compensating region of the second conduction type by photoetching and ion implanting；
Step 5, at front side of silicon wafer deposition dielectric film, form contact hole by chemical wet etching, formed the quasiconductor injection region of the second conduction type by ion implanting；Deposit metal afterwards, then form gate electrode and emitter electrode by chemical wet etching at front side of silicon wafer；Deposition dielectric film form metal gasket by chemical wet etching subsequently；
Step 6, silicon chip is carried out thinning back side, and the back side after thinning carries out the injection of foreign ion of the first conduction type, then carry out the injection of the foreign ion of the second conduction type overleaf；By thermal process, the ion that the back side is injected is activated afterwards；
Step 7, in silicon chip back side deposited metal, form collecting zone electrode.
6. in the manufacture method of igbt as claimed in claim 5, it is characterised in that: injecting of the electric charge compensating region of the second type in step 4 includes at least the high energy ion implantation that primary energy is higher than 1MeV.
7. the manufacture method of the structure cell of an igbt, it is characterised in that comprise below step:
Step one, on the silicon substrate in drift semiconductor district with the first conduction type, form groove by photoetching and etching, then deposit gate oxidation films and polysilicon, form trench gate；
Step 2, by ion implanting and annealing formed the second conduction type quasiconductor well region；
Step 3, formed the launch site of the first conduction type by photoetching and ion implanting, and formed the quasiconductor electric charge compensating region of the second conduction type by photoetching and ion implanting；The semiconductor enhancement mode accumulation area of the first conduction type is formed again by photoetching and ion implanting；
Step 4, at front side of silicon wafer deposition dielectric film, contact hole is formed by chemical wet etching, formed the quasiconductor injection region of the second conduction type by ion implanting, deposit metal afterwards, then form gate electrode and emitter electrode by chemical wet etching at front side of silicon wafer；Deposition dielectric film form metal gasket by chemical wet etching subsequently；
Step 5, silicon chip is carried out thinning back side, and the back side after thinning carries out the injection of foreign ion of the first conduction type, then carry out the injection of the foreign ion of the second conduction type overleaf；By thermal process, the ion that the back side is injected is activated afterwards；
Step 6, in silicon chip back side deposited metal, form collecting zone electrode.
8. in the manufacture method of igbt as claimed in claim 7, it is characterised in that: injecting of the electric charge compensating region of the second type in step 3 includes at least the ion implanting that primary energy is higher than 1MeV.
9. in the manufacture method of igbt as claimed in claim 7, it is characterised in that: the ion implanting of the enhancement mode accumulation area of the first type in step 3 comprises the Implantation Energy ion implanting higher than 1MeV.
10. the manufacture method of the structure cell of an igbt, it is characterised in that comprise below step:
Step one, silicon substrate in the drift semiconductor district with the first conduction type front deposit one floor as the epitaxial layer of the semiconductor enhancement mode accumulation area of the first conduction type；Continue the epitaxial layer depositing the first conduction type to the thickness needed；
Step 2, the epitaxial layer with the first type formed in step one silicon chip on, form groove by photoetching and etching, then deposit gate oxidation films and polysilicon, form trench gate；
Step 3, by ion implanting and annealing formed the second conduction type quasiconductor well region；
Step 4, formed the launch site of the first conduction type by photoetching and ion implanting；
Step 5, at front side of silicon wafer deposition dielectric film, contact hole is formed by chemical wet etching, the quasiconductor electric charge compensating region of the second conduction type is formed by ion implanting, the quasiconductor injection region of the second conduction type is formed by ion implanting, deposit metal afterwards, then form gate electrode and emitter electrode by chemical wet etching at front side of silicon wafer；Deposition dielectric film form metal gasket by chemical wet etching subsequently；
Step 6, silicon chip is carried out thinning back side, and the back side after thinning carries out the injection of foreign ion of the first conduction type, then carry out the injection of the foreign ion of the second conduction type overleaf；By thermal process, the ion that the back side is injected is activated afterwards；
Step 7, in silicon chip back side deposited metal, form collecting zone electrode.
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| CN109273520A (en) * | 2017-07-18 | 2019-01-25 | 富士电机株式会社 | Semiconductor device |
| CN109564939A (en) * | 2017-02-24 | 2019-04-02 | 富士电机株式会社 | Semiconductor device |
| CN112397580A (en) * | 2019-08-19 | 2021-02-23 | 广东美的白色家电技术创新中心有限公司 | Insulated gate bipolar transistor and manufacturing method thereof |
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