JP2005210047A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2005210047A
JP2005210047A JP2004092975A JP2004092975A JP2005210047A JP 2005210047 A JP2005210047 A JP 2005210047A JP 2004092975 A JP2004092975 A JP 2004092975A JP 2004092975 A JP2004092975 A JP 2004092975A JP 2005210047 A JP2005210047 A JP 2005210047A
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semiconductor
contact
semiconductor device
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JP4723816B2 (en
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Sachiko Kawaji
佐智子 河路
Takahide Sugiyama
隆英 杉山
Masanori Usui
正則 臼井
Koji Hotta
幸司 堀田
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Toyota Motor Corp
Toyota Central R&D Labs Inc
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Application filed by Toyota Motor Corp, Toyota Central R&D Labs Inc filed Critical Toyota Motor Corp
Priority to EP04801653A priority patent/EP1697995B1/en
Priority to KR1020067014839A priority patent/KR100802527B1/en
Priority to US10/581,664 priority patent/US7737491B2/en
Priority to EP08004963A priority patent/EP2146377B1/en
Priority to PCT/JP2004/018432 priority patent/WO2005062385A1/en
Priority to DE602004029714T priority patent/DE602004029714D1/en
Publication of JP2005210047A publication Critical patent/JP2005210047A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
    • H01L29/7395—Vertical transistors, e.g. vertical IGBT
    • H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
    • H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
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    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1095—Body region, i.e. base region, of DMOS transistors or IGBTs
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors

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Abstract

<P>PROBLEM TO BE SOLVED: To reduce ON-state voltage by increasing the hole carrier concentration between emitter-collector electrodes. <P>SOLUTION: In an Insulated Gate Bipolar Transistor (IGBT) provided with a pair of main electrodes (emitter-collector electrodes) and a trench gate electrode 32 controlling the on-off state of the electric current flowing between a pair of the main electrodes, an n-type floating semiconductor region is formed in a body region 28 side from the bonding interface of the body region 28 and a drift region 26. Moreover, this floating semiconductor region 40 is preferably formed in contact with a body contact region 34. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明は、一対の主電極と、その一対の主電極間を流れる電流のオン・オフを制御するゲート電極を備えた半導体装置に関し、とくにその半導体装置のオン電圧あるいはオン抵抗の低減化に関する。   The present invention relates to a semiconductor device including a pair of main electrodes and a gate electrode for controlling on / off of a current flowing between the pair of main electrodes, and more particularly to reduction of on-voltage or on-resistance of the semiconductor device.

半導体装置の一例として、バイポーラトランジスタの表面部にＭＯＳ構造を備えたＩＧＢＴ（Insulated Gate Bipolar Transistor）が知られている。この種の半導体装置は、一対の主電極と、その一対の主電極間を流れる電流のオン・オフを制御するゲート電極を備えている。ゲート電極にオン電圧が印加されると、一方の主電極からは半導体領域に電子キャリアが注入され、他方の主電極からは半導体領域に正孔キャリアが注入される。これにより半導体領域に伝導度変調が起こり、低いオン電圧を実現する。   As an example of a semiconductor device, an IGBT (Insulated Gate Bipolar Transistor) having a MOS structure on the surface of a bipolar transistor is known. This type of semiconductor device includes a pair of main electrodes and a gate electrode that controls on / off of a current flowing between the pair of main electrodes. When a turn-on voltage is applied to the gate electrode, electron carriers are injected from one main electrode into the semiconductor region, and hole carriers are injected from the other main electrode into the semiconductor region. Thereby, conductivity modulation occurs in the semiconductor region, and a low on-voltage is realized.

特許文献１には、この種の半導体装置において、低いオン電圧を実現する技術が記載されている。
特開平８−３１６４７９号公報（その公報の図３参照） Patent Document 1 describes a technique for realizing a low on-voltage in this type of semiconductor device.
JP-A-8-316479 (refer to FIG. 3 of that publication)

特許文献１に記載されている半導体装置を図１７に模式的に示す（以下、本明細書ではこの構成を従来構造と称する）。図１７に示す半導体装置１５は、一対の主電極（この場合はエミッタ電極とコレクタ電極）間を流れる電流のオン・オフを制御するトレンチゲート電極３３２を備えている。
半導体装置１５は、エミッタ電極Ｅと接続するｐ＋型のボディコンタクト領域３３４と、そのエミッタ電極Ｅと接続するｎ＋型のエミッタ領域３３６と、そのボディコンタクト領域３３４とエミッタ領域３３６を囲繞するｐ−型のボディ領域３２８と、そのボディ領域３２８と接するｎ−型のドリフト領域３２６とを備えている。ボディ領域３２８とドリフト領域３２６の間には、ｎ＋型の半導体領域３４０が設けられている。エミッタ領域３３６を貫いてトレンチが形成され、そのトレンチにトレンチゲート電極３３２が埋め込まれている。トレンチゲート電極３３２は、ゲート絶縁膜３３３を介してエミッタ領域３３６とドリフト領域３２６を隔てているボディ領域３２８に対向している。
ドリフト領域３２６と接するｎ＋型のバッファ領域３２４と、そのバッファ領域３２４に接するｐ＋型のコレクタ領域３２２とを備え、そのコレクタ領域３２２はコレクタ電極Ｃに接続されている。 A semiconductor device described in Patent Document 1 is schematically shown in FIG. 17 (hereinafter, this configuration is referred to as a conventional structure in this specification). A semiconductor device 15 shown in FIG. 17 includes a trench gate electrode 332 that controls on / off of a current flowing between a pair of main electrodes (in this case, an emitter electrode and a collector electrode).
The semiconductor device 15 includes a p + type body contact region 334 connected to the emitter electrode E, an n + type emitter region 336 connected to the emitter electrode E, and a p surrounding the body contact region 334 and the emitter region 336. A − type body region 328 and an n − type drift region 326 in contact with the body region 328 are provided. An n + type semiconductor region 340 is provided between the body region 328 and the drift region 326. A trench is formed through the emitter region 336, and a trench gate electrode 332 is embedded in the trench. The trench gate electrode 332 faces the body region 328 that separates the emitter region 336 and the drift region 326 with the gate insulating film 333 interposed therebetween.
An n + -type buffer region 324 in contact with the drift region 326 and a p + -type collector region 322 in contact with the buffer region 324 are provided, and the collector region 322 is connected to the collector electrode C.

半導体装置１５のオン状態の動作を説明する。エミッタ電極Ｅを接地し、コレクタ電極Ｃとトレンチゲート電極３３２に正電圧を印加すると、ボディ領域３２８のうちトレンチゲート電極３３２と対向する箇所がｎ型に反転される。電子キャリアがエミッタ領域３３６からそのｎ型に反転した箇所を経由しドリフト領域３２６へ注入され、そしてバッファ領域３２４内に蓄積する。電子キャリアがバッファ領域３２４に蓄積すると、バッファ領域３２４とコレクタ領域３２２の接触電位差が低下し、コレクタ領域３２２からバッファ領域３２４とドリフト領域３２６へ正孔キャリアが注入される。これによりバッファ領域３２４及びドリフト領域３２６に伝導度変調が起こり、低いオン電圧を実現する。
コレクタ領域３２２から注入された正孔キャリアは、電子キャリアと再結合して消滅するか、ボディ領域３２８とボディコンタクト領域３３４を経由してエミッタ電極Ｅへと排出される。
半導体装置１５は、ドリフト領域３２６の上部にそのドリフト領域３２６よりも不純物濃度が高濃度の半導体領域３４０が形成されている。したがって、エミッタ電極Ｅへと排出される正孔キャリアが、この半導体領域３４０とドリフト領域３２６の界面に形成されるポテンシャル障壁によってドリフト領域３２６内に溜まり易くなる（図１７参照）。これにより、エミッタ・コレクタ電極間の正孔キャリア濃度が大きくなりオン電圧が低減される。 The operation of the semiconductor device 15 in the on state will be described. When the emitter electrode E is grounded and a positive voltage is applied to the collector electrode C and the trench gate electrode 332, the portion of the body region 328 that faces the trench gate electrode 332 is inverted to n-type. Electron carriers are injected from the emitter region 336 into the drift region 326 via the n-type inverted portion and accumulate in the buffer region 324. When the electron carriers accumulate in the buffer region 324, the contact potential difference between the buffer region 324 and the collector region 322 decreases, and hole carriers are injected from the collector region 322 into the buffer region 324 and the drift region 326. As a result, conductivity modulation occurs in the buffer region 324 and the drift region 326, and a low on-voltage is realized.
Hole carriers injected from the collector region 322 are recombined with electron carriers and disappear, or are discharged to the emitter electrode E via the body region 328 and the body contact region 334.
In the semiconductor device 15, a semiconductor region 340 having an impurity concentration higher than that of the drift region 326 is formed above the drift region 326. Therefore, hole carriers discharged to the emitter electrode E are likely to accumulate in the drift region 326 by the potential barrier formed at the interface between the semiconductor region 340 and the drift region 326 (see FIG. 17). This increases the hole carrier concentration between the emitter and collector electrodes and reduces the on-voltage.

しかしながら、特許文献１の半導体装置１５において、半導体領域３４０を抜けてボディ領域３２８に流入した少数キャリアは、すぐにボディコンタクト領域３３４を経由してエミッタ電極Ｅへと排出されており、ボディ領域３２８内の少数キャリア濃度は小さいままであった。
本発明の目的は、ボディ領域内の少数キャリア濃度を高めることで、オン電圧の低減化を図ることを目的とする。 However, in the semiconductor device 15 of Patent Document 1, minority carriers that have flowed into the body region 328 through the semiconductor region 340 are immediately discharged to the emitter electrode E via the body contact region 334, and the body region 328. Among them, the minority carrier concentration remained small.
An object of the present invention is to reduce the on-voltage by increasing the minority carrier concentration in the body region.

本発明の半導体装置は、一対の主電極と、一方の主電極と接続する第１導電型のボディコンタクト領域と、その一方の主電極と接続する第２導電型の第２導電型半導体領域と、そのボディコンタクト領域と第２導電型半導体領域の少なくとも一部と接する第１導電型のボディ領域と、そのボディ領域と接するとともに、ボディコンタクト領域と第２導電型半導体領域からボディ領域によって隔てられている第２導電型のドリフト領域と、前記第２導電型半導体領域とドリフト領域を隔てているボディ領域にゲート絶縁膜を介して対向するゲート電極とを備えている。
本発明の一つの半導体装置は、ボディ領域とドリフト領域の接合界面よりボディ領域側に第２導電型のフローティング半導体領域及び／又は絶縁層が形成されていることを特徴としている。フローティング半導体領域は、ドリフト領域と離反して形成されており、フローティング状態である。フローティング半導体領域又は絶縁層が複数個形成されていてもよく、また半導体装置内に同時に形成されていてもよい。
このフローティング半導体領域及び／又は絶縁層の形成位置は、ボディ領域内であってもよく、ボディコンタクト領域に直接接触していてもよく、あるいはボディコンタクト領域内に形成されていてもよい。要は、ボディ領域とドリフト領域の接合界面よりもボディ領域側に形成されていればよい。
なお、本発明はＭＯＳＦＥＴ、ＩＧＢＴ、サイリスタ等に適用することができ、ＭＯＳＦＥＴであれば一対の主電極はドレイン・ソース電極であり、第２導電型半導体領域がソース領域となる。ＩＧＢＴやサイリスタであれば一対の主電極はエミッタ・コレクタ電極であり、第２導電型半導体領域がエミッタ領域となる。 The semiconductor device of the present invention includes a pair of main electrodes, a first conductivity type body contact region connected to one main electrode, and a second conductivity type second conductivity type semiconductor region connected to the one main electrode. A body region of a first conductivity type in contact with the body contact region and at least a part of the second conductivity type semiconductor region, a body region in contact with the body contact region, and separated from the body contact region and the second conductivity type semiconductor region by the body region. A drift region of the second conductivity type, and a gate electrode facing the body region separating the drift region from the second conductivity type semiconductor region via a gate insulating film.
One semiconductor device of the present invention is characterized in that a floating semiconductor region and / or an insulating layer of the second conductivity type is formed on the body region side from the junction interface between the body region and the drift region. The floating semiconductor region is formed away from the drift region and is in a floating state. A plurality of floating semiconductor regions or insulating layers may be formed, or may be formed simultaneously in the semiconductor device.
The formation position of the floating semiconductor region and / or the insulating layer may be in the body region, may be in direct contact with the body contact region, or may be formed in the body contact region. In short, it may be formed on the body region side with respect to the junction interface between the body region and the drift region.
The present invention can be applied to MOSFETs, IGBTs, thyristors, etc. In the case of MOSFETs, a pair of main electrodes are drain / source electrodes, and the second conductivity type semiconductor region is a source region. In the case of an IGBT or thyristor, the pair of main electrodes is an emitter / collector electrode, and the second conductivity type semiconductor region is an emitter region.

従来構造では、ボディ領域内の少数キャリア濃度は、そのボディ領域内に亘って小さいという問題があった。上記の半導体装置によると、ボディ領域とドリフト領域の接合界面よりもボディ領域側に第２導電型のフローティング半導体領域が形成されているために、そのフローティング半導体領域によって少数キャリアはボディ領域内に溜められる。したがって、ボディ領域内の少数キャリア濃度が高くなり、ひいては一対の主電極間の少数キャリア濃度が高くなる。このためオン電圧の低減を実現できる。   The conventional structure has a problem that the minority carrier concentration in the body region is small over the body region. According to the semiconductor device described above, since the second conductivity type floating semiconductor region is formed on the body region side of the junction interface between the body region and the drift region, minority carriers are accumulated in the body region by the floating semiconductor region. It is done. Accordingly, the minority carrier concentration in the body region is increased, and as a result, the minority carrier concentration between the pair of main electrodes is increased. For this reason, reduction of ON voltage is realizable.

第２導電型半導体領域の膜厚が、フローティング半導体領域又は絶縁層の膜厚よりも小さいことが好ましい。
フローティング半導体領域及び／又は絶縁層を形成することで、オン電圧は低減される。オン電圧が低減されると、その飽和電流値が上昇し、半導体装置が破壊され易くなるという問題が生じ得る。
本発明者らは、上記の問題に関してその原因を探求したところ、飽和電流値の上昇はその半導体装置の直列抵抗に起因しており、なかでも第２導電型半導体領域の特性に大きく影響されることを突き止めた。即ち、第２導電型半導体領域の多数キャリアの供給能力が大きいと、ボディ領域内の少数キャリアの蓄積に追随して第２導電型半導体領域から多量の多数キャリアが注入され、ひいては飽和電流値が上昇し半導体装置が破壊に至るのである。したがって、第２導電型半導体領域の多数キャリアの供給能力を適度に抑えることで、半導体装置の破壊を抑制できることを突き止めた。典型的には、第２半導体領域の不純物濃度を小さくしたり、あるいはその膜厚や幅などを小さくし体積自体を小さくするなどの方法で実現できる。また、この第２導電型半導体領域の多数キャリアの供給能力は、フローティング半導体領域又は絶縁層における少数キャリアの蓄積能力に相関して設定されるのが好ましい。上述したように、ボディ領域内で少数キャリアの蓄積量が増加する場合に半導体装置の破壊が問題となり易いためである。したがって、本発明ではその一例として、第２導電型半導体領域の膜厚がフローティング半導体領域又は絶縁層の膜厚よりも小さいことが好ましいとしたのである。この場合、オン電圧の低減化とともに半導体装置の破壊が抑制される。なお、この例に限らず、エミッタ領域の不純物濃度や体積などを調整することで、同様の作用効果を得ることができる。 The film thickness of the second conductivity type semiconductor region is preferably smaller than the film thickness of the floating semiconductor region or the insulating layer.
By forming the floating semiconductor region and / or the insulating layer, the on-voltage is reduced. When the on-voltage is reduced, the saturation current value increases, which may cause a problem that the semiconductor device is easily destroyed.
As a result of searching for the cause of the above problem, the inventors of the present invention have found that the increase in saturation current value is caused by the series resistance of the semiconductor device, and is particularly affected by the characteristics of the second conductivity type semiconductor region. I found out. That is, if the supply capacity of majority carriers in the second conductivity type semiconductor region is large, a large number of majority carriers are injected from the second conductivity type semiconductor region following the accumulation of minority carriers in the body region, and consequently the saturation current value is increased. The semiconductor device rises and breaks down. Therefore, it has been found that the breakdown of the semiconductor device can be suppressed by appropriately suppressing the majority carrier supply capability of the second conductivity type semiconductor region. Typically, this can be realized by reducing the impurity concentration of the second semiconductor region, or reducing the film thickness, width, etc. to reduce the volume itself. Moreover, it is preferable that the majority carrier supply capability of the second conductivity type semiconductor region is set in correlation with the minority carrier accumulation capability in the floating semiconductor region or the insulating layer. This is because, as described above, when the accumulation amount of minority carriers in the body region increases, the destruction of the semiconductor device tends to be a problem. Therefore, in the present invention, as an example, it is preferable that the film thickness of the second conductivity type semiconductor region is smaller than the film thickness of the floating semiconductor region or the insulating layer. In this case, the on-voltage is reduced and the destruction of the semiconductor device is suppressed. Note that the present invention is not limited to this example, and the same effect can be obtained by adjusting the impurity concentration and volume of the emitter region.

フローティング半導体領域がゲート絶縁膜に接するとともに、ボディコンタクト領域とドリフト領域を接続するボディ領域が確保されているのが好ましい。
フローティング半導体領域がゲート絶縁膜に接して形成されていると、蓄積される少数キャリアに伴うフローティング半導体領域直下のボディ領域の電位上昇に追随して、フローティング半導体領域の電位も上昇する。この電位の上昇により、フローティング半導体領域からボディ領域とドリフト領域に向けて多数キャリアが供給され、いわゆるサイリスタ動作がオンされる。これにより、このフローティング半導体領域は少数キャリアの蓄積によるオン電圧の低減化とともに、サイリスタ動作によるオン電圧の低減化をも実現する。さらに、本発明では、ボディコンタクト領域とドリフト領域を接続するボディ領域が確保されている。即ち、フローティング半導体領域が、ボディコンタクト領域とドリフト領域との間を隔てるようにボディ領域の全領域に亘って形成されているのではなく、少なくともその一部はボディ領域を介してボディコンタクト領域とドリフト領域を結んでいるのである。これにより、フローティング半導体領域によって蓄積される少数キャリアが、その経路を経由してボディコンタクト領域へと確実に排出される。したがって、半導体装置が安定的にターンオフすることができる。 It is preferable that the floating semiconductor region is in contact with the gate insulating film and a body region for connecting the body contact region and the drift region is secured.
If the floating semiconductor region is formed in contact with the gate insulating film, the potential of the floating semiconductor region also rises following the potential increase of the body region immediately below the floating semiconductor region due to the accumulated minority carriers. Due to this rise in potential, majority carriers are supplied from the floating semiconductor region toward the body region and the drift region, and so-called thyristor operation is turned on. As a result, the floating semiconductor region realizes a reduction in on-voltage due to thyristor operation as well as reduction in on-voltage due to minority carrier accumulation. Furthermore, in the present invention, a body region connecting the body contact region and the drift region is secured. That is, the floating semiconductor region is not formed over the entire region of the body region so as to separate the body contact region and the drift region, but at least a part of the floating semiconductor region is connected to the body contact region via the body region. It connects the drift region. Thereby, minority carriers accumulated in the floating semiconductor region are reliably discharged to the body contact region via the path. Therefore, the semiconductor device can be stably turned off.

第２導電型半導体領域とボディ領域の接合界面近傍に、ボディ領域の不純物濃度よりも不純物濃度が高い第１導電型半導体領域が形成されており、その第１半導体領域の一部はボディコンタクト領域と接するのが好ましい。第１導電型半導体領域は、第２導電型半導体領域の内部に形成されていても構わない。
この第１導電型半導体領域を形成することで、少数キャリアが第２導電型半導体領域を経由して排出されるのを抑制することができる。即ちラッチアップ現象が抑制される。したがって、トレードオフの関係が改善されボディ領域の不純物濃度を小さくすることができる。ボディ領域の不純物濃度を小さくすることができるので、ボディ領域内の少数キャリア濃度が高まり、ひいてはオン電圧が低減される。
また、フローティング半導体領域及び／又は絶縁層が形成され少数キャリアの蓄積能力が高まると、ラッチアップ現象の発生がとくに問題となり易いが、この種の半導体装置に対して上記の第１導電型半導体領域を備えることでラッチアップ現象が回避される。したがって、フローティング半導体領域及び／又は絶縁層が形成された半導体装置では、第１半導体領域を形成するのがとくに好適である。 A first conductivity type semiconductor region having an impurity concentration higher than the impurity concentration of the body region is formed in the vicinity of the junction interface between the second conductivity type semiconductor region and the body region, and a part of the first semiconductor region is a body contact region. It is preferable to touch. The first conductivity type semiconductor region may be formed inside the second conductivity type semiconductor region.
By forming the first conductivity type semiconductor region, minority carriers can be suppressed from being discharged through the second conductivity type semiconductor region. That is, the latch-up phenomenon is suppressed. Therefore, the trade-off relationship is improved and the impurity concentration in the body region can be reduced. Since the impurity concentration in the body region can be reduced, the minority carrier concentration in the body region is increased, and thus the on-voltage is reduced.
In addition, when the floating semiconductor region and / or the insulating layer is formed and the ability to accumulate minority carriers is increased, the occurrence of latch-up phenomenon is particularly likely to be a problem. By providing the latch-up phenomenon is avoided. Therefore, it is particularly preferable to form the first semiconductor region in the semiconductor device in which the floating semiconductor region and / or the insulating layer is formed.

フローティング半導体領域及び／又は絶縁層がボディコンタクト領域と接するのが好ましい。典型的には、ボディコンタクト領域とボディ領域の接合界面や、ボディコンタクト領域の内部に形成されているのが好ましい。
上記の位置関係に形成されるフローティング半導体領域及び／又は絶縁層は、少数キャリアの蓄積効果が大きく有効である。ボディ領域内の少数キャリア濃度が高まり、ひいてはオン電圧が低減化される。 The floating semiconductor region and / or the insulating layer is preferably in contact with the body contact region. Typically, it is preferably formed at the junction interface between the body contact region and the body region or inside the body contact region.
The floating semiconductor region and / or the insulating layer formed in the above positional relationship has a great effect of accumulating minority carriers. The minority carrier concentration in the body region is increased, and consequently the on-voltage is reduced.

本発明の他の一つの半導体装置は、ボディコンタクト領域とボディ領域の接合界面近傍に第２導電型の第１フローティング半導体領域が形成されており、ボディ領域とドリフト領域の接合界面近傍に第２導電型の第２フローティング半導体領域が形成されていることを特徴としている。第２フローティング半導体領域は、ドリフト領域と離反して形成されており、フローティング状態である。   According to another semiconductor device of the present invention, the first conductivity type first floating semiconductor region is formed in the vicinity of the junction interface between the body contact region and the body region, and the second conductivity type is formed in the vicinity of the junction interface between the body region and the drift region. A conductive type second floating semiconductor region is formed. The second floating semiconductor region is formed away from the drift region and is in a floating state.

ドリフト領域からボディ領域そしてボディコンタクト領域を亘ってエミッタ電極へ排出される少数キャリア濃度は、ドリフト領域とボディ領域のｐｎ接合界面で最も小さくなり易い。上記の半導体装置の場合、第２フローティング半導体領域によって、少数キャリアは上記のｐｎ接合界面近傍に溜められ、さらに第１フローティング半導体領域によってボディ領域内にも溜められる。
上記の半導体装置によると、ボディ領域とドリフト領域のｐｎ接合界面と、ボディ領域内の少数キャリアの濃度を同時に高くすることができる。これによりボディ領域内の広い範囲に亘って少数キャリア濃度が高くなり、ひいては一対の主電極間の少数キャリア濃度が高くなる。このためオン電圧の低減を実現できる。 The minority carrier concentration discharged from the drift region to the emitter electrode across the body region and body contact region is likely to be the smallest at the pn junction interface between the drift region and the body region. In the case of the semiconductor device described above, minority carriers are stored in the vicinity of the pn junction interface by the second floating semiconductor region, and further stored in the body region by the first floating semiconductor region.
According to the above-described semiconductor device, the pn junction interface between the body region and the drift region and the minority carrier concentration in the body region can be simultaneously increased. This increases the minority carrier concentration over a wide range in the body region, and consequently increases the minority carrier concentration between the pair of main electrodes. For this reason, reduction of on-voltage can be realized.

本発明の他の一つの半導体装置は、ボディコンタクト領域とボディ領域の接合界面近傍に第２導電型の第１フローティング半導体領域が形成されており、ボディ領域とドリフト領域の接合界面近傍に、その不純物濃度がドリフト領域の不純物濃度よりも高い第２導電型の高濃度半導体領域が形成されていることを特徴としている。
高濃度半導体領域は、ボディ領域とドリフト領域の接合界面近傍であり、ボディ領域と接していても、あるいは離反していてもよい。
高濃度半導体領域の不純物濃度がドリフト領域の不純物濃度よりも高ければ、ドリフト領域からボディ領域そしてボディコンタクト領域を亘ってエミッタ電極へ排出される少数キャリアは、高濃度半導体領域によってドリフト領域とボディ領域のｐｎ接合界面近傍に溜められる。さらに、第２導電型の半導体領域を抜けてエミッタ電極へと排出される少数キャリアは、第１フローティング半導体領域によってボディ領域内に溜められる。したがって、一対の主電極間の少数キャリア濃度が高くなる。このためオン電圧の低減を実現できる。 In another semiconductor device of the present invention, a first floating semiconductor region of the second conductivity type is formed in the vicinity of the junction interface between the body contact region and the body region, and in the vicinity of the junction interface between the body region and the drift region, A high-concentration semiconductor region of the second conductivity type whose impurity concentration is higher than the impurity concentration of the drift region is formed.
The high-concentration semiconductor region is in the vicinity of the junction interface between the body region and the drift region, and may be in contact with or separated from the body region.
If the impurity concentration of the high-concentration semiconductor region is higher than the impurity concentration of the drift region, minority carriers discharged from the drift region to the emitter electrode across the body region and body contact region are caused by the high-concentration semiconductor region to the drift region and the body region. In the vicinity of the pn junction interface. Furthermore, minority carriers that pass through the second conductivity type semiconductor region and are discharged to the emitter electrode are accumulated in the body region by the first floating semiconductor region. Accordingly, the minority carrier concentration between the pair of main electrodes is increased. For this reason, reduction of on-voltage can be realized.

第１フローティング半導体領域の少なくとも一部と、第２フローティング半導体領域又は高濃度半導体領域の少なくとも一部が、少数キャリアの経路に位置していることが好ましい。
ドリフト領域からボディ領域そしてボディコンタクト領域を亘ってエミッタ電極へ排出される少数キャリアの経路に対して、上記の各構成要素が位置していると、その少数キャリアを溜める効果を有効に活用することができる。 It is preferable that at least a part of the first floating semiconductor region and at least a part of the second floating semiconductor region or the high-concentration semiconductor region are located in the minority carrier path.
When each of the above components is located on the minority carrier path that is discharged from the drift region to the emitter electrode across the body region and body contact region, the effect of accumulating the minority carriers must be effectively utilized. Can do.

第１導電型のボディ領域内に複数個の第２導電型のフローティング半導体領域が分散配置されていることが好ましい。
フローティング半導体領域の形状はとくに限定されるものでない。また、その形成位置もとくに限定されず、例えば一対の電極間方向にフローティング半導体領域とボディ領域が交互に複数形成されていたり、また一対の電極間方向に直交する面内で部分的に配置されていてもよく、要はボディ領域内において空間的に分散配置されていればよい。
第１フローティング半導体領域と、第２フローティング半導体領域のみの場合に比して、ボディ領域の全領域に亘って少数キャリア濃度をさらに高くすることができる。オン電圧がさらに低減される。 It is preferable that a plurality of second conductivity type floating semiconductor regions are dispersedly arranged in the first conductivity type body region.
The shape of the floating semiconductor region is not particularly limited. Also, the formation position is not particularly limited. For example, a plurality of floating semiconductor regions and body regions are alternately formed in the direction between a pair of electrodes, or are partially disposed in a plane orthogonal to the direction between the pair of electrodes. In short, it is only necessary to be spatially distributed in the body region.
Compared with the case of only the first floating semiconductor region and the second floating semiconductor region, the minority carrier concentration can be further increased over the entire body region. The on-voltage is further reduced.

本発明に係る半導体装置によれば、ボディ領域内において少数キャリアを蓄積することができる。少数キャリア濃度が高くなりオン電圧が低減される。   According to the semiconductor device of the present invention, minority carriers can be accumulated in the body region. The minority carrier concentration increases and the on-voltage is reduced.

最初に実施例の主要な特徴を列記する。
(第１実施形態) 一対の主電極と、その一対の主電極間を流れる電流のオン・オフを制御するゲート電極を備えており、一方の主電極（例えばエミッタ電極）と接続する第１導電型（例えばｐ型）のボディコンタクト領域と、その主電極と接続する第２導電型（例えばｎ型）のエミッタ領域と、そのボディコンタクト領域とエミッタ領域の少なくとも一部と接する第１導電型のボディ領域と、そのボディ領域と接するとともに、ボディコンタクト領域及びエミッタ領域からはボディ領域によって隔てられている第２導電型のドリフト領域と、そのドリフト領域と接するとともに、ボディ領域からはそのドリフト領域によって隔てられ、他方の主電極（例えばコレクタ電極）と接続する第１導電型のコレクタ領域と、前記エミッタ領域とドリフト領域を隔てるボディ領域にゲート絶縁膜を介して対向するゲート電極とを備えているＩＧＢＴ構造の半導体装置において、ボディコンタクト領域とボディ領域の接合界面近傍に第２導電型の第１フローティング半導体領域が形成されており、ボディ領域とドリフト領域の接合界面近傍に第２導電型の半導体領域が形成されていることを特徴とする半導体装置。
(第２実施形態) 一対の主電極と、その一対の主電極間を流れる電流のオン・オフを制御するゲート電極を備えており、一方の主電極（例えばソース電極）と接続する第１導電型（例えばｐ型）のボディコンタクト領域と、その主電極と接続する第２導電型（例えばｎ型）のソース領域と、そのボディコンタクト領域とソース領域の少なくとも一部と接する第１導電型のボディ領域と、そのボディ領域と接するとともに、ボディコンタクト領域及びソース領域からはボディ領域によって隔てられている第２導電型のドリフト領域と、そのドリフト領域と接するとともに、ボディ領域からはそのドリフト領域によって隔てられ、他方の主電極（例えばドレイン電極）と接続する第２導電型のドレイン領域と、前記ソース領域とドリフト領域を隔てるボディ領域にゲート絶縁膜を介して対向するゲート電極とを備えているＭＯＳ型の半導体装置において、ボディコンタクト領域とボディ領域の接合界面近傍に第２導電型の第１フローティング半導体領域が形成されており、ボディ領域とドリフト領域の接合界面近傍に第２導電型の半導体領域が形成されていることを特徴とする半導体装置。
(第３実施形態) 第１実施形態または第２実施形態の第２導電型の半導体領域がフローティング状態である。
(第４実施形態) 第１実施形態または第２実施形態の第２導電型の半導体領域の不純物濃度が、ドリフト領域の不純物濃度よりも高い。 First, the main features of the embodiment are listed.
First Embodiment A pair of main electrodes, and a gate electrode that controls on / off of a current flowing between the pair of main electrodes, are provided, and the first conductivity is connected to one main electrode (for example, an emitter electrode). Type (for example, p-type) body contact region, a second conductivity type (for example, n-type) emitter region connected to the main electrode, and a first conductivity type in contact with at least part of the body contact region and the emitter region A body region and a second conductivity type drift region that is in contact with the body region and separated from the body contact region and the emitter region by the body region, and in contact with the drift region, and from the body region by the drift region A collector region of a first conductivity type that is separated and connected to the other main electrode (for example, a collector electrode), and the emitter region and the drift In a semiconductor device having an IGBT structure having a body region that separates a region and a gate electrode facing each other with a gate insulating film interposed therebetween, a first floating semiconductor region of a second conductivity type is provided in the vicinity of the junction interface between the body contact region and the body region. A semiconductor device, wherein a semiconductor region of the second conductivity type is formed in the vicinity of the junction interface between the body region and the drift region.
Second Embodiment A pair of main electrodes and a gate electrode that controls on / off of a current flowing between the pair of main electrodes are provided, and the first conductivity is connected to one of the main electrodes (for example, a source electrode). Type (for example, p-type) body contact region, a second conductivity type (for example, n-type) source region connected to the main electrode, and a first conductivity type in contact with at least part of the body contact region and the source region A body region and a second conductivity type drift region that is in contact with the body region and separated from the body contact region and the source region by the body region, and in contact with the drift region, and from the body region by the drift region A drain region of a second conductivity type that is separated and connected to the other main electrode (for example, a drain electrode), and the source region and the drift region are separated In a MOS type semiconductor device having a gate electrode opposed to a body region via a gate insulating film, a second floating type first floating semiconductor region is formed in the vicinity of the junction interface between the body contact region and the body region. And a second conductivity type semiconductor region is formed in the vicinity of the junction interface between the body region and the drift region.
Third Embodiment The second conductivity type semiconductor region of the first embodiment or the second embodiment is in a floating state.
Fourth Embodiment The impurity concentration of the second conductivity type semiconductor region of the first embodiment or the second embodiment is higher than the impurity concentration of the drift region.

(第１実施例) 図１に、第１実施例の半導体装置１の要部断面図を示す。半導体装置１はエミッタ・コレクタ電極間を流れる電流のオン・オフを制御するトレンチゲート電極３２を備えた半導体装置である。
この半導体装置１は、エミッタ電極Ｅと接続するｐ＋型の不純物を含有するボディコンタクト領域３４とｎ＋型の不純物を含有するエミッタ領域３６を備える。そのボディコンタクト領域３４とエミッタ領域３６を囲繞するｐ−型の不純物を含有するボディ領域２８を備える。そのボディ領域２８の下方に接するｎ−型の不純物を含有するドリフト領域２６を備えており、そのドリフト領域２６は、ボディコンタクト領域３４とエミッタ領域３６からボディ領域２８によって隔てられている。
エミッタ領域３６とボディ領域２８を貫通してドリフト領域２６に達するトレンチが形成されている。そのトレンチにはポリシリコンが埋設され、トレンチゲート電極３２が形成されている。トレンチゲート電極３２は、ゲート絶縁膜３３を介してボディ領域２８に対向している。
ドリフト領域２６の下方に接してｎ＋型の不純物を含有するバッファ領域２４が形成され、そのバッファ領域２４の下方にはｐ＋型の不純物を含有するコレクタ領域２２が形成されている。このコレクタ領域２２にはアルミニウム等からなるコレクタ電極Ｃが接続さている。
ボディ領域２８内に、ｎ型の不純物を含有するフローティング半導体領域４０が形成されており、フローティング半導体領域４０はボディコンタクト領域３４に接している。
各半導体領域の不純物濃度は、コレクタ領域２２が1×1018〜1×1020cm-3の範囲であり、バッファ領域２４が1×1015〜1×1018cm-3の範囲であり、ドリフト領域２６が1×1013〜1×1015cm-3の範囲であり、ボディ領域２８が1×1015〜1×1018cm-3の範囲であり、ボディコンタクト領域３４が1×1018〜1×1020cm-3の範囲であり、エミッタ領域３６が1×1018〜1×1020cm-3の範囲で形成されるのが好ましい。そして、フローティング半導体領域４０の不純物濃度はとくに限定するものではないが、1×1015〜1×1018cm-3の範囲であるのが好ましい。この範囲内であると、少数キャリアをよく蓄積することができる。 First Embodiment FIG. 1 shows a cross-sectional view of a main part of a semiconductor device 1 according to a first embodiment. The semiconductor device 1 is a semiconductor device provided with a trench gate electrode 32 for controlling on / off of a current flowing between the emitter and collector electrodes.
The semiconductor device 1 includes a body contact region 34 containing a p + type impurity connected to the emitter electrode E and an emitter region 36 containing an n + type impurity. A body region 28 containing p − type impurities surrounding the body contact region 34 and the emitter region 36 is provided. A drift region 26 containing an n − -type impurity is provided under the body region 28, and the drift region 26 is separated from the body contact region 34 and the emitter region 36 by the body region 28.
A trench reaching the drift region 26 through the emitter region 36 and the body region 28 is formed. Polysilicon is buried in the trench, and a trench gate electrode 32 is formed. The trench gate electrode 32 faces the body region 28 with the gate insulating film 33 interposed therebetween.
A buffer region 24 containing an n + -type impurity is formed in contact with the lower portion of the drift region 26, and a collector region 22 containing a p + -type impurity is formed below the buffer region 24. A collector electrode C made of aluminum or the like is connected to the collector region 22.
A floating semiconductor region 40 containing n-type impurities is formed in the body region 28, and the floating semiconductor region 40 is in contact with the body contact region 34.
The impurity concentration of each semiconductor region is in the range of 1 × 10 18 to 1 × 10 20 cm −3 in the collector region 22 and in the range of 1 × 10 15 to 1 × 10 18 cm −3 in the buffer region 24. The drift region 26 is in the range of 1 × 10 13 to 1 × 10 15 cm −3 , the body region 28 is in the range of 1 × 10 15 to 1 × 10 18 cm −3 , and the body contact region 34 is 1 × 10 10. 18 in the range of ~1 × 10 20 cm -3, preferably emitter region 36 is formed in a range of 1 × 10 18 ~1 × 10 20 cm -3. The impurity concentration of the floating semiconductor region 40 is not particularly limited, but is preferably in the range of 1 × 10 15 to 1 × 10 18 cm −3 . Within this range, minority carriers can be accumulated well.

次に半導体装置１がオン状態のときの動作を説明する。
エミッタ電極Ｅを接地し、コレクタ電極Ｃとトレンチゲート電極３２に正電圧を印加すると、ボディ領域２８のうちトレンチゲート電極３２と対向する箇所がｎ型に反転される。電子キャリアがエミッタ領域３４からそのｎ型に反転した箇所をトレンチゲート電極３２に沿って通過し、ドリフト領域２６へと注入される。ドリフト領域２６に注入された電子キャリアは、そのドリフト領域２６内をコレクタ電極Ｃ側へ向かって流れ、電子キャリアはバッファ領域２４内に蓄積する。電子キャリアがバッファ領域２４に蓄積すると、バッファ領域２４とコレクタ領域２２の接触電位差が低下し、コレクタ領域２２からバッファ領域２４とドリフト領域２６へ正孔キャリアが注入される。これによりバッファ領域２４及びドリフト領域２６に伝導度変調が起こり、低いオン電圧を実現する。 Next, an operation when the semiconductor device 1 is in the on state will be described.
When the emitter electrode E is grounded and a positive voltage is applied to the collector electrode C and the trench gate electrode 32, the portion of the body region 28 facing the trench gate electrode 32 is inverted to n-type. Electron carriers pass from the emitter region 34 to the n-type inverted portion along the trench gate electrode 32 and are injected into the drift region 26. The electron carriers injected into the drift region 26 flow in the drift region 26 toward the collector electrode C, and the electron carriers accumulate in the buffer region 24. When the electron carriers accumulate in the buffer region 24, the contact potential difference between the buffer region 24 and the collector region 22 decreases, and hole carriers are injected from the collector region 22 into the buffer region 24 and the drift region 26. As a result, conductivity modulation occurs in the buffer region 24 and the drift region 26, thereby realizing a low on-voltage.

コレクタ領域２２から注入された正孔キャリアは、電子キャリアと再結合して消滅するか、ボディ領域２８とボディコンタクト領域３４を亘ってエミッタ電極Ｅへと排出される。本実施例ではこの正孔キャリアの排出路に介在する位置関係にフローティング半導体領域４０が形成されている。
このフローティング半導体領域４０とボディ領域２８の接合界面にポテンシャル障壁が形成され、そのためこのフローティング半導体領域４０を経由してボディコンタクト領域３４へと流れようとする正孔キャリアの流動が妨げられる。とくに、本実施例のフローティング半導体領域４０は、ボディコンタクト領域３４に接する位置関係に形成されており、少数キャリアの流動を妨げる効果が大きい。その結果、ボディ領域２８内に正孔キャリアが蓄積されることになり、ひいてはオン電圧が低減される。 The hole carriers injected from the collector region 22 are recombined with electron carriers and disappear, or are discharged to the emitter electrode E across the body region 28 and the body contact region 34. In this embodiment, the floating semiconductor region 40 is formed in a positional relationship interposed in the hole carrier discharge path.
A potential barrier is formed at the junction interface between the floating semiconductor region 40 and the body region 28, so that the flow of hole carriers that attempt to flow to the body contact region 34 via the floating semiconductor region 40 is hindered. In particular, the floating semiconductor region 40 of the present embodiment is formed in a positional relationship in contact with the body contact region 34 and has a great effect of preventing minority carrier flow. As a result, hole carriers are accumulated in the body region 28, and as a result, the on-voltage is reduced.

(第２実施例) 図２に第２実施例の半導体装置２の要部断面図を示す。なお、図1の半導体装置１と略同一の構成に関しては、同一の番号を付してその説明を省略する。
図示４２は、フローティング半導体領域である。このフローティング半導体領域４２は、ドリフト領域２６とボディコンタクト領域３４を結ぶ正孔キャリアの排出路に介在する位置関係に形成されている。そのため正孔キャリアの蓄積効果を有する。
本実施例の特徴は、エミッタ領域３５の膜厚(Ｌ１)が、フローティング半導体領域４２の膜厚(Ｌ２)よりも小さいことである。フローティング半導体領域４２による正孔キャリアの蓄積に伴って、エミッタ領域３５から電子キャリアが供給され、半導体装置２のオン電圧は低減される。しかしながら、このエミッタ領域３５の電子キャリアの供給能力が大きすぎると、飽和電流値が増加して半導体装置の破壊が生じ易くなる。このエミッタ領域３５の電子キャリアの供給能力はその領域に含有される不純物量と関係している。したがって、エミッタ領域３５の不純物濃度を小さくしたり、体積を小さくしたり、あるいはエミッタ領域３５を分散配置させるなどの対処を施すことで、電子キャリアの供給能力を小さくすることができる。エミッタ領域３５の電子キャリアの供給能力を小さくすることで、半導体装置の破壊を抑制できる。また、この電子キャリアの供給能力は、正孔キャリアの蓄積能力との関係で設定されるのが好ましく、例えば、正孔キャリアの蓄積能力が大きい場合ほど、電子キャリアの供給能力を下げて半導体装置２が破壊されるのを抑制するのが好適である。
本実施例では、フローティング半導体領域４２の膜厚(Ｌ２)に着目し、このフローティング半導体領域４２の膜厚(Ｌ２)に比して、エミッタ領域３５の膜厚(Ｌ１)を小さく設定することで正孔キャリアの蓄積能力と電子キャリアの供給能力をバランスさせている。この関係で形成されていると、オン電圧が低減されるとともに、半導体装置２が破壊されるのを抑制することができる。
なお、上記で説明したように、要は正孔キャリアの蓄積効果と電子キャリアの供給能力をバランスさせる設定をすればよく、例えば、エミッタ領域３５の体積や、不純物濃度や、幅などで両者をバランスさせる設定を規定してもよい。同様の作用効果を得ることができる。 Second Embodiment FIG. 2 shows a cross-sectional view of the main part of a semiconductor device 2 according to a second embodiment. In addition, about the structure substantially the same as the semiconductor device 1 of FIG. 1, the same number is attached and the description is abbreviate | omitted.
42 is a floating semiconductor region. The floating semiconductor region 42 is formed in a positional relationship interposed in a hole carrier discharge path connecting the drift region 26 and the body contact region 34. Therefore, it has the effect of accumulating hole carriers.
The feature of this embodiment is that the film thickness (L1) of the emitter region 35 is smaller than the film thickness (L2) of the floating semiconductor region 42. As hole carriers accumulate in the floating semiconductor region 42, electron carriers are supplied from the emitter region 35, and the on-voltage of the semiconductor device 2 is reduced. However, if the electron carrier supply capability of the emitter region 35 is too large, the saturation current value increases and the semiconductor device is easily destroyed. The electron carrier supply capability of the emitter region 35 is related to the amount of impurities contained in the region. Therefore, by taking measures such as reducing the impurity concentration of the emitter region 35, reducing the volume, or disposing the emitter regions 35 in a distributed manner, the electron carrier supply capability can be reduced. By reducing the electron carrier supply capability of the emitter region 35, the semiconductor device can be prevented from being broken. The electron carrier supply capability is preferably set in relation to the hole carrier storage capability. For example, the higher the hole carrier storage capability, the lower the electron carrier supply capability and the semiconductor device. It is preferable to suppress the destruction of 2.
In this embodiment, paying attention to the film thickness (L2) of the floating semiconductor region 42, the film thickness (L1) of the emitter region 35 is set smaller than the film thickness (L2) of the floating semiconductor region 42. The storage capacity of hole carriers and the supply capacity of electron carriers are balanced. If formed in this relationship, the on-voltage can be reduced and the semiconductor device 2 can be prevented from being destroyed.
As described above, the point is to set the balance between the hole carrier accumulation effect and the electron carrier supply capability. For example, the volume of the emitter region 35, the impurity concentration, the width, etc. Settings to be balanced may be defined. Similar effects can be obtained.

(第３実施例) 図３に第３実施例の半導体装置３の要部断面図を示す。
図示４５は、フローティング半導体領域である。このフローティング半導体領域４５は、ドリフト領域２６とボディコンタクト領域３４を結ぶ正孔キャリアの排出路に介在する位置関係に形成されている。そのため正孔キャリアの蓄積効果を有する。
図示４７もフローティング半導体領域であり、正孔キャリアの蓄積効果を有する。さらに、このフローティング半導体領域４７はゲート絶縁膜３３に接して形成されている点に特徴がある。このため、このフローティング半導体領域４７はサイリスタ動作を実現するのである。この半導体装置３がオンすると、フローティング半導体領域４７の直下のボディ領域２８に正孔キャリアが蓄積され、それに追随してフローティング半導体領域４７の電位が持ち上がる。すると、エミッタ領域３６からゲート絶縁膜３３に沿って供給される電子キャリアは、フローティング半導体領域４７を利用して面的に広がってボディ領域２８とドリフト領域２６に向けて注入される。このため、このフローティング半導体領域４７は、正孔キャリアの蓄積とともにサイリスタ動作を実現する。したがって、オン電圧が極めて低減される。
なお、従来から高濃度のフローティング領域をボディ領域内に形成してサイリスタ動作を実現する技術は知られている。しかしながら、この種の半導体装置のフローティング半導体領域はサイリスタ動作の実現のみを目的としており、そのためその不純物濃度が高かった。したがって、過剰のキャリアが蓄積してしまい、ターンオフができなくなるという事態が発生していた。一方、本実施例のフローティング半導体領域４７は、正孔キャリアを蓄積させるとともに、その蓄積に伴って上昇する電位を利用してサイリスタ動作を実現している。したがって、このフローティング半導体領域４７の不純物濃度は、従来に比して低い濃度で十分である。なお、サイリスタ動作が生じ易いように、フローティング半導体領域４７とドリフト領域２６との距離(Ｌ３)は短い方が好ましい。
また、このフローティング半導体領域４７の他の特徴は、ボディコンタクト領域３４とドリフト領域２６の間の全領域に亘って介在していないことである。換言すると、フローティング半導体領域４７は、ゲート絶縁膜３３との接触面以外がボディ領域２８と接しているのである。即ち、ボディコンタクト領域３４とドリフト領域２６との間をボディ領域２８で結ぶ正孔キャリア排出路４７ａが形成されている。このため、ボディ領域２８に蓄積された正孔キャリアは、この排出路４７ａを経由してボディコンタクト領域３４に確実に排出される。ターンオフ動作が不安定となる事態を回避することができる。 Third Embodiment FIG. 3 shows a cross-sectional view of the main part of a semiconductor device 3 according to a third embodiment.
45 in the figure is a floating semiconductor region. The floating semiconductor region 45 is formed in a positional relationship interposed in a hole carrier discharge path connecting the drift region 26 and the body contact region 34. Therefore, it has the effect of accumulating hole carriers.
47 shown in the figure is also a floating semiconductor region and has an effect of accumulating hole carriers. Further, the floating semiconductor region 47 is characterized in that it is formed in contact with the gate insulating film 33. For this reason, the floating semiconductor region 47 realizes a thyristor operation. When the semiconductor device 3 is turned on, hole carriers are accumulated in the body region 28 immediately below the floating semiconductor region 47, and the potential of the floating semiconductor region 47 is raised following the accumulation. Then, the electron carriers supplied from the emitter region 36 along the gate insulating film 33 spread in a plane using the floating semiconductor region 47 and are injected toward the body region 28 and the drift region 26. For this reason, the floating semiconductor region 47 realizes a thyristor operation together with the accumulation of hole carriers. Therefore, the ON voltage is extremely reduced.
Conventionally, a technique for realizing a thyristor operation by forming a high concentration floating region in a body region is known. However, the floating semiconductor region of this type of semiconductor device is intended only for realizing a thyristor operation, and therefore has a high impurity concentration. Therefore, a situation has occurred in which excess carriers accumulate and turn-off cannot be performed. On the other hand, the floating semiconductor region 47 of the present embodiment accumulates hole carriers and realizes a thyristor operation by utilizing a potential that increases with the accumulation. Therefore, the impurity concentration of the floating semiconductor region 47 is sufficient if it is lower than the conventional one. Note that the distance (L3) between the floating semiconductor region 47 and the drift region 26 is preferably short so that the thyristor operation is likely to occur.
Another feature of the floating semiconductor region 47 is that it is not interposed over the entire region between the body contact region 34 and the drift region 26. In other words, the floating semiconductor region 47 is in contact with the body region 28 except for the contact surface with the gate insulating film 33. That is, a hole carrier discharge path 47 a that connects the body contact region 34 and the drift region 26 by the body region 28 is formed. For this reason, the hole carriers accumulated in the body region 28 are reliably discharged to the body contact region 34 via the discharge path 47a. A situation where the turn-off operation becomes unstable can be avoided.

図４に第３実施例の変形例の半導体装置４の要部断面図を示す。この変形例は、ゲート電極４３２がプレーナ型の一例である。
図示４４７が、正孔キャリアの蓄積とともに、サイリスタ動作を実現するフローティング半導体領域である。この場合も、フローティング半導体領域４４７は、ゲート絶縁膜４３３に接するとともに、正孔キャリア排出路４４７ａを確保しているので、オン電圧の低減と安定な動作を実現する。 FIG. 4 shows a cross-sectional view of a main part of a semiconductor device 4 of a modification of the third embodiment. In this modification, the gate electrode 432 is an example of a planar type.
Reference numeral 447 in the figure denotes a floating semiconductor region that realizes thyristor operation along with accumulation of hole carriers. Also in this case, since the floating semiconductor region 447 is in contact with the gate insulating film 433 and the hole carrier discharge path 447a is secured, reduction of the on-voltage and stable operation are realized.

(第４実施例) 図５に第４実施例の半導体装置５の要部断面図を示す。
本実施例の特徴は、エミッタ領域３６とボディ領域５２の間に介在してｐ型のラッチアップ防止領域５２が形成されている点である。このラッチアップ防止領域５２の不純物濃度はボディ領域２８よりも高く、さらにこのラッチアップ防止領域５２の一部はボディコンタクト領域３４と接している。
このラッチアップ防止領域５２を介在させることで、ボディ領域２８内に蓄積する正孔キャリアがエミッタ領域３６へ排出されるのを防止することができる。正孔キャリアは、ラッチアップ防止領域５２とボディコンタクト領域３４の接触面を経由してボディコン領域３４に排出される。このラッチアップ防止領域５２を備えることでオン電圧を低減することができるが、それは次のように説明できる。このラッチアップ防止領域５２が形成されていない場合を例にすると、ボディ領域２８の不純物濃度を下げてボディ領域２８の少数キャリア濃度を上げようとしたならば、その蓄積された少数キャリアがエミッタ領域へと流動してラッチアップが生じ、半導体装置が破壊される事態が発生してしまう。したがって、ラッチアップ現象とオン電圧の低減化はトレードオフの関係と言える。
そこで本実施例のラッチアップ防止領域５２を形成することで、このトレードオフの関係を打破することできる。即ち、ラッチアップ現象が抑制されるために、ボディ領域２８の不純物濃度を小さくすることができる。そのため、ボディ領域２８の正孔キャリア濃度を上げることができる。ひいては、オン電圧が低減されるのである。 Fourth Embodiment FIG. 5 shows a cross-sectional view of a main part of a semiconductor device 5 according to a fourth embodiment.
The feature of this embodiment is that a p-type latch-up prevention region 52 is formed between the emitter region 36 and the body region 52. The impurity concentration of the latch-up prevention region 52 is higher than that of the body region 28, and a part of the latch-up prevention region 52 is in contact with the body contact region 34.
By interposing the latch-up prevention region 52, it is possible to prevent the hole carriers accumulated in the body region 28 from being discharged to the emitter region 36. The hole carriers are discharged to the bodycon region 34 via the contact surface between the latch-up prevention region 52 and the body contact region 34. The on-voltage can be reduced by providing the latch-up prevention region 52, which can be explained as follows. Taking the case where the latch-up prevention region 52 is not formed as an example, if the impurity concentration of the body region 28 is decreased to increase the minority carrier concentration of the body region 28, the accumulated minority carriers are transferred to the emitter region. As a result, the semiconductor device is destroyed. Therefore, it can be said that the latch-up phenomenon and the reduction of the ON voltage are in a trade-off relationship.
Therefore, the trade-off relationship can be overcome by forming the latch-up prevention region 52 of the present embodiment. That is, since the latch-up phenomenon is suppressed, the impurity concentration in the body region 28 can be reduced. Therefore, the hole carrier concentration in the body region 28 can be increased. As a result, the on-voltage is reduced.

(第５実施例) 図６に第５実施例の半導体装置６の要部断面図を示す。
図示５４がラッチアップを防止するラッチアップ防止領域であるとともに、エミッタ電極Ｅと直接接続している。したがって、正孔キャリアはこのラッチアップ防止領域５４を経由してエミッタ電極Ｅへと排出される。このラッチアップ防止領域５４はエミッタ領域３６を囲繞して形成されている。
ラッチアップ防止領域５４を囲繞してｎ型の半導体領域が形成されている。このｎ型の半導体領域４８は正孔キャリアの蓄積効果を有している。このため、この半導体装置６のオン電圧は低減される。
本実施例では、ｐ−型のボディ領域２８が、ｎ型の半導体領域４８とｎ−型のドリフト領域に挟まれているために、この半導体装置６がオフしたときにその両層から空乏層が素早く広がる。そのため、早いスイッチング速度を実現することができる。 Fifth Embodiment FIG. 6 shows a cross-sectional view of the main part of a semiconductor device 6 according to a fifth embodiment.
54 is a latch-up prevention region for preventing latch-up and is directly connected to the emitter electrode E. Therefore, hole carriers are discharged to the emitter electrode E through the latch-up prevention region 54. This latch-up prevention region 54 is formed surrounding the emitter region 36.
An n-type semiconductor region is formed surrounding the latch-up prevention region 54. The n-type semiconductor region 48 has a hole carrier accumulation effect. For this reason, the on-voltage of the semiconductor device 6 is reduced.
In this embodiment, since the p − type body region 28 is sandwiched between the n type semiconductor region 48 and the n − type drift region, a depletion layer is formed from both layers when the semiconductor device 6 is turned off. Spreads quickly. Therefore, a fast switching speed can be realized.

(第６実施例) 図７に第６実施例の半導体装置７の要部断面図を示す。本実施例では、正孔キャリアの蓄積に、絶縁層６２とフローティング半導体領域４９を同時に利用している。
絶縁層６２はドリフト領域２６からボディコンタクト領域３４へと排出される正孔キャリアの排出路に介在されるように、ボディコンタクト領域３４の直下に形成されている。したがって、正孔キャリアの蓄積効果が極めて大きい。
そして、ゲート電極３３側にはフローティング半導体領域４９が形成されている。このフローティング半導体領域４９の不純物濃度は比較的小さく、キャリアの蓄積効果はそれほど大きくない。しかしながら、ゲート電極３３に沿った位置に形成されているために、電子キャリアに対する抵抗を小さくすることができる。また、この半導体装置７をオフしたときは、このフローティング半導体領域４９を経由してボディ領域２８に蓄積された正孔キャリアを排出することができる。ターンオフを安定的に動作させることができる。
本実施例の特徴は、絶縁層６２とフローティング半導体領域４９を同時に利用することで、正孔キャリアの蓄積と、電子キャリアに対する抵抗と、ターンオフ時の正孔キャリアの排出とをバランスよく具備する半導体装置を実現することができる。所望の特性を備えた半導体装置を実現し易い。 (Sixth Embodiment) FIG. 7 shows a cross-sectional view of a main part of a semiconductor device 7 according to a sixth embodiment. In this embodiment, the insulating layer 62 and the floating semiconductor region 49 are simultaneously used for the accumulation of hole carriers.
The insulating layer 62 is formed directly under the body contact region 34 so as to be interposed in a hole carrier discharge path discharged from the drift region 26 to the body contact region 34. Therefore, the hole carrier accumulation effect is extremely large.
A floating semiconductor region 49 is formed on the gate electrode 33 side. The impurity concentration of the floating semiconductor region 49 is relatively small, and the carrier accumulation effect is not so great. However, since it is formed at a position along the gate electrode 33, the resistance to electron carriers can be reduced. In addition, when the semiconductor device 7 is turned off, the hole carriers accumulated in the body region 28 can be discharged via the floating semiconductor region 49. The turn-off can be stably operated.
A feature of the present embodiment is that the insulating layer 62 and the floating semiconductor region 49 are used at the same time, so that the semiconductor has a well-balanced hole carrier accumulation, resistance to electron carriers, and discharge of hole carriers at turn-off. An apparatus can be realized. It is easy to realize a semiconductor device having desired characteristics.

(第７実施例) 図８に、第７実施例の半導体装置８の要部断面図を示す。本実施例では、正孔キャリアを蓄積させる半導体領域を多層に形成することで、ボディ領域２８内の正孔キャリア濃度をさらに増加させた一例である。
まず、ドリフト領域２６上にそのドリフト領域２６よりも不純物が高濃度なｎ＋型の高濃度半導体領域４０ａが形成されている。さらに、ボディコンタクト領域３４とボディ領域２８のｐｎ接合界面の近傍にはｎ＋型の第１フローティング半導体領域４０ｂが形成されている。
半導体領域の不純物濃度は、高濃度半導体領域４０ａが1×1015〜1×1017cm-3の範囲であり、第１フローティング半導体領域が1×1015〜1×1018cm-3の範囲で形成されるのが好ましい。 (Seventh Embodiment) FIG. 8 shows a cross-sectional view of a main part of a semiconductor device 8 according to a seventh embodiment. The present embodiment is an example in which the hole carrier concentration in the body region 28 is further increased by forming multiple semiconductor regions in which hole carriers are accumulated.
First, an n + type high concentration semiconductor region 40 a having a higher concentration of impurities than the drift region 26 is formed on the drift region 26. Further, an n + type first floating semiconductor region 40 b is formed in the vicinity of the pn junction interface between the body contact region 34 and the body region 28.
The impurity concentration of the semiconductor region is in the range of 1 × 10 15 to 1 × 10 17 cm −3 for the high concentration semiconductor region 40 a and in the range of 1 × 10 15 to 1 × 10 18 cm −3 for the first floating semiconductor region. Is preferably formed.

図９には半導体装置８の要部斜視図が示されている。
高濃度半導体領域４０ａ及び第１フローティング半導体領域４０ｂがエミッタ領域３４の下方に部分的に形成されており、第１フローティング半導体領域４０ｂの下方のボディ領域２８がボディコンタクト領域３６と接触しフローティング状態になっていない（紙面奥側で接続している）。この場合、半導体装置１がターンオフしたとき、ボディ領域２８内の正孔キャリアを素早く外部へ排出することができるために、スイッチング速度が速くなり好適である。
この構成に代えて、第１フローティング半導体領域４０ｂの下方のボディ領域２８が、チップ全体に亘ってフローティング状態になっていてもよい。この場合、チップ内部に溜められた正孔キャリアは、フローティング状態のボディ領域２８から第１フローティング半導体領域４０ｂを通過して表面に形成されているボディコンタクト領域３４へ流れこむ。即ち、第１フローティング半導体領域４０ｂと高濃度半導体領域４０ａの両層から、ボディ領域２８へ空乏層が伸びて、ボディ領域２８が素早く空乏化することからスイッチング速度が速くなり好適である。
なお、半導体装置８のように、高濃度半導体領域４０ａ及び第１フローティング半導体領域４０ｂが、エミッタ領域３４近傍のボディコンタクト領域３６の下方に形成されているのが好ましい。エミッタ電極Ｅへと排出される正孔キャリアは、エミッタ領域３４から注入される電子キャリアに引き寄せられ、エミッタ領域３４近傍のボディコンタクト領域３６からエミッタ電極Ｅへと排出される。つまり正孔キャリアの経路に高濃度半導体領域４０ａ及び第１フローティング半導体領域４０ｂが位置している。したがって、上記の箇所に半導体領域４０ａ及び第１フローティング半導体領域４０ｂが形成されていると効果的に正孔キャリアを溜めることができる。
なお、第１フローティング半導体領域４０ｂは、ボディ領域２８内部に形成されていてもよい。ボディ領域２８の内部に形成されることで、フローティング電位がより形成され易くなり、電界がかかりにくくなり高耐圧化を実現できる。 FIG. 9 is a perspective view of a main part of the semiconductor device 8.
The high concentration semiconductor region 40a and the first floating semiconductor region 40b are partially formed below the emitter region 34, and the body region 28 below the first floating semiconductor region 40b is in contact with the body contact region 36 and enters a floating state. Not connected (connected at the back of the page). In this case, when the semiconductor device 1 is turned off, the hole carriers in the body region 28 can be quickly discharged to the outside, which is preferable because the switching speed is increased.
Instead of this configuration, the body region 28 below the first floating semiconductor region 40b may be in a floating state over the entire chip. In this case, hole carriers accumulated in the chip flow from the floating body region 28 to the body contact region 34 formed on the surface through the first floating semiconductor region 40b. That is, a depletion layer extends from both the first floating semiconductor region 40b and the high concentration semiconductor region 40a to the body region 28, and the body region 28 is quickly depleted.
As in the semiconductor device 8, the high concentration semiconductor region 40 a and the first floating semiconductor region 40 b are preferably formed below the body contact region 36 near the emitter region 34. Hole carriers discharged to the emitter electrode E are attracted to electron carriers injected from the emitter region 34 and discharged from the body contact region 36 near the emitter region 34 to the emitter electrode E. That is, the high-concentration semiconductor region 40a and the first floating semiconductor region 40b are located in the hole carrier path. Therefore, when the semiconductor region 40a and the first floating semiconductor region 40b are formed at the above-described locations, hole carriers can be effectively stored.
The first floating semiconductor region 40b may be formed inside the body region 28. By being formed inside the body region 28, a floating potential is more easily formed, an electric field is hardly applied, and a high breakdown voltage can be realized.

次に半導体装置８がオン状態のときの動作を説明する。
エミッタ電極Ｅを接地し、コレクタ電極Ｃとトレンチゲート電極３２に正電圧を印加すると、ボディ領域２８のうちトレンチゲート電極３２と対向する箇所がｎ型に反転される。電子キャリアがエミッタ領域３４からそのｎ型に反転した箇所をトレンチゲート電極３２に沿って通過し、ドリフト領域２６へと注入される。ドリフト領域２６に注入された電子キャリアは、そのドリフト領域２６内をコレクタ電極Ｃ側へ向かって流れ、電子キャリアはバッファ領域２４内に蓄積する。電子キャリアがバッファ領域２４に蓄積すると、バッファ領域２４とコレクタ領域２２の接触電位差が低下し、コレクタ領域２２からバッファ領域２４とドリフト領域２６へ正孔キャリアが注入される。これによりバッファ領域２４及びドリフト領域２６に伝導度変調が起こり、低いオン電圧を実現する。 Next, the operation when the semiconductor device 8 is in the on state will be described.
When the emitter electrode E is grounded and a positive voltage is applied to the collector electrode C and the trench gate electrode 32, the portion of the body region 28 facing the trench gate electrode 32 is inverted to n-type. Electron carriers pass from the emitter region 34 to the n-type inverted portion along the trench gate electrode 32 and are injected into the drift region 26. The electron carriers injected into the drift region 26 flow in the drift region 26 toward the collector electrode C, and the electron carriers accumulate in the buffer region 24. When the electron carriers accumulate in the buffer region 24, the contact potential difference between the buffer region 24 and the collector region 22 decreases, and hole carriers are injected from the collector region 22 into the buffer region 24 and the drift region 26. As a result, conductivity modulation occurs in the buffer region 24 and the drift region 26, thereby realizing a low on-voltage.

コレクタ領域２２から注入された正孔キャリアは、電子キャリアと再結合して消滅するか、ボディ領域２８とボディコンタクト領域３４を亘ってエミッタ電極Ｅへと排出される。図８には、エミッタ電極Ｅへと排出される正孔キャリアが模式的に示されている。
まず、正孔キャリアは高濃度半導体領域４０ａとドリフト領域２６の接合界面に形成されるポテンシャル障壁によって、この接合界面近傍のドリフト領域２６内に溜められる。この高濃度半導体領域４０ａとドリフト領域２６の接合界面のポテンシャル障壁を超えてボディ領域２８に流入した正孔キャリアは、さらに第１フローティング半導体領域４０ｂとボディ領域２８の接合界面に形成されるポテンシャル障壁によって、この接合界面近傍のボディ領域２８内に溜められる。この第１フローティング半導体領域４０ｂとボディ領域２８の接合界面のポテンシャル障壁を超えた正孔キャリアはエミッタ電極へと排出される。 The hole carriers injected from the collector region 22 are recombined with electron carriers and disappear, or are discharged to the emitter electrode E across the body region 28 and the body contact region 34. FIG. 8 schematically shows the hole carriers discharged to the emitter electrode E.
First, hole carriers are accumulated in the drift region 26 near the junction interface by a potential barrier formed at the junction interface between the high-concentration semiconductor region 40 a and the drift region 26. The hole carriers that flow into the body region 28 beyond the potential barrier at the junction interface between the high-concentration semiconductor region 40a and the drift region 26 further form a potential barrier formed at the junction interface between the first floating semiconductor region 40b and the body region 28. Thus, it is accumulated in the body region 28 in the vicinity of the bonding interface. Hole carriers that exceed the potential barrier at the junction interface between the first floating semiconductor region 40b and the body region 28 are discharged to the emitter electrode.

図８のボディコンタクト領域３４から第１フローティング半導体領域４０ｂ、ボディ領域２８、高濃度半導体領域４０ａ、ドリフト領域２６、バッファ領域２４、そしてコレクタ領域２２までの図１０中Ｘ−Ｘ線に対応したエミッタ・コレクタ電極間の正孔キャリア濃度が図１０に示されている。
図１０の図面上端がエミッタ電極Ｅであり、図面下端がコレクタ電極Ｃであり、図面左端には対応する各領域の番号が示されている。横軸が正孔キャリア濃度であり、右側ほど正孔キャリア濃度が高い。
なお、図１０の図示１２が第７実施例の半導体装置８のエミッタ・コレクタ電極間の正孔キャリア濃度であり、図示１１が従来構造（高濃度半導体領域４０ａのみが形成されている場合に相当する）の正孔キャリア濃度であり、図示１０が第１フローティング半導体領域４０ｂや、高濃度半導体領域４０ａが形成されていない場合の正孔キャリア濃度である。 The emitter corresponding to the XX line in FIG. 10 from the body contact region 34 of FIG. 8 to the first floating semiconductor region 40b, the body region 28, the high concentration semiconductor region 40a, the drift region 26, the buffer region 24, and the collector region 22 The hole carrier concentration between the collector electrodes is shown in FIG.
The upper end of the drawing in FIG. 10 is the emitter electrode E, the lower end of the drawing is the collector electrode C, and the numbers of the corresponding regions are shown at the left end of the drawing. The horizontal axis is the hole carrier concentration, and the hole carrier concentration is higher on the right side.
10 shows the hole carrier concentration between the emitter and collector electrodes of the semiconductor device 8 of the seventh embodiment, and FIG. 11 shows the conventional structure (corresponding to the case where only the high-concentration semiconductor region 40a is formed). The hole carrier concentration shown in FIG. 10 is the hole carrier concentration when the first floating semiconductor region 40b and the high concentration semiconductor region 40a are not formed.

まず、図示１０の第１フローティング半導体領域４０ｂや、高濃度半導体領域４０ａが形成されていない場合を見てみると、ボディ領域２８とドリフト領域２６のｐｎ接合界面で正孔キャリア濃度が最も減少し、ボディ領域２８内の正孔キャリア濃度が低い状態で連続していることが分かる。また、ドリフト領域２６内の正孔キャリア濃度もコレクタ領域２２側からエミッタ領域３６側に向かって低くなっていることが分かる。
従来構造の図示１１の場合では、ボディ領域２８とドリフト領域２６の接合界面に高濃度半導体領域（４０ａに相当する）が形成されているために、この接合界面の正孔キャリア濃度が図示１０に比して高くなっている。しかしながら、ボディ領域２８内の正孔キャリア濃度は低い状態で連続していることが分かる。このことから、従来構造では、ボディ領域２８とドリフト領域２６の接合界面に形成された高濃度半導体領域（４０ａに相当する）によるポテンシャル障壁を超えてボディ領域２８内に流入した正孔キャリアは、すぐにエミッタ電極へと排出されてしまう。また、従来構造の場合でも、ドリフト領域２６内の正孔キャリア濃度はコレクタ領域２２側からエミッタ領域３６側へ向かって低くなっている。
一方、図示１２の第７実施例の半導体装置８の場合を見てみると、ボディ領域２８内の正孔キャリア濃度が高い状態で連続していることが分かる。また、ドリフト領域２６内において、コレクタ領域Ｃ側からエミッタ領域Ｅ側へ向かって減少する正孔キャリア濃度の減少幅が、従来構造に比して緩和されている。したがって、エミッタ・コレクタ電極間に亘って正孔キャリア濃度が高くなっている。このことから、従来構造などに比して半導体装置８のオン電圧は低減されている。 First, looking at the case where the first floating semiconductor region 40b and the high-concentration semiconductor region 40a shown in FIG. 10 are not formed, the hole carrier concentration decreases most at the pn junction interface between the body region 28 and the drift region 26. It can be seen that the hole carrier concentration in the body region 28 is continuous in a low state. In addition, it can be seen that the hole carrier concentration in the drift region 26 also decreases from the collector region 22 side toward the emitter region 36 side.
In the case of FIG. 11 of the conventional structure, since a high concentration semiconductor region (corresponding to 40a) is formed at the junction interface between the body region 28 and the drift region 26, the hole carrier concentration at this junction interface is as shown in FIG. It is higher than that. However, it can be seen that the hole carrier concentration in the body region 28 is continuous in a low state. From this, in the conventional structure, the hole carriers that have flowed into the body region 28 beyond the potential barrier due to the high-concentration semiconductor region (corresponding to 40a) formed at the junction interface between the body region 28 and the drift region 26 are Immediately discharged to the emitter electrode. Even in the conventional structure, the hole carrier concentration in the drift region 26 decreases from the collector region 22 side toward the emitter region 36 side.
On the other hand, looking at the semiconductor device 8 of the seventh embodiment shown in FIG. 12, it can be seen that the hole carrier concentration in the body region 28 is continuous in a high state. Further, in the drift region 26, the decreasing range of the hole carrier concentration that decreases from the collector region C side to the emitter region E side is moderated as compared with the conventional structure. Therefore, the hole carrier concentration is high between the emitter and collector electrodes. For this reason, the on-voltage of the semiconductor device 8 is reduced as compared with the conventional structure.

第７実施例の半導体装置８をターンオフすると、高濃度半導体領域４０ａと第１フローティング半導体領域４０ｂのそれぞれからボディ領域２８へ空乏層が広がる。高濃度半導体領域４０ａのみを備える半導体装置（従来構造に相当する）と比較すると、ボディ領域２８内の広い領域を空乏化することができる。したがって、従来構造に比して耐圧を向上し得る。また、従来構造では、正孔キャリアの蓄積効果をさらに向上しようと、高濃度半導体領域４０ａに相当する領域の不純物濃度を増加させると、その領域とボディ領域のｐｎ接合界面で電界を保持できなくなり、耐圧特性が劣化してしまうという問題があった。第１実施例の半導体装置１では、不純物濃度を高くする必要がない。したがって電界が集中することがない。
また、このターンオフのときの空乏化に伴い、正孔キャリアは短い時間でエミッタ電極へ排出される。従来構造に比してターンオフ時間が短くなりスイッチング速度が速くなる。 When the semiconductor device 8 of the seventh embodiment is turned off, a depletion layer spreads from the high concentration semiconductor region 40 a and the first floating semiconductor region 40 b to the body region 28. Compared to a semiconductor device (corresponding to a conventional structure) having only the high-concentration semiconductor region 40a, a wide region in the body region 28 can be depleted. Therefore, the breakdown voltage can be improved as compared with the conventional structure. In the conventional structure, if the impurity concentration in the region corresponding to the high-concentration semiconductor region 40a is increased to further improve the hole carrier accumulation effect, the electric field cannot be maintained at the pn junction interface between the region and the body region. There was a problem that the breakdown voltage characteristics deteriorated. In the semiconductor device 1 of the first embodiment, it is not necessary to increase the impurity concentration. Therefore, the electric field does not concentrate.
Further, with the depletion at the time of turn-off, hole carriers are discharged to the emitter electrode in a short time. Compared with the conventional structure, the turn-off time is shortened and the switching speed is increased.

以下、第７実施例の半導体装置８を基本構造とした変形例を、図面を参照して説明する。
(第８実施例) 図１１に示す第８実施例の半導体装置９は、第７実施例の半導体装置８と比して、高濃度半導体領域４０ａと第１フローティング半導体領域４０ｂのみならず、ボディ領域２８内にさらに第３フローティング半導体領域４０ｃが付加されている。
第３フローティング半導体領域４０ｃが付加されると、さらにボディ領域２８内の正孔キャリア濃度を高くすることができ、オン電圧がさらに低減される。また、第３フローティング半導体領域４０ｃは、半導体装置９がターンオフするときのボディ領域２８の空乏化にも効果があり、耐圧の向上やターンオフ時間の短縮に効果を奏する。 Hereinafter, a modified example in which the semiconductor device 8 of the seventh embodiment has a basic structure will be described with reference to the drawings.
(Eighth Embodiment) The semiconductor device 9 of the eighth embodiment shown in FIG. 11 has not only the high-concentration semiconductor region 40a and the first floating semiconductor region 40b but also the body as compared with the semiconductor device 8 of the seventh embodiment. A third floating semiconductor region 40 c is further added in the region 28.
When the third floating semiconductor region 40c is added, the hole carrier concentration in the body region 28 can be further increased, and the on-voltage is further reduced. The third floating semiconductor region 40c is also effective in depleting the body region 28 when the semiconductor device 9 is turned off, and is effective in improving the breakdown voltage and shortening the turn-off time.

(第９実施例) 図１２に示す第９実施例の半導体装置１０は、高濃度半導体領域４１ａと各フローティング半導体領域（４１ｂ、４１ｃ）がトレンチゲート電極３２と接していない。
この場合でも、ボディ領域２８内の正孔キャリア濃度を高くする効果を奏する。少なくともボディコンタクト領域３４とボディ領域２８の接合界面近傍（４１ｂ）と、ボディ領域２８とドリフト領域２６の接合界面近傍（４１ａ）に、部分的に半導体領域が形成されていればよい。第３フローティング半導体領域４１ｃはボディ領域２８内において、空間的に分散配置されていればよい。 Ninth Embodiment In the semiconductor device 10 of the ninth embodiment shown in FIG. 12, the high-concentration semiconductor region 41a and each floating semiconductor region (41b, 41c) are not in contact with the trench gate electrode 32.
Even in this case, the effect of increasing the hole carrier concentration in the body region 28 is exhibited. A semiconductor region may be partially formed at least near the junction interface (41b) between the body contact region 34 and the body region 28 and near the junction interface (41a) between the body region 28 and the drift region 26. The third floating semiconductor regions 41 c only need to be spatially dispersed in the body region 28.

(第１０実施例) 図１３に示す第１０実施例の半導体装置１１は、ドリフト領域２６に所謂スーパージャンクション構造が形成された場合である。このスーパージャンクション構造は、ｎ型不純物を含有するｎ型コラム２５と、ｐ型不純物を含有するｐ型コラムがエミッタ・コレクタ電極間方向に伸びており、エミッタ・コレクタ電極間方向に直交する面内で、ｎ型コラム２５とｐ型コラムの互層が交互に繰返されている。半導体装置４のｎ型コラム２５とｐ型コラム２３は薄板状であり、エミッタ・コレクタ電極間方向に直交する面で断面視したときにストライプ状に形成されている。
半導体装置１１は、半導体装置８〜１０と同様の作用効果によりボディ領域２８内の正孔キャリア濃度が高くなり、オン電圧が低減されることに加え、スーパージャンクション構造によりドリフト領域２６のオン抵抗の低減化と耐圧の向上を図ることができる。
なお、スーパージャンクション構造は、ｎ型コラム２５とｐ型コラム２３がエミッタ・コレクタ電極間方向に伸びており、エミッタ・コレクタ電極間方向に直交する面内で、ｎ型コラム２５とｐ型コラムの互層が交互に繰返されていればよい。例えばｎ型コラム２５とｐ型部分領域のそれぞれが薄板状であれば、ｎ型部分領域とｐ型部分領域は一方方向に繰返される。ｎ型コラム２５とｐ型コラム２３のそれぞれの断面が長方形の柱状であれば、各柱を千鳥格子状に配置することで各コラムが２方向に繰返されるスーパージャンクション構造が得られる。ｎ型コラム２５とｐ型コラム２３のそれぞれの断面が正六角形の柱状であれば、交互に隙間なく配置することで各コラムが３方向に繰返されるスーパージャンクション構造が得られる。あるいは、面的に広がるｎ型コラム２５のなかに、断面が長方形の柱状のｐ型コラム２３を相互に間隔をおいて２方向に繰返し配置したり、断面が正六角形のｐ型コラム２３を相互に間隔をおいて３方向に繰返し配置したりすることによっても、ｎ型コラム２５とｐ型コラム２３が電極間方向に直交する面内で交互に繰返されているスーパージャンクション構造が得られる。要は少なくとも一方方向に繰り返されていればよい。 Tenth Embodiment A semiconductor device 11 according to a tenth embodiment shown in FIG. 13 is a case where a so-called super junction structure is formed in the drift region 26. In this super junction structure, an n-type column 25 containing an n-type impurity and a p-type column containing a p-type impurity extend in the direction between the emitter and collector electrodes, and are in a plane perpendicular to the direction between the emitter and collector electrodes. Thus, alternating layers of the n-type column 25 and the p-type column are alternately repeated. The n-type column 25 and the p-type column 23 of the semiconductor device 4 have a thin plate shape, and are formed in a stripe shape when viewed in a cross section in a plane orthogonal to the direction between the emitter and collector electrodes.
In the semiconductor device 11, the hole carrier concentration in the body region 28 is increased due to the same effect as the semiconductor devices 8 to 10, the on-voltage is reduced, and the on-resistance of the drift region 26 is reduced by the super junction structure. Reduction and improvement in breakdown voltage can be achieved.
In the super junction structure, the n-type column 25 and the p-type column 23 extend in the direction between the emitter and collector electrodes, and the n-type column 25 and the p-type column are within the plane orthogonal to the direction between the emitter and collector electrodes. It suffices if the alternate layers are repeated alternately. For example, if each of the n-type column 25 and the p-type partial region is a thin plate, the n-type partial region and the p-type partial region are repeated in one direction. If the cross sections of the n-type column 25 and the p-type column 23 are rectangular columns, a super junction structure in which each column is repeated in two directions can be obtained by arranging the columns in a staggered pattern. If the cross section of each of the n-type column 25 and the p-type column 23 is a regular hexagonal column, a super junction structure in which each column is repeated in three directions can be obtained by arranging them alternately without a gap. Alternatively, columnar p-type columns 23 having a rectangular cross section are arranged in two directions at intervals from each other in an n-type column 25 spreading in a plane, or p-type columns 23 having a regular hexagonal cross section are mutually arranged. By repeating the arrangement in three directions at intervals, a super junction structure in which the n-type column 25 and the p-type column 23 are alternately repeated in a plane orthogonal to the interelectrode direction can be obtained. In short, it only needs to be repeated in at least one direction.

(第１１実施例) 図１４に示す第１１実施例の半導体装置１２は、スーパージャンクション構造を有する第１０実施例の変形例の一つであり、ドリフト領域２６内においてｐ−型のｐ型フローティング領域２７が空間的に分散配置されている。
ドリフト領域２６のスーパージャンクション構造は、第１０実施例のように、エミッタ・コレクタ電極間方向に直交する面内でｎ型コラム２５とｐ型コラム２６が交互に繰返される他に、第１１実施例のようにｐ型フローティング領域２７が空間的に分散配置されていてもよい。 Eleventh Embodiment A semiconductor device 12 of the eleventh embodiment shown in FIG. 14 is one of the modifications of the tenth embodiment having a super junction structure, and is a p − type p type floating in the drift region 26. Regions 27 are spatially distributed.
The super junction structure of the drift region 26 is different from the eleventh embodiment except that the n-type column 25 and the p-type column 26 are alternately repeated in a plane orthogonal to the emitter-collector electrode direction as in the tenth embodiment. As described above, the p-type floating regions 27 may be spatially distributed.

(第１２実施例) 図１５に示す第１２実施例の半導体装置１３は、ドリフト領域が備えられていない構成である。半導体領域の全領域がボディ領域１２８に相当する。このボディ領域１２８内に、エミッタ・コレクタ電極間を遮るように複数のフローティング半導体領域１４３が形成されている。エミッタ電極Ｅ側からコレクタ電極Ｃ側までトレンチゲート電極１３２が形成されている。
この半導体装置１３のオン状態では、トレンチゲート電極１３２に沿って形成される反転層を経由して、エミッタ領域１３６から電子キャリアがバッファ領域１２４へ注入される。一方、コレクタ領域１２２から注入された正孔キャリアは、ボディ領域１２８を経由してエミッタ電極へと向かうが、各フローティング半導体領域１４３の正孔キャリアの蓄積効果によって、ボディ領域１２８内の正孔キャリア濃度は高くなる。したがってオン電圧は低い。
また、この半導体装置１３がターンオフすると、各フローティング半導体領域１４３とボディ領域１２８のｐｎ接合界面から空乏層が広がるために、ボディ領域１２８の広い範囲が空乏化される。耐圧は高い。また、この空乏化によってボディ領域１２８に蓄積していた正孔キャリアは素早くエミッタ電極へと排出されるためにターンオフ時間は短い。 Twelfth Embodiment A semiconductor device 13 according to a twelfth embodiment shown in FIG. 15 has a configuration in which no drift region is provided. The entire semiconductor region corresponds to the body region 128. A plurality of floating semiconductor regions 143 are formed in the body region 128 so as to block between the emitter and collector electrodes. A trench gate electrode 132 is formed from the emitter electrode E side to the collector electrode C side.
In the on state of the semiconductor device 13, electron carriers are injected from the emitter region 136 into the buffer region 124 via an inversion layer formed along the trench gate electrode 132. On the other hand, the hole carriers injected from the collector region 122 go to the emitter electrode via the body region 128, but the hole carriers in the body region 128 are accumulated by the effect of hole carrier accumulation in each floating semiconductor region 143. The concentration becomes higher. Therefore, the on-voltage is low.
Further, when the semiconductor device 13 is turned off, a depletion layer spreads from the pn junction interface between each floating semiconductor region 143 and the body region 128, so that a wide range of the body region 128 is depleted. The pressure resistance is high. Further, since the hole carriers accumulated in the body region 128 due to the depletion are quickly discharged to the emitter electrode, the turn-off time is short.

(第１３実施例) 図１６に示す第１３実施例の半導体装置１４は、ゲート電極２３２がプレーナー型である。この場合でも少なくともボディコンタクト領域２３４とボディ領域２２８の接合界面近傍（２４４ｂ）と、ボディ領域２２８とドリフト領域２２６の接合界面近傍（２４４ａ）に、部分的に半導体領域が形成されていると、ボディ領域２２８内の正孔キャリア濃度を高くすることができ、オン電圧が低減される。 Thirteenth Embodiment In the semiconductor device 14 of the thirteenth embodiment shown in FIG. 16, the gate electrode 232 is a planar type. Even in this case, if the semiconductor region is partially formed at least near the junction interface (244b) between the body contact region 234 and the body region 228 and near the junction interface (244a) between the body region 228 and the drift region 226, The hole carrier concentration in the region 228 can be increased, and the on-voltage is reduced.

以上、本発明の具体例を詳細に説明したが、これらは例示に過ぎず、特許請求の範囲を限定するものではない。特許請求の範囲に記載の技術には、以上に例示した具体例を様々に変形、変更したものが含まれる。
例えば、トレンチゲート電極がドリフト領域の下方深くまで形成されたディープトレンチタイプであってもよい。
また、以上の各実施例ではＩＧＢＴ半導体素子について記述しているが、他の素子（サイリスタ、バイポーラトランジスタ、パワーＭＯＳ）等にも同様の効果を得ることができる。
また、本明細書または図面に説明した技術要素は、単独であるいは各種の組合せによって技術的有用性を発揮するものであり、出願時請求項記載の組合せに限定されるものではない。また、本明細書または図面に例示した技術は複数目的を同時に達成し得るものであり、そのうちの一つの目的を達成すること自体で技術的有用性を持つものである。 Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
For example, a deep trench type in which the trench gate electrode is formed deeply below the drift region may be used.
Moreover, although the IGBT semiconductor element is described in each of the above embodiments, the same effect can be obtained for other elements (thyristors, bipolar transistors, power MOSs) and the like.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

第１実施例の半導体装置１の要部断面図を示す。1 is a cross-sectional view of main parts of a semiconductor device 1 of a first embodiment. 第２実施例の半導体装置２の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 2 of 2nd Example is shown. 第３実施例の半導体装置３の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 3 of 3rd Example is shown. 第３実施例の変形例の半導体装置４の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 4 of the modification of 3rd Example is shown. 第４実施例の半導体装置５の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 5 of 4th Example is shown. 第５実施例の半導体装置６の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 6 of 5th Example is shown. 第６実施例の半導体装置７の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 7 of 6th Example is shown. 第７実施例の半導体装置８の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 8 of 7th Example is shown. 第７実施例の半導体装置８の要部斜視図を示す。The principal part perspective view of the semiconductor device 8 of 7th Example is shown. エミッタ・コレクタ電極間の正孔キャリア濃度分布を示す。The hole carrier concentration distribution between the emitter and collector electrodes is shown. 第８実施例の半導体装置９の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 9 of 8th Example is shown. 第９実施例の半導体装置１０の要部断面図を示す。The principal part sectional drawing of the semiconductor device 10 of 9th Example is shown. 第１０実施例の半導体装置１１の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 11 of 10th Example is shown. 第１１実施例の半導体装置１２の要部断面図を示す。Sectional drawing of the principal part of the semiconductor device 12 of 11th Example is shown. 第１２実施例の半導体装置１３の要部断面図を示す。The principal part sectional drawing of the semiconductor device 13 of 12th Example is shown. 第１３実施例の半導体装置１４の要部断面図を示す。The principal part sectional drawing of the semiconductor device 14 of 13th Example is shown. 従来構造の半導体装置１５の要部断面図を示す。The principal part sectional drawing of the semiconductor device 15 of the conventional structure is shown.

符号の説明Explanation of symbols

２２：コレクタ領域
２４：バッファ領域
２６：ドリフト領域
２８：ボディ領域
３２：トレンチゲート電極
３３：ゲート絶縁膜
３４：ボディコンタクト領域
３６：エミッタ領域（第２導電型半導体領域）
４０：フローティング半導体領域
４０ａ：高濃度半導体領域
４０ｂ：第１フローティング半導体領域
４０ｃ：第３フローティング半導体領域 22: collector region 24: buffer region 26: drift region 28: body region 32: trench gate electrode 33: gate insulating film 34: body contact region 36: emitter region (second conductivity type semiconductor region)
40: floating semiconductor region 40a: high concentration semiconductor region 40b: first floating semiconductor region 40c: third floating semiconductor region

Claims (11)

一対の主電極と、
一方の主電極と接続する第１導電型のボディコンタクト領域と、
その一方の主電極と接続する第２導電型の第２導電型半導体領域と、
そのボディコンタクト領域と第２導電型半導体領域の少なくとも一部と接する第１導電型のボディ領域と、
そのボディ領域と接するとともに、ボディコンタクト領域と第２導電型半導体領域からボディ領域によって隔てられている第２導電型のドリフト領域と、
前記第２導電型半導体領域とドリフト領域を隔てているボディ領域にゲート絶縁膜を介して対向するゲート電極とを備えている半導体装置において、
ボディ領域とドリフト領域の接合界面よりボディ領域側に第２導電型のフローティング半導体領域及び／又は絶縁層が形成されていることを特徴とする半導体装置。 A pair of main electrodes;
A body contact region of a first conductivity type connected to one main electrode;
A second conductivity type semiconductor region of a second conductivity type connected to the one main electrode;
A first conductivity type body region in contact with the body contact region and at least a part of the second conductivity type semiconductor region;
A drift region of a second conductivity type in contact with the body region and separated from the body contact region and the second conductivity type semiconductor region by the body region;
In the semiconductor device comprising a gate electrode facing the body region separating the second conductivity type semiconductor region and the drift region through a gate insulating film,
A semiconductor device, wherein a second conductivity type floating semiconductor region and / or an insulating layer is formed on the body region side of a junction interface between a body region and a drift region. 第２導電型半導体領域の膜厚が、フローティング半導体領域及び／又は絶縁層の膜厚より小さいことを特徴とする請求項１の半導体装置。   2. The semiconductor device according to claim 1, wherein the film thickness of the second conductivity type semiconductor region is smaller than the film thickness of the floating semiconductor region and / or the insulating layer. 前記フローティング半導体領域がゲート絶縁膜に接するとともに、ボディコンタクト領域とドリフト領域を接続するボディ領域が確保されていることを特徴とする請求項２の半導体装置。   3. The semiconductor device according to claim 2, wherein the floating semiconductor region is in contact with the gate insulating film, and a body region for connecting the body contact region and the drift region is secured. 第２導電型半導体領域とボディ領域の接合界面近傍に、ボディ領域の不純物濃度よりも不純物濃度が高い第１導電型半導体領域が形成されており、その第１導電型半導体領域の一部はボディコンタクト領域と接していることを特徴とする請求項３の半導体装置。   A first conductivity type semiconductor region having an impurity concentration higher than the impurity concentration of the body region is formed in the vicinity of the junction interface between the second conductivity type semiconductor region and the body region, and a part of the first conductivity type semiconductor region is formed in the body. 4. The semiconductor device according to claim 3, wherein the semiconductor device is in contact with the contact region. 前記フローティング半導体領域及び／又は絶縁層が、ボディコンタクト領域と接することを特徴とする請求項１の半導体装置。   2. The semiconductor device according to claim 1, wherein the floating semiconductor region and / or the insulating layer is in contact with a body contact region. 前記フローティング半導体領域がゲート絶縁膜に接するとともに、ボディコンタクト領域とドリフト領域を接続するボディ領域が確保されていることを特徴とする請求項２の半導体装置。   3. The semiconductor device according to claim 2, wherein the floating semiconductor region is in contact with the gate insulating film, and a body region for connecting the body contact region and the drift region is secured. 第２導電型半導体領域とボディ領域の接合界面近傍に、ボディ領域の不純物濃度よりも不純物濃度が高い第１導電型半導体領域が形成されており、その第１導電型半導体領域の一部はボディコンタクト領域に接していることを特徴とする請求項１の半導体装置。   A first conductivity type semiconductor region having an impurity concentration higher than the impurity concentration of the body region is formed in the vicinity of the junction interface between the second conductivity type semiconductor region and the body region, and a part of the first conductivity type semiconductor region is formed in the body. The semiconductor device according to claim 1, wherein the semiconductor device is in contact with the contact region. 一対の主電極と、
一方の主電極と接続する第１導電型のボディコンタクト領域と、
その一方の主電極と接続する第２導電型の第２導電型半導体領域と、
そのボディコンタクト領域と第２導電型半導体領域の少なくとも一部と接する第１導電型のボディ領域と、
そのボディ領域と接するとともに、ボディコンタクト領域と第２導電型半導体領域からボディ領域によって隔てられている第２導電型のドリフト領域と、
前記第２導電型半導体領域とドリフト領域を隔てているボディ領域にゲート絶縁膜を介して対向するゲート電極とを備えている半導体装置において、
ボディコンタクト領域とボディ領域の接合界面近傍に第２導電型の第１フローティング半導体領域が形成されており、ボディ領域とドリフト領域の接合界面近傍に第２導電型の第２フローティング半導体領域が形成されていることを特徴とする半導体装置。 A pair of main electrodes;
A body contact region of a first conductivity type connected to one main electrode;
A second conductivity type semiconductor region of a second conductivity type connected to the one main electrode;
A first conductivity type body region in contact with the body contact region and at least a part of the second conductivity type semiconductor region;
A drift region of a second conductivity type in contact with the body region and separated from the body contact region and the second conductivity type semiconductor region by the body region;
In the semiconductor device comprising a gate electrode facing the body region separating the second conductivity type semiconductor region and the drift region through a gate insulating film,
A second conductivity type first floating semiconductor region is formed near the junction interface between the body contact region and the body region, and a second conductivity type second floating semiconductor region is formed near the junction interface between the body region and the drift region. A semiconductor device characterized by that. 一対の主電極と、
一方の主電極と接続する第１導電型のボディコンタクト領域と、
その一方の主電極と接続する第２導電型の第２導電型半導体領域と、
そのボディコンタクト領域と第２導電型半導体領域の少なくとも一部と接する第１導電型のボディ領域と、
そのボディ領域と接するとともに、ボディコンタクト領域と第２導電型半導体領域からボディ領域によって隔てられている第２導電型のドリフト領域と、
前記第２導電型半導体領域とドリフト領域を隔てているボディ領域にゲート絶縁膜を介して対向するゲート電極とを備えている半導体装置において、
ボディコンタクト領域とボディ領域の接合界面近傍に第２導電型の第１フローティング半導体領域が形成されており、ボディ領域とドリフト領域の接合界面近傍に、その不純物濃度がドリフト領域の不純物濃度よりも高い第２導電型の高濃度半導体領域が形成されていることを特徴とする半導体装置。 A pair of main electrodes;
A body contact region of a first conductivity type connected to one main electrode;
A second conductivity type semiconductor region of a second conductivity type connected to the one main electrode;
A first conductivity type body region in contact with the body contact region and at least a part of the second conductivity type semiconductor region;
A drift region of a second conductivity type in contact with the body region and separated from the body contact region and the second conductivity type semiconductor region by the body region;
In the semiconductor device comprising a gate electrode facing the body region separating the second conductivity type semiconductor region and the drift region through a gate insulating film,
A first conductivity type first floating semiconductor region is formed in the vicinity of the junction interface between the body contact region and the body region, and the impurity concentration is higher in the vicinity of the junction interface between the body region and the drift region than the impurity concentration in the drift region. A semiconductor device, wherein a second conductivity type high concentration semiconductor region is formed. 前記第１フローティング半導体領域の少なくとも一部と、第２フローティング半導体領域又は高濃度半導体領域の少なくとも一部が、少数キャリアの経路に位置していることを特徴とする請求項８または９の半導体装置。   10. The semiconductor device according to claim 8, wherein at least a part of the first floating semiconductor region and at least a part of the second floating semiconductor region or the high concentration semiconductor region are located in a minority carrier path. . 第１導電型のボディ領域内に複数個の第２導電型のフローティング半導体領域が分散配置されていることを特徴とする請求項８〜１０のいずれかの半導体装置。   11. The semiconductor device according to claim 8, wherein a plurality of second conductive type floating semiconductor regions are dispersedly arranged in the first conductive type body region.
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US7737491B2 (en) 2010-06-15
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JP4723816B2 (en) 2011-07-13
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US20070114598A1 (en) 2007-05-24
EP2146377B1 (en) 2012-07-25

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