JP2006179815A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that suppresses JFET phenomena and solves a tradeoff between break-down voltage and ON voltage. <P>SOLUTION: This semiconductor device contains a gate insulating film 42 formed continually from the surface of a p<SP>-</SP>-type body region 34 separating the n<SP>-</SP>-type semiconductor 12 and n<SP>+</SP>-type emitter region 32 to that of a semiconductor layer 12 positioned outside of a periphery 34a of the body region 34, and a planner gate electrode 44 opposed to the body region 34 interposing the insulating film 42 separating the semiconductor layer 12 and the emitter region 32. In addition, it contains an n<SP>+</SP>-type semiconductor region 52 formed along the periphery 34a of the body region 34 on the surface of the semiconductor layer 12 covered with the gate insulating film 42 and a p<SP>+</SP>-type semiconductor region 54 formed near the n<SP>+</SP>-type semiconductor region 52. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a planar gate electrode. In particular, the present invention relates to a technique for reducing on-voltage without impairing the breakdown voltage of a semiconductor device including a planar gate electrode.

A semiconductor device provided with a planar gate electrode is known. An IGBT (Insulated Gate Bipolar Transistor) is known as an example of this type of semiconductor device.
The IGBT includes an n ⁻ type semiconductor layer, and a p ⁻ type body region is formed on a part of the surface of the semiconductor layer. A p ⁺ type body contact region and an n ⁺ type emitter region are formed in part of the surface of the body region. Furthermore, an insulating film is formed so as to continuously extend from the surface of the body region separating the semiconductor layer and the emitter region to the surface of the semiconductor layer located outside the periphery of the body region. A planar gate electrode is formed on the surface of the insulating film covering the body region separating the semiconductor layer and the emitter region. The planar gate electrode is opposed to the body region separating the semiconductor layer and the emitter region. A portion of the insulating film located between the planar gate electrode and the body region is referred to as a gate insulating film. The insulating film includes a field oxide film and / or a LOCOS oxide film in addition to the gate insulating film. The IGBT includes a p ⁺ -type collector layer in contact with the back surface of the semiconductor layer, a collector electrode in contact with the collector layer, and an emitter electrode in contact with the body contact region and the emitter region. The semiconductor layer excluding the body region functions as a drift region.

In the IGBT, a pn junction is formed by a p ⁻ type body region and an n ⁻ type semiconductor layer (also called a drift region), and a depletion layer extends from the pn junction. In the case of the planar gate electrode structure, a depletion layer extending in the lateral direction from the pn junction in the n ⁻ type semiconductor layer is formed, so that a current path in the n ⁻ semiconductor layer below the insulating film is limited, That is, there is a problem that the JFET phenomenon occurs. In order to solve this problem, a technique is known in which an n ⁺ type semiconductor region having a higher impurity concentration than the surrounding n ⁻ type semiconductor layer is provided in the semiconductor layer below the insulating film. By providing a region having a high impurity concentration, the depletion layer can be prevented from growing. Thereby, a sufficient current path can be secured in the semiconductor layer, and the occurrence of the JFET phenomenon can be suppressed. As related publicly known techniques, the techniques of Patent Document 1 and Patent Document 2 are known.
JP 2002-110985 A JP 2001-24284 A

The inventors of the present invention not only can suppress the occurrence of the JFET phenomenon by forming a region having a high impurity concentration in the semiconductor layer, but also the holes are accumulated in the semiconductor layer due to the presence of the region. Together, the inventors have newly found that the on-voltage of the IGBT is reduced. Therefore, an attempt was made to further improve the hole accumulation effect by making the impurity concentration in the high impurity concentration region higher than that known in the prior art. However, if the impurity concentration of the high impurity concentration region is too high, the potential of the high impurity concentration region rises to the collector potential when the semiconductor device is turned off, and the collector electrode is formed at a short distance between the high impurity concentration region and the emitter region. It has been found that the breakdown voltage of the semiconductor device deteriorates because it must withstand the potential difference between the emitter electrode and the emitter electrode. On the other hand, when the impurity concentration in the region is low, the hole accumulation effect decreases.
By adjusting the impurity concentration in the high impurity concentration region provided to take measures against the JFET phenomenon by the inventors' study, the on-voltage is reduced by suppressing the occurrence of the JFET phenomenon and enhancing the effect of accumulating minority carriers. And it has been found difficult to ensure the required breakdown voltage. It was confirmed that there is a trade-off between increasing the effect of accumulating minority carriers and ensuring withstand voltage, and it is difficult to achieve both.
Note that this trade-off relationship is not limited to the IGBT, but is also common to other semiconductor devices including a planar gate electrode, such as a MOS.
In order to reduce the on-voltage while ensuring the necessary breakdown voltage, the present inventors need a technology that breaks the trade-off relationship that exists between the breakdown voltage and the minority carrier accumulation effect. He recognized and succeeded.

The semiconductor device of the present invention includes a semiconductor layer containing a first conductivity type impurity at a low concentration. A body region containing the second conductivity type impurity at a low concentration is formed on a part of the surface of the semiconductor layer. A body contact region containing a high concentration of the second conductivity type impurity and a first semiconductor region containing a high concentration of the first conductivity type impurity are formed on a part of the surface of the body region. The first semiconductor region is separated from the semiconductor layer by the body region.
An insulating film is formed on the surface of the body region that separates the semiconductor layer from the first semiconductor region. The insulating film is continuously formed up to the surface of the semiconductor layer located outside the periphery of the body region. A planar gate electrode is formed on the surface of the insulating film that covers the surface of the body region that separates the semiconductor layer from the first semiconductor region. The planar gate electrode is opposed to the body region that separates the semiconductor layer and the first semiconductor region via the insulating film.
In the semiconductor device of the present invention, the second semiconductor region containing the first conductivity type impurity at a high concentration is formed on the surface of the semiconductor layer covered with the insulating film and along the periphery of the body region. Further, a third semiconductor region containing the second conductivity type impurity at a high concentration is formed in the vicinity of the second semiconductor region.
The insulating film includes a gate insulating film, and further includes a field oxide film and / or a LOCOS oxide film. These may be formed by a plurality of insulating members, or may be formed integrally. The insulating film may be formed on the entire surface of the semiconductor layer outside the periphery of the body region, or may be formed on a part of the surface. Of the insulating film, a portion interposed between the planar gate electrode and the body region is referred to as a gate insulating film. Note that a part of the planar gate electrode may be formed to extend on the surface of the field oxide film and / or the LOCOS oxide film.

The impurity concentration of the second semiconductor region is high. Thereby, the width of the depletion layer extending from the pn junction interface between the body region and the semiconductor layer (including the pn junction interface between the body region and the second semiconductor region when the second semiconductor region is in contact with the body region) is suppressed. I can. Therefore, in the semiconductor layer below the insulating film, the phenomenon that the current path is limited by the depletion layer, that is, the occurrence of the JFET phenomenon can be suppressed. Further, since the concentration is high, the effect of accumulating minority carriers is great, and the combination of the two can reduce the on-voltage of the semiconductor device. Furthermore, when the semiconductor device is turned off, a depletion layer can be extended into the second semiconductor region from the third semiconductor region formed in the vicinity of the second semiconductor region. Therefore, even when the second semiconductor region has a high concentration, a situation in which the second semiconductor region is raised to a high potential can be avoided. The breakdown voltage of the semiconductor device is not impaired.
According to the semiconductor device of the present invention, by using the high-concentration second semiconductor region, occurrence of the JFET phenomenon can be suppressed, minority carriers can be accumulated, and the on-voltage can be reduced. On the other hand, it is possible to prevent the breakdown voltage from being damaged by using the high-concentration third semiconductor region. The trade-off relationship existing between the withstand voltage and the on-voltage can be broken, and both can be improved.

  The semiconductor device of the present invention is particularly useful in an IGBT. A semiconductor device in which the present invention is applied to an IGBT is in contact with a second conductivity type collector layer in contact with the back surface of the semiconductor layer, a collector electrode in contact with the collector layer, a body contact region, and the first semiconductor region. An emitter electrode is further provided. If necessary, a buffer layer containing a high concentration of the first conductivity type impurity may be provided between the collector layer and the semiconductor layer.

The second semiconductor regions are preferably formed at intervals along the periphery of the body region.
In this case, when the semiconductor device is turned off, minority carriers are quickly discharged from the interval between the second semiconductor regions, and a stable turn-off operation is obtained.
The second semiconductor region and the third semiconductor region are preferably in contact with each other.
In this case, when the semiconductor device is turned off, the depletion layer can be effectively extended from the third semiconductor region into the second semiconductor region, and a necessary breakdown voltage can be easily secured.

The third semiconductor region is preferably formed between the adjacent second semiconductor regions.
In this case, the combination of the second semiconductor region and the third semiconductor region is repeatedly formed along the periphery of the body region. Thereby, when the semiconductor device is turned off, a wide range of the semiconductor layer below the insulating film can be depleted. Even if the impurity concentration of the second semiconductor region is high, it is possible to avoid a situation where the breakdown voltage of the semiconductor device is impaired.

The first semiconductor regions are preferably formed at intervals along the periphery of the body region.
By forming the second semiconductor region, the minority carrier accumulation effect can be improved. On the other hand, even if the accumulated minority carriers flow into the first semiconductor region and the gate voltage is turned off, the semiconductor device There is a possibility that a phenomenon that does not turn off (latch-up phenomenon) occurs.
By forming the first semiconductor regions at intervals, a path for discharging the accumulated minority carriers to the body contact region can be secured. The minority carrier accumulation effect can be improved while suppressing the occurrence of the latch-up phenomenon.

It is preferable that the space between the first semiconductor regions formed at intervals and the third semiconductor region face each other with the body region interposed therebetween.
By arranging the positional relationship between the first semiconductor region and the third semiconductor region so as to face each other through the body region, the path through which minority carriers are discharged to the body contact region is minimized. . The minority carrier accumulation effect can be further improved while effectively suppressing the occurrence of the latch-up phenomenon.

  It is preferable that the third semiconductor region is in contact with the body region. The accumulated minority carriers can be effectively discharged not to the first semiconductor region but to the body contact region.

  The combination of the second semiconductor region and the third semiconductor region is preferably stacked in the layer thickness direction of the semiconductor layer. By forming the combination of the second semiconductor region and the third semiconductor region in various directions, the degree of freedom in designing the second semiconductor region and the third semiconductor region can be increased. Therefore, it is easy to realize an optimum state for breaking the trade-off relationship existing between the withstand voltage and the on-voltage while suppressing the occurrence of the JFET phenomenon.

  In the semiconductor device having the planar gate electrode according to the present invention, the use of the high-concentration second semiconductor region can suppress the occurrence of the JFET phenomenon and obtain the minority carrier accumulation effect, thereby reducing the on-voltage. can do. On the other hand, it is possible to prevent the breakdown voltage from being damaged by using the high-concentration third semiconductor region. The trade-off relationship existing between the withstand voltage and the on-voltage can be broken, and both can be improved.

The main features of the examples are listed.
(First Form) n ⁺ type semiconductor regions (an example of a second semiconductor region) and p ⁺ type semiconductor regions (an example of a third semiconductor region) are alternately formed along the periphery of the body region.
(Second Embodiment) A combination of an n ⁺ type semiconductor region and a p ⁺ type semiconductor region is repeatedly formed along the periphery of the body region.
Volume (Third Embodiment) ^{n +} -type semiconductor region is larger than the volume of the ^{p +} -type semiconductor region.
(Fourth Embodiment) The surface area of the n ⁺ type semiconductor region on the surface of the semiconductor layer is larger than the surface area of the p ⁺ type semiconductor region.
(Fifth Mode) The amount of impurities in the n ⁺ type semiconductor region is larger than the amount of impurities in the p ⁺ type semiconductor region.

  FIG. 1 is a perspective view of a main part of the semiconductor device 10. 2 is a longitudinal sectional view corresponding to line II-II in FIG. 1, and FIG. 3 is a longitudinal sectional view corresponding to line III-III in FIG. 2 and 3 show a unit cell (also referred to as a half cell) having a repeating structure of the semiconductor device 10. FIG. 4 is a plan view of the semiconductor device 10, but it should be noted that the semiconductor device 10 is shown with the gate insulating film 42 and the planar gate electrode 44 removed. In the embodiments described below, a semiconductor material containing silicon as a main component is used. However, similar effects can be obtained when other semiconductor materials are used.

The semiconductor device 10 includes an n ⁻ type semiconductor layer 12. As will be described later, the n ⁻ type semiconductor layer 12 is locally implanted with impurities, and the entire region is not maintained in the n ⁻ type. ^{-Maintained in a} mold.
A p ⁻ type body region 34 is formed on a part of the surface of the semiconductor layer 12. A p ⁺ -type body contact region 36 is formed on a part of the surface of the body region 34. An n ⁺ -type emitter region 32 (an example of a first semiconductor region) is formed on a part of the surface of the body region 34 (a position different from the p ⁺ -type body contact region 36). The n ⁺ -type emitter region 32 is separated from the drift region 26 surrounding the body region 34 by the body region 34. As shown in FIGS. 1 and 4, the emitter region 32 is formed along the peripheral edge 34 a of the body region 34 with an interval in the Y-axis direction. Here, the peripheral edge 34 a of the body region 34 refers to a line in which the contour line of the region where the p ⁻ -type impurity of the body region 34 is diffused contacts the surface of the semiconductor layer 12. In the present embodiment, the peripheral edge 34 a of the body region 34 extends linearly in the Y-axis direction and is parallel to the repeating direction of the emitter region 32. A body contact region 36 is formed in the interval between adjacent emitter regions 32 (36a in the figure). In the present embodiment, the region 36a shown in the figure (hereinafter referred to as the body contact partial region 36a) is formed as an integral region with the body contact region 36, but the region having a different p-type impurity concentration as necessary. It can be. For example, regions with different impurity concentrations may be formed due to limitations of the manufacturing method.

A gate insulating film 42 is continuously formed in a range including the surface of the body region 34 that separates the drift region 26 and the emitter region 32 and the surface of the semiconductor layer 12 located outside the peripheral edge 34 a of the body region 34. Has been. A planar gate electrode 44 is opposed to the body region 34 separating the drift region 26 and the emitter region 32 with a gate insulating film 42 interposed therebetween. In this example, only the gate insulating film 42 is extended on the surface of the drift layer 12, but if necessary, a thicker field oxide film, LOCOS oxide film, or the like is added to the drift region 26. It may be formed on the surface.
As shown in FIG. 4, the n ⁺ -type semiconductor region which is the surface of the drift region 26 covered with the gate insulating film 44 and is spaced along the peripheral edge 34 a of the body region 34 in the Y-axis direction. 52 (an example of a second semiconductor region) is formed. Between adjacent ^{n +} -type semiconductor region 52, a combination of the ^{p +} -type (an example of the third semiconductor region) semiconductor region 54 is formed, ^{n +} -type semiconductor region 52 and ^{p +} -type semiconductor region 54 is Y It is repeatedly formed in the axial direction. The p ⁺ type semiconductor region 54 is in contact with the n ⁺ type semiconductor region 52.
As shown in FIG. 52 a in FIG. 2, the n ⁺ type semiconductor region 52 is in contact with the body region 34. As shown in FIG. 54 a of FIG. 3, the p ⁺ type semiconductor region 54 is in contact with the body region 34. As shown in FIG. 4, the body contact partial region 36 a and the p ⁺ type semiconductor region 54 formed between the emitter regions 32 face each other in the X-axis direction with the body region 34 interposed therebetween. The body contact partial region 36a and the p ⁺ type semiconductor region 54 are aligned on a straight line in the X-axis direction. It can also be said that each combination of the body contact partial region 36a and the p ⁺ type semiconductor region 54 is arranged in parallel to the Y direction.
A p ⁺ -type collector layer 22 that is in contact with the back surface of the drift layer 26 via an n ⁺ -type buffer layer 24 is formed. The collector layer 22 is in contact with the collector electrode C. Further, the emitter electrode E is in contact with the body contact region 36 and the emitter region 32. In the present embodiment, a punch-through (PT) type IGBT including the buffer layer 24 is illustrated, but a non-punch-through (NPT) type IGBT in which the buffer layer 24 is omitted may be used as necessary.
N in the present invention ^- the semiconductor layer 12 of the type, n before the ion implantation ^- it refers to type semiconductor and a layer of, n ^- the surface of the type semiconductor layer 12 of the body region 34, body contact region 36, emitter Region 32, n ⁺ type semiconductor region 52, and p ⁺ type semiconductor region 54 are formed. The remaining region 26 of the n ⁻ type semiconductor layer 12 functions as a drift region.

Next, the on operation of the semiconductor device 10 will be described.
When a positive voltage is applied to the collector electrode C and a voltage larger than the threshold is applied to the gate electrode 44 with the emitter electrode E grounded, an inversion layer is formed on the surface of the body region 34 facing the gate electrode 44. Then, the semiconductor device 10 is turned on. Electrons supplied from the emitter region 32 are injected into the drift region 26 via the inversion layer and the n ⁺ type semiconductor region 52. At this time, a depletion layer extends from the pn junction of the p ⁻ type body region 32 and the n ⁺ type semiconductor region 52 into the n ⁺ type semiconductor region 52, but the impurity concentration of the n ⁺ type semiconductor region 52 is high. The width of this depletion layer is small. Therefore, as shown in FIG. 2, electrons that move in the n ⁺ type semiconductor region 52 in the lateral direction move downward from a position that exceeds the width of the depletion layer. If the width of the depletion layer is large, the electron movement is blocked by the depletion layer and cannot move downward. Although the so-called JFET phenomenon occurs, when the n ⁺ type semiconductor region 52 is used as in this embodiment, the width of the depletion layer extending is suppressed, and the JFET phenomenon is not substantially recognized. An increase in on-resistance can be prevented.
Electrons injected into the drift region 26 are accumulated in the buffer layer 24 and reduce the contact potential difference between the collector layer 22 and the buffer layer 24. When the contact potential difference decreases, holes are injected from the collector layer 22 into the buffer layer 24 and the drift region 26. As a result, conductivity modulation occurs in the drift region 26. In this embodiment, as shown in FIG. 2, holes injected into the drift region 26, n ⁺ -type by the presence of the semiconductor region 52, the n ⁺ -type semiconductor drift layer 26 below the region 52 and the n ⁺ Accumulated in the type semiconductor region 52. Corresponding to the increase in the amount of accumulated holes, the amount of electrons supplied also increases, and conductivity modulation is further activated. Therefore, the on-voltage of the semiconductor device 10 is extremely reduced.

As shown in FIGS. 3 and 4, some of the accumulated holes are divided into a p ⁺ type semiconductor region 54 adjacent to the n ⁺ type semiconductor region 52 and a body region in contact with the p ⁺ type semiconductor region 54. 34 and the emitter electrode E through the body contact partial region 36a. As shown in FIG. 4, the emitter regions 32 are formed in a dispersed manner, and the body contact partial region 36a and the p ⁺ type semiconductor region 54 are arranged in a linearly opposed positional relationship to shorten the distance. Thus, holes are not discharged to the emitter region 32 (a latch-up phenomenon occurs when holes are discharged to the emitter region 32), and can be discharged preferentially to the p ⁺ -type semiconductor region 54. That is, the on-voltage can be reduced while suppressing the occurrence of the latch-up phenomenon.

Next, the off operation of the semiconductor device 10 will be described.
When a positive voltage is applied to the collector electrode C and a voltage lower than the threshold is applied to the gate electrode 44 with the emitter electrode E grounded, the inversion layer disappears and the semiconductor device 10 is turned off. When the semiconductor device 10 is turned off, a depletion layer extends from the pn junction of the body region 34 and the drift region 26. In addition, a depletion layer extends from the p ⁺ type semiconductor region 54 to the n ⁺ type semiconductor region 52. As a result, a depletion region is formed over the entire region of the drift region 26, the n ⁺ type semiconductor region 52 and the p ⁺ type semiconductor region 54. Therefore, the potential difference between the collector electrode C and the emitter electrode E can be maintained over a long vertical distance created by a wide depletion region. Therefore, the electric field intensity per unit distance is relaxed, and a semiconductor device with a high breakdown voltage can be obtained.
Thus, by using the n ⁺ -type semiconductor region 52, it is possible to suppress the occurrence of the JFET phenomenon, obtain the effect of minority carrier accumulation, and reduce the on-voltage. On the other hand, by using the p ⁺ type semiconductor region 54, it is possible to prevent the breakdown voltage from being damaged. The trade-off relationship existing between the withstand voltage and the on-voltage can be broken, and both can be improved.

The semiconductor device 10 has the following other features.
In the semiconductor device 10, the emitter regions 32 are formed in a dispersed manner, and further, the body contact partial region 36a and the p ⁺ type semiconductor region 54 are arranged in a linearly opposed positional relationship to shorten the distance. Thus, there is an effect of quickly discharging the accumulated holes to the emitter region 32 when the semiconductor device 10 is turned off. Therefore, the turn-off time is shortened and the turn-off loss can be reduced.
The p ⁺ type semiconductor region 54 may be in a floating state that is not in electrical contact with the body region 34.
The impurity concentration of the n ⁺ -type semiconductor region 52 is not particularly limited, but is preferably a concentration that does not substantially cause the JFET phenomenon. Whether or not the JFET phenomenon substantially occurs depends on not only the impurity concentration but also the volume of the n ⁺ type semiconductor region 52, the impurity concentration of the body region 34, the impurity concentration of the p ⁺ type semiconductor region 54, and the n ⁺ type semiconductor region. Since it is determined by various factors such as a volume ratio between the 52 and the p ⁺ type semiconductor region 54, it is difficult to uniformly determine a suitable impurity concentration range. It is preferable to set appropriately corresponding to the semiconductor device to be formed.
The n ⁺ type semiconductor region 52 and the p ⁺ type semiconductor region 54 may be charge-balanced in order to be fully depleted, but may be formed in an unbalanced state as necessary. In short, it is sufficient that depletion proceeds to such an extent that the potential of the n ⁺ -type semiconductor region 52 does not rise to the collector potential when the semiconductor device 10 is off.
The volume of the n ⁺ type semiconductor region 52 is preferably larger than the volume of the p ⁺ type semiconductor region 54. The hole accumulation effect can be improved. Even when the volume of the p ⁺ type semiconductor region 54 is small, a sufficient hole discharge path can be secured.
The impurity amount of the n ⁺ type semiconductor region 52 is preferably larger than the impurity amount of the p ⁺ type semiconductor region 54. In this case, the hole accumulation effect can be improved.

Moreover, it is good also as a modification shown in FIG.
The semiconductor device 100 of this modification is an example in which n ⁺ type semiconductor regions 152 and 158 and p ⁺ type semiconductor regions 154 and 156 are stacked in the layer thickness direction of the drift region 112. In the semiconductor device 100, the n ⁺ type semiconductor regions 152 and 158 and the p ⁺ type semiconductor regions 154 and 156 are stacked in a staggered pattern when viewed in cross section, and different conductivity types are provided in both the horizontal direction and the vertical direction. It is formed alternately.
In this manner, combinations of the n ⁺ type semiconductor regions 152 and 158 and the p ⁺ type semiconductor regions 154 and 156 are formed not only in the direction parallel to the surface of the drift region 112 but also in various directions such as the layer thickness direction. By doing so, the design freedom of the n ⁺ type semiconductor regions 152 and 158 and the p ⁺ type semiconductor regions 154 and 156 can be increased. In the surface portion of the semiconductor layer 112 below the gate insulating film 142, it becomes easy to form an optimum state for realizing accumulation of holes, discharge of holes, suppression of JFET phenomenon, promotion of depletion, and the like.

Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above.
The technical elements described in this specification or the drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in this specification or the drawings can achieve a plurality of objects at the same time, and has technical usefulness by achieving one of the objects.

The principal part perspective view of the semiconductor device of an Example is shown. The longitudinal cross-sectional view corresponding to the II-II line of FIG. 1 is shown. The longitudinal cross-sectional view corresponding to the III-III line of FIG. 1 is shown. The principal part top view of the semiconductor device of an Example is shown. The principal part perspective view of the semiconductor device of a modification is shown.

Explanation of symbols

12: Semiconductor layer 22: Collector layer 24: Buffer layer 26: Drift region 32: Emitter region 34: Body region 36: Body contact region 36a: Body contact partial region 42: Gate insulating film 44: Planar gate electrode 52: n ⁺ type Semiconductor region 54: p ⁺ type semiconductor region

Claims (9)

A semiconductor layer containing a first conductivity type impurity in a low concentration;
A body region formed on a part of the surface of the semiconductor layer and containing a second conductivity type impurity at a low concentration;
A body contact region formed on a part of the surface of the body region and containing a second conductivity type impurity in a high concentration;
A first semiconductor region formed on a part of a surface of the body region, separated from the semiconductor layer by the body region, and containing a first conductivity type impurity in a high concentration;
An insulating film continuously formed from the surface of the body region separating the semiconductor layer and the first semiconductor region to the surface of the semiconductor layer located outside the periphery of the body region;
A planar gate electrode facing the body region separating the semiconductor layer and the first semiconductor region through the insulating film;
A second semiconductor region formed on the surface of the semiconductor layer covered with the insulating film and at a position along the periphery of the body region, and containing a high concentration of first conductivity type impurities;
A third semiconductor region formed in the vicinity of the second semiconductor region and containing a second conductivity type impurity in a high concentration;
A semiconductor device comprising: A collector layer of a second conductivity type in contact with the back surface of the semiconductor layer;
A collector electrode in contact with the collector layer;
The semiconductor device according to claim 1, further comprising an emitter electrode in contact with the body contact region and the first semiconductor region.   3. The semiconductor device according to claim 1, wherein the second semiconductor region is formed at intervals along a peripheral edge of the body region.   The semiconductor device according to claim 1, wherein the second semiconductor region and the third semiconductor region are in contact with each other.   5. The semiconductor device according to claim 3, wherein the third semiconductor region is formed between adjacent second semiconductor regions.   The semiconductor device according to claim 1, wherein the first semiconductor region is formed at intervals along a peripheral edge of the body region.   7. The semiconductor device according to claim 6, wherein the interval between the first semiconductor regions and the third semiconductor region are opposed to each other through the body region.   The semiconductor device according to claim 3, wherein the third semiconductor region is in contact with the body region.   The semiconductor device according to claim 1, wherein a combination of the second semiconductor region and the third semiconductor region is stacked in a layer thickness direction of the semiconductor layer.

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