US20100117117A1 - Vertical IGBT Device - Google Patents
Vertical IGBT Device Download PDFInfo
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- US20100117117A1 US20100117117A1 US12/267,793 US26779308A US2010117117A1 US 20100117117 A1 US20100117117 A1 US 20100117117A1 US 26779308 A US26779308 A US 26779308A US 2010117117 A1 US2010117117 A1 US 2010117117A1
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- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 claims description 10
- 230000001678 irradiating effect Effects 0.000 claims description 7
- 229910021332 silicide Inorganic materials 0.000 claims description 6
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- 229910052763 palladium Inorganic materials 0.000 claims description 5
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- 238000000137 annealing Methods 0.000 claims description 4
- 238000004519 manufacturing process Methods 0.000 claims 2
- 238000010438 heat treatment Methods 0.000 claims 1
- 238000009792 diffusion process Methods 0.000 description 12
- 239000012212 insulator Substances 0.000 description 7
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 4
- 229910052710 silicon Inorganic materials 0.000 description 4
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- 230000015572 biosynthetic process Effects 0.000 description 3
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- 230000000903 blocking effect Effects 0.000 description 2
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66325—Bipolar junction transistors [BJT] controlled by field-effect, e.g. insulated gate bipolar transistors [IGBT]
- H01L29/66333—Vertical insulated gate bipolar transistors
- H01L29/66348—Vertical insulated gate bipolar transistors with a recessed gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/30—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
- H01L29/32—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7395—Vertical transistors, e.g. vertical IGBT
- H01L29/7396—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions
- H01L29/7397—Vertical transistors, e.g. vertical IGBT with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
Definitions
- Insulated-Gate Bipolar Transistors are three-terminal power semiconductor devices that combine the gate-drive characteristics of a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with the high-current and low-saturation-voltage capability of a bipolar transistor.
- MOSFET Metal Oxide Semiconductor Field-Effect Transistor
- Modern IGBT devices are formed by integrating an FET and a bipolar power transistor on the same silicon die. The FET functions as a control input while the bipolar power transistor is used as a switch.
- IGBTs efficiently switch electric power in many applications such as electric motors, variable speed refrigerators, air-conditioners, etc. However, these applications have considerably high inductive loads which cause the current to flow in the reverse direction of the switch. If this reverse current is commutated into the IGBT, the device will be destroyed. Therefore diodes are connected anti-parallel to conduct the current and thereby protect the IGBT.
- One technique to enable the IGBT to conduct the reverse current is to integrate a freewheeling diode into the IGBT device.
- the collector electrode of the IGBT is divided into different regions of n and p-type material.
- the p-type regions form the IGBT collector.
- the n-type regions in conjunction with the n-type drift zone of the IGBT device, form a freewheeling diode with the p-body and a heavily doped p-type emitter contact region of the IGBT device.
- Integrating a freewheeling diode with an IGBT device can create some problematic conditions. Mainly, power continues to dissipate in a freewheeling diode in conduction mode even after the diode has been reverse biased. Current will continue to flow until the diode reaches a steady-state reverse bias condition. The condition when the diode changes from forward conduction to blocking is commonly referred to as Reverse Recovery.
- the Reverse Recovery Charge (RRC) causes the integrated freewheeling diode to incur electrical losses. These electrical losses increase when the diode is integrated in the IGBT.
- Diode RRC can be lowered by reducing the concentration of free-charge carriers within the IGBT device in diode mode.
- Most free-charge carriers originate within the IGBT device from the highly doped emitter contact region of the device. This highly doped region injects free-charge carriers into the drift zone of the IGBT device in diode mode. Accordingly, the diode RCC can be reduced by lowering the doping concentration of the highly doped emitter contact region.
- a local reduced charge-carrier lifetime region can be formed in the drift zone of the IGBT to reduce diode RRC.
- the reduced charge-carrier lifetime typically has a very low charge carrier lifetime to sufficiently reduce the RCC of the freewheeling diode integrated with the IGBT device.
- a single reduced charge-carrier lifetime region is typically formed by irradiating either the front or back side of the wafer on which the IGBT device and freewheeling diode are fabricated. The irradiation treatment may result in two zones being formed within the single reduced charge-carrier lifetime region. One zone has a charge carrier lifetime higher than that of the second zone, but lower than that of the non-irradiated part of the IGBT drift zone.
- the single region must still have a very low charge carrier lifetime to be effective at reducing diode RRC.
- Forming a very low charge carrier lifetime region in the drift zone of an IGBT increases the V CESat (collector-to-emitter saturation voltage) of the IGBT and also leakage current during blocking mode.
- the circuit designer must still trade-off between high emitter efficiency and low diode RRC. Accordingly, forming a single reduced charge-carrier lifetime region conventionally yields a stored charge that is at least three times higher than that of a single non-freewheeling diode.
- a power semiconductor device comprises a semiconductor substrate.
- a transistor gate structure is arranged in a trench formed in the semiconductor substrate.
- a body region of a first conductivity type is arranged adjacent the transistor gate structure and a first highly-doped region of a second conductivity type is arranged in an upper portion of the body region.
- a drift zone of the second conductivity type is arranged below the body region and a second highly-doped region of the second conductivity type is arranged below the drift zone.
- An end-of-range irradiation region is arranged adjacent the transistor gate structure and has a plurality of vacancies. In some embodiment, at least some of the vacancies are occupied by metals.
- FIG. 1 is a cross-sectional view of an embodiment of a power semiconductor device including an end-of-range irradiation region arranged between adjacent transistor gate trench structures in a body region of the device.
- FIG. 2 is a cross-sectional view of another embodiment of a power semiconductor device including an end-of-range irradiation region arranged between adjacent transistor gate trench structures below a body region of the device.
- FIGS. 3A and 3B are cross-sectional views of different embodiments of a power semiconductor device during formation of an end-of-range irradiation region arranged between adjacent transistor gate trench structures.
- FIG. 4 is a cross-sectional view of another embodiment of a power semiconductor device during formation of an end-of-range irradiation region arranged between adjacent transistor gate trench structures.
- FIG. 5 is a cross-sectional view of yet another embodiment of a power semiconductor device during formation of an end-of-range irradiation region arranged between adjacent transistor gate trench structures.
- FIGS. 6A-6D are cross-sectional views of an embodiment of a semiconductor substrate during different stages of a metal diffusion process.
- FIGS. 7A-7D are cross-sectional views of an embodiment of a semiconductor substrate during different stages of another metal diffusion process.
- FIG. 8 is a cross-sectional view of an embodiment of several power semiconductor devices fabricated on the same substrate.
- FIG. 9 is a cross-sectional view of another embodiment of several power semiconductor devices fabricated on the same substrate.
- FIG. 10 is a cross-sectional view of yet another embodiment of several power semiconductor devices fabricated on the same substrate.
- FIG. 1 illustrates an embodiment of a power semiconductor device 100 including an Insulated-Gate Bipolar Transistor (IGBT) integrated with a freewheeling diode, together referred to herein as a reverse conducting IGBT (RC-IGBT).
- IGBT Insulated-Gate Bipolar Transistor
- RC-IGBT reverse conducting IGBT
- the IGBT has a transistor gate structure 102 arranged in trenches 104 formed in a semiconductor substrate 106 .
- the transistor gate structure 102 includes a gate conductor 108 insulated from a body region 110 of the substrate 106 by a gate insulator 112 disposed on the inner walls of the trench 104 .
- the body region 110 is of a first conductivity type (e.g., p-type) and is arranged adjacent the transistor gate structure 102 .
- a first conductivity type e.g., p-type
- a source region 114 of a second conductivity type (e.g., n-type) is arranged in an upper portion of the body region 110 .
- a highly-doped emitter contact region 116 of the first conductivity type is arranged in the body region 110 between the source regions 114 and is in contact with an emitter contact layer 118 .
- the emitter contact layer 118 is isolated from the gate conductor 108 by an insulating layer 120 to ensure proper operation of the IGBT.
- a drift zone 122 of the second conductivity type is arranged below the body region 110 .
- a highly-doped collector contact region 124 of the first conductivity type is arranged below the drift zone 122 , separating the drift zone 122 from a collector contact layer 126 of the IGBT.
- the freewheeling diode integrated with the IGBT has an anode at least partially formed by the body region 110 and highly-doped emitter contact region 116 of the IGBT.
- the cathode of the freewheeling diode is at least partially formed by one or more n-type regions 128 formed in the highly p-doped collector contact region 124 .
- the diode may adversely affect IGBT performance.
- the semiconductor substrate 106 is irradiated at one or more different energy levels to form an end-of-range irradiation region 130 between adjacent ones of the transistor gate structures 102 .
- the end-of-range irradiation region 130 is where the maximum decrease in charge carrier lifetime occurs.
- the end-of-range irradiation region 130 is arranged in the body region 110 of the device 100 between adjacent ones of the transistor gate structures 102 as shown in FIG. 1 .
- FIG. 2 illustrates another embodiment of the power semiconductor device 100 where the end-of-range irradiation region 130 is arranged below the body region 110 between adjacent ones of the transistor gate structures 102 .
- the irradiation treatment employed creates a plurality of vacancies in the end-of-range irradiation region 130 denoted by label ‘X’ in the Figures.
- At least some of the vacancies in the end-of-range irradiation region 130 are occupied by metals to improve the effectiveness of the end-of-range region 130 as will be described in more detail later.
- Various embodiments are described herein for forming the end-of-range irradiation region 130 between adjacent ones of the transistor gate structures 102 .
- FIG. 3A illustrates one embodiment of forming the end-of-range irradiation region 130 by irradiating the semiconductor substrate 106 where arrows denote the irradiation treatment. Irradiation is performed before the emitter contact layer 118 is formed, e.g., using protons or helium.
- an opening 300 is formed in the insulating layer 120 that protects the IGBT transistor gate structure 102 .
- the opening 300 is formed in a region of the insulating layer 120 arranged over the body region 110 .
- the gate insulator 112 remains protected by the insulating layer 120 during the irradiation treatment.
- the opening 300 is subsequently used to form a contact between the emitter contact layer 118 and the highly-doped emitter contact region 116 .
- the substrate 106 Prior to forming the emitter contact layer 118 , the substrate 106 is irradiated through the opening 300 formed in the insulating layer 120 . In one embodiment, irradiation is performed at a relatively low energy level, e.g. proton irradiation at approximately 180 keV. Under these conditions, the end-of-range region 130 extends from the body region 110 into the insulating layer 120 as shown in FIG. 3A .
- the irradiation is performed at a relatively high energy level of approximately 435 keV (e.g., proton irradiation), causing the end-of-range region to be formed below the body region 110 in the drift zone 122 as illustrated in FIG. 3B .
- the end-of-range region 130 is arranged between adjacent ones of the transistor gate structures 102 .
- FIG. 4 illustrates another embodiment of irradiating the semiconductor substrate 106 to form the end-of-range irradiation region 130 where the arrows denote the irradiation treatment.
- the opening 300 formed in the insulating layer 120 is used as a mask.
- a thick resist layer 400 is formed on the insulating layer 120 .
- the optional layer 400 can be used when the end-of-range defects are generated by irradiation. Layer 400 prevents protons or Helium from damaging the gate insulator 112 .
- This embodiment enables the use of a higher irradiation energy without changing the depth of the end-of-range irradiation region 130 . In both the high and low irradiation energy cases (e.g., FIGS.
- the resulting end-of-range irradiation region 130 is where the freewheeling diode resides within the RC-IGBT.
- the end-of-range irradiation region 130 is formed in the body region 110 of the device 100 as shown in FIG. 4 when a relatively high irradiation energy level is used, where the irradiation energy level depends on the thickness of layer 400 .
- the end-of-range irradiation region 130 can be formed below the body region 110 in the drift zone 122 as shown in FIG. 2 by using a relatively high irradiation energy level, e.g., approximately 435 keV.
- FIG. 5 illustrates yet another embodiment of irradiating the semiconductor substrate 106 to form the end-of-range irradiation region 130 where the arrows denote the irradiation treatment.
- an opening 500 is formed in the optional resist layer 400 .
- the opening 500 is formed in the resist layer 400 in a region of the opening 300 formed in the insulating layer 120 .
- the gate insulator 112 is masked by both the resist layer 400 and insulating layer 120 during the irradiation treatment.
- An energy level of approximately 435 keV can be employed when the substrate 106 is irradiated through the openings 500 , 300 formed in the resist and insulating layers 400 , 120 , respectively.
- the end-of-range irradiation region 130 is formed below the body region 110 , but still between the trenches 104 .
- At least some of the vacancies in the end-of-range irradiation region 130 can be occupied by metals to increase the effectiveness of the end-of-range irradiation region 130 .
- Metals can be diffused into the semiconductor substrate 106 before or after the semiconductor substrate 106 is irradiated, creating metal interstitials within the silicon lattice of the substrate 106 .
- metals are diffused into the substrate 106 at a temperature in the range of approximately 700° C. to 900° C. for a duration of approximately 30 to 120 minutes. The substrate 106 is then irradiated. An annealing of the substrate 106 in the range of approximately 600° C. to 800° C.
- the substrate 106 is irradiated, and then metals are diffused into the substrate 106 at a temperature in the range of approximately 600° C. to 800° C. for a duration of approximately 30 to 120 minutes. Described next are various embodiment for occupying vacancies in the end-of-range irradiation region 130 with metals.
- FIGS. 6A-6D illustrate one embodiment where metals such as platinum or palladium fill vacancies generated by an irradiation process.
- a metal silicide layer 600 is formed on the substrate 106 as shown in FIG. 6A .
- a diffusion process is then performed at a relatively low temperature, creating a substantial interstitial concentration 602 of metal atoms within the silicon lattice of the substrate 106 as shown in FIG. 6B .
- the metal silicide layer 600 is then removed and the substrate 106 irradiated at a relatively low energy level as indicated by the arrows in FIG. 6C to create end-of-range vacancies between adjacent ones of the trench structures 104 in the body region 110 .
- the diffused metals occupy the end-of-range vacancies as indicated by label ‘M’ in FIG. 6D by performing a second diffusion process step at a higher temperature.
- the metal can also be implanted before the first diffusion process is performed.
- the following steps e.g., irradiation, second diffusion
- the metal silicide layer 600 can be formed on the upper surface of the substrate instead of the lower surface.
- the end-of-range region 130 is formed in the body region 100 between the trenches 104 according to this embodiment.
- FIGS. 7A-7D illustrate another embodiment where metals such as platinum or palladium fill vacancies generated by an irradiation process.
- the metal silicide layer 600 is formed on the substrate 106 ( FIG. 7A ) and diffused at a relatively low temperature to create a substantial interstitial concentration 602 of metal atoms within the silicon lattice of the substrate 106 ( FIG. 7B ).
- the metal can also be formed on the upper surface of the substrate 106 or implanted before the first diffusion process as described above. Either way, the metal silicide layer 600 is then removed and the substrate 106 irradiated at a relatively high energy level as indicated by the arrows in FIG. 7C .
- end-of-range vacancies are created between adjacent ones of the trench structures 104 below the body region 110 instead of within the body region 110 .
- the diffused metals occupy the end-of-range vacancies as indicated by label ‘M’ in FIG. 7D by performing a second diffusion process step at a higher temperature.
- the high temperature second diffusion process anneals out damage caused to the gate insulator region of the trenches 104 during the previous high-energy irradiation treatment.
- the homogenous metal diffusion profile results in an optimum decrease of the stored charge of the integrated diode of the RC-IGBT.
- the metal diffusion profile in conjunction with the availability of end-of-range vacancies between adjacent ones of the transistor gate structures 102 , yield a significantly higher concentration of potentially electrically-active metals as opposed to simply diffusing metals into the substrate 106 without any substrate irradiation.
- the specific characteristics of the diffused metals in particular the energy levels within the band gap and the capture cross section, have a positive effect on the electrical characteristics of the RC-IGBT.
- any irradiation damage caused in the gate insulator 112 or at the border between the body region 110 and gate insulator 112 are mostly repaired when the substrate 106 is annealed at a relatively high temperature for redistributing the interstitial metal atoms into the end-of-range vacancies.
- instabilities in the threshold voltage of the IGBT during operation are significantly reduced.
- the secondary defect complexes created by conventional irradiation techniques and low temperature treatment are effectively repaired during high-temperature annealing. Hence, undesirable doping effects resulting from the irradiation processing are corrected without negatively influencing the recombination effect.
- FIG. 8 illustrates an embodiment of several of the power semiconductor devices 100 fabricated on the same substrate 106 .
- the end-of-range region irradiation regions 130 are arranged in the body regions 110 .
- the end-of-range region irradiation regions 130 may arranged below the body regions 110 between adjacent ones of the transistor gate structures 102 as shown in FIGS. 9 and 10 .
- the highly-doped collector contact region 124 formed below the drift zone 122 comprises an n-type region 800 arranged under some of the transistor gate structures 102 and a p-type region 802 arranged under the other transistor gate structures 102 .
- the end-of-range irradiation regions 130 are arranged above the n-type region 800 of the highly-doped collector contact region 124 , but not above the p-type region 802 .
- the gate conductor 108 above the n-type region 800 is connected to the gate conductor above the p-type region 802 .
- the gate conductor 108 above the n-type region 800 is not connected to the gate conductor above the p-type region 802 , but connected to the emitter contact layer 118 .
Abstract
According to one embodiment, a power semiconductor device comprises a semiconductor substrate. A transistor gate structure is arranged in a trench formed in the semiconductor substrate. A body region of a first conductivity type is arranged adjacent the transistor gate structure and a first highly-doped region of a second conductivity type is arranged in an upper portion of the body region. A drift zone of the second conductivity type is arranged below the body region and a second highly-doped region of the second conductivity type is arranged below the drift zone. An end-of-range irradiation region is arranged adjacent the transistor gate structure and has a plurality of vacancies. In some embodiments, at least some of the vacancies are occupied by metals.
Description
- Insulated-Gate Bipolar Transistors (IGBTs) are three-terminal power semiconductor devices that combine the gate-drive characteristics of a Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) with the high-current and low-saturation-voltage capability of a bipolar transistor. Modern IGBT devices are formed by integrating an FET and a bipolar power transistor on the same silicon die. The FET functions as a control input while the bipolar power transistor is used as a switch. IGBTs efficiently switch electric power in many applications such as electric motors, variable speed refrigerators, air-conditioners, etc. However, these applications have considerably high inductive loads which cause the current to flow in the reverse direction of the switch. If this reverse current is commutated into the IGBT, the device will be destroyed. Therefore diodes are connected anti-parallel to conduct the current and thereby protect the IGBT.
- One technique to enable the IGBT to conduct the reverse current is to integrate a freewheeling diode into the IGBT device. The collector electrode of the IGBT is divided into different regions of n and p-type material. The p-type regions form the IGBT collector. The n-type regions, in conjunction with the n-type drift zone of the IGBT device, form a freewheeling diode with the p-body and a heavily doped p-type emitter contact region of the IGBT device.
- Integrating a freewheeling diode with an IGBT device can create some problematic conditions. Mainly, power continues to dissipate in a freewheeling diode in conduction mode even after the diode has been reverse biased. Current will continue to flow until the diode reaches a steady-state reverse bias condition. The condition when the diode changes from forward conduction to blocking is commonly referred to as Reverse Recovery. The Reverse Recovery Charge (RRC) causes the integrated freewheeling diode to incur electrical losses. These electrical losses increase when the diode is integrated in the IGBT. Some applications cannot tolerate elevated temperature and/or power conditions. In addition, elevated temperature and power consumption reduce IGBT lifetime.
- Electrical losses caused by integrating a freewheeling diode with an IGBT device can be lowered by reducing the RRC of the diode. Diode RRC can be lowered by reducing the concentration of free-charge carriers within the IGBT device in diode mode. Most free-charge carriers originate within the IGBT device from the highly doped emitter contact region of the device. This highly doped region injects free-charge carriers into the drift zone of the IGBT device in diode mode. Accordingly, the diode RCC can be reduced by lowering the doping concentration of the highly doped emitter contact region. However, this significantly reduces the latch-up robustness of the IGBT device, which is not a practical solution for most IGBT applications because IGBT performance degrades.
- A local reduced charge-carrier lifetime region can be formed in the drift zone of the IGBT to reduce diode RRC. The reduced charge-carrier lifetime typically has a very low charge carrier lifetime to sufficiently reduce the RCC of the freewheeling diode integrated with the IGBT device. A single reduced charge-carrier lifetime region is typically formed by irradiating either the front or back side of the wafer on which the IGBT device and freewheeling diode are fabricated. The irradiation treatment may result in two zones being formed within the single reduced charge-carrier lifetime region. One zone has a charge carrier lifetime higher than that of the second zone, but lower than that of the non-irradiated part of the IGBT drift zone. However, the single region must still have a very low charge carrier lifetime to be effective at reducing diode RRC. Forming a very low charge carrier lifetime region in the drift zone of an IGBT increases the VCESat (collector-to-emitter saturation voltage) of the IGBT and also leakage current during blocking mode. Moreover, the circuit designer must still trade-off between high emitter efficiency and low diode RRC. Accordingly, forming a single reduced charge-carrier lifetime region conventionally yields a stored charge that is at least three times higher than that of a single non-freewheeling diode.
- According to one embodiment, a power semiconductor device comprises a semiconductor substrate. A transistor gate structure is arranged in a trench formed in the semiconductor substrate. A body region of a first conductivity type is arranged adjacent the transistor gate structure and a first highly-doped region of a second conductivity type is arranged in an upper portion of the body region. A drift zone of the second conductivity type is arranged below the body region and a second highly-doped region of the second conductivity type is arranged below the drift zone. An end-of-range irradiation region is arranged adjacent the transistor gate structure and has a plurality of vacancies. In some embodiment, at least some of the vacancies are occupied by metals.
- Those skilled in the art will recognize additional features and advantages upon reading the following detailed description, and upon viewing the accompanying drawings.
-
FIG. 1 is a cross-sectional view of an embodiment of a power semiconductor device including an end-of-range irradiation region arranged between adjacent transistor gate trench structures in a body region of the device. -
FIG. 2 is a cross-sectional view of another embodiment of a power semiconductor device including an end-of-range irradiation region arranged between adjacent transistor gate trench structures below a body region of the device. -
FIGS. 3A and 3B are cross-sectional views of different embodiments of a power semiconductor device during formation of an end-of-range irradiation region arranged between adjacent transistor gate trench structures. -
FIG. 4 is a cross-sectional view of another embodiment of a power semiconductor device during formation of an end-of-range irradiation region arranged between adjacent transistor gate trench structures. -
FIG. 5 is a cross-sectional view of yet another embodiment of a power semiconductor device during formation of an end-of-range irradiation region arranged between adjacent transistor gate trench structures. -
FIGS. 6A-6D are cross-sectional views of an embodiment of a semiconductor substrate during different stages of a metal diffusion process. -
FIGS. 7A-7D are cross-sectional views of an embodiment of a semiconductor substrate during different stages of another metal diffusion process. -
FIG. 8 is a cross-sectional view of an embodiment of several power semiconductor devices fabricated on the same substrate. -
FIG. 9 is a cross-sectional view of another embodiment of several power semiconductor devices fabricated on the same substrate. -
FIG. 10 is a cross-sectional view of yet another embodiment of several power semiconductor devices fabricated on the same substrate. -
FIG. 1 illustrates an embodiment of apower semiconductor device 100 including an Insulated-Gate Bipolar Transistor (IGBT) integrated with a freewheeling diode, together referred to herein as a reverse conducting IGBT (RC-IGBT). The IGBT has atransistor gate structure 102 arranged intrenches 104 formed in asemiconductor substrate 106. Thetransistor gate structure 102 includes agate conductor 108 insulated from abody region 110 of thesubstrate 106 by agate insulator 112 disposed on the inner walls of thetrench 104. Thebody region 110 is of a first conductivity type (e.g., p-type) and is arranged adjacent thetransistor gate structure 102. Asource region 114 of a second conductivity type (e.g., n-type) is arranged in an upper portion of thebody region 110. A highly-dopedemitter contact region 116 of the first conductivity type is arranged in thebody region 110 between thesource regions 114 and is in contact with anemitter contact layer 118. Theemitter contact layer 118 is isolated from thegate conductor 108 by aninsulating layer 120 to ensure proper operation of the IGBT. Adrift zone 122 of the second conductivity type is arranged below thebody region 110. A highly-dopedcollector contact region 124 of the first conductivity type is arranged below thedrift zone 122, separating thedrift zone 122 from acollector contact layer 126 of the IGBT. - The freewheeling diode integrated with the IGBT has an anode at least partially formed by the
body region 110 and highly-dopedemitter contact region 116 of the IGBT. The cathode of the freewheeling diode is at least partially formed by one or more n-type regions 128 formed in the highly p-dopedcollector contact region 124. However, unless the RRC of the freewheeling diode is reduced, the diode may adversely affect IGBT performance. To this end, thesemiconductor substrate 106 is irradiated at one or more different energy levels to form an end-of-range irradiation region 130 between adjacent ones of thetransistor gate structures 102. The end-of-range irradiation region 130 is where the maximum decrease in charge carrier lifetime occurs. - In one embodiment, the end-of-
range irradiation region 130 is arranged in thebody region 110 of thedevice 100 between adjacent ones of thetransistor gate structures 102 as shown inFIG. 1 .FIG. 2 illustrates another embodiment of thepower semiconductor device 100 where the end-of-range irradiation region 130 is arranged below thebody region 110 between adjacent ones of thetransistor gate structures 102. In either embodiment, the irradiation treatment employed creates a plurality of vacancies in the end-of-range irradiation region 130 denoted by label ‘X’ in the Figures. In some embodiment, at least some of the vacancies in the end-of-range irradiation region 130 are occupied by metals to improve the effectiveness of the end-of-range region 130 as will be described in more detail later. Various embodiments are described herein for forming the end-of-range irradiation region 130 between adjacent ones of thetransistor gate structures 102. -
FIG. 3A illustrates one embodiment of forming the end-of-range irradiation region 130 by irradiating thesemiconductor substrate 106 where arrows denote the irradiation treatment. Irradiation is performed before theemitter contact layer 118 is formed, e.g., using protons or helium. According to this embodiment, anopening 300 is formed in the insulatinglayer 120 that protects the IGBTtransistor gate structure 102. Theopening 300 is formed in a region of the insulatinglayer 120 arranged over thebody region 110. Thus, thegate insulator 112 remains protected by the insulatinglayer 120 during the irradiation treatment. Theopening 300 is subsequently used to form a contact between theemitter contact layer 118 and the highly-dopedemitter contact region 116. Prior to forming theemitter contact layer 118, thesubstrate 106 is irradiated through theopening 300 formed in the insulatinglayer 120. In one embodiment, irradiation is performed at a relatively low energy level, e.g. proton irradiation at approximately 180 keV. Under these conditions, the end-of-range region 130 extends from thebody region 110 into the insulatinglayer 120 as shown inFIG. 3A . In another embodiment, the irradiation is performed at a relatively high energy level of approximately 435 keV (e.g., proton irradiation), causing the end-of-range region to be formed below thebody region 110 in thedrift zone 122 as illustrated inFIG. 3B . In either irradiation energy embodiment, the end-of-range region 130 is arranged between adjacent ones of thetransistor gate structures 102. -
FIG. 4 illustrates another embodiment of irradiating thesemiconductor substrate 106 to form the end-of-range irradiation region 130 where the arrows denote the irradiation treatment. According to this embodiment, theopening 300 formed in the insulatinglayer 120 is used as a mask. A thick resistlayer 400 is formed on the insulatinglayer 120. Theoptional layer 400 can be used when the end-of-range defects are generated by irradiation.Layer 400 prevents protons or Helium from damaging thegate insulator 112. This embodiment enables the use of a higher irradiation energy without changing the depth of the end-of-range irradiation region 130. In both the high and low irradiation energy cases (e.g.,FIGS. 3 and 4 ), metal atoms (e.g. platinum or palladium) can be optionally integrated into the end-of-range vacancies as will be described in more detail later. The resulting end-of-range irradiation region 130 is where the freewheeling diode resides within the RC-IGBT. The end-of-range irradiation region 130 is formed in thebody region 110 of thedevice 100 as shown inFIG. 4 when a relatively high irradiation energy level is used, where the irradiation energy level depends on the thickness oflayer 400. Alternatively, the end-of-range irradiation region 130 can be formed below thebody region 110 in thedrift zone 122 as shown inFIG. 2 by using a relatively high irradiation energy level, e.g., approximately 435 keV. -
FIG. 5 illustrates yet another embodiment of irradiating thesemiconductor substrate 106 to form the end-of-range irradiation region 130 where the arrows denote the irradiation treatment. According to this embodiment, anopening 500 is formed in the optional resistlayer 400. In one embodiment, theopening 500 is formed in the resistlayer 400 in a region of theopening 300 formed in the insulatinglayer 120. This way, thegate insulator 112 is masked by both the resistlayer 400 and insulatinglayer 120 during the irradiation treatment. An energy level of approximately 435 keV can be employed when thesubstrate 106 is irradiated through theopenings layers range irradiation region 130 is formed below thebody region 110, but still between thetrenches 104. - At least some of the vacancies in the end-of-
range irradiation region 130, as indicated by label ‘X’ in the Figures, can be occupied by metals to increase the effectiveness of the end-of-range irradiation region 130. Metals can be diffused into thesemiconductor substrate 106 before or after thesemiconductor substrate 106 is irradiated, creating metal interstitials within the silicon lattice of thesubstrate 106. In one embodiment, metals are diffused into thesubstrate 106 at a temperature in the range of approximately 700° C. to 900° C. for a duration of approximately 30 to 120 minutes. Thesubstrate 106 is then irradiated. An annealing of thesubstrate 106 in the range of approximately 600° C. to 800° C. for a duration of approximately 30 to 120 minutes causes the interstitial metal atoms to systematically integrate into the end-of-range vacancies created during irradiation. The annealing also repairs defects created during irradiation, particularly in thetransistor gate structure 102 of the IGBT. In another embodiment thesubstrate 106 is irradiated, and then metals are diffused into thesubstrate 106 at a temperature in the range of approximately 600° C. to 800° C. for a duration of approximately 30 to 120 minutes. Described next are various embodiment for occupying vacancies in the end-of-range irradiation region 130 with metals. -
FIGS. 6A-6D illustrate one embodiment where metals such as platinum or palladium fill vacancies generated by an irradiation process. According to this embodiment, ametal silicide layer 600 is formed on thesubstrate 106 as shown inFIG. 6A . A diffusion process is then performed at a relatively low temperature, creating a substantialinterstitial concentration 602 of metal atoms within the silicon lattice of thesubstrate 106 as shown inFIG. 6B . Themetal silicide layer 600 is then removed and thesubstrate 106 irradiated at a relatively low energy level as indicated by the arrows inFIG. 6C to create end-of-range vacancies between adjacent ones of thetrench structures 104 in thebody region 110. The diffused metals occupy the end-of-range vacancies as indicated by label ‘M’ inFIG. 6D by performing a second diffusion process step at a higher temperature. The metal can also be implanted before the first diffusion process is performed. The following steps (e.g., irradiation, second diffusion) are the same as above. In yet another embodiment, themetal silicide layer 600 can be formed on the upper surface of the substrate instead of the lower surface. In each case, the end-of-range region 130 is formed in thebody region 100 between thetrenches 104 according to this embodiment. -
FIGS. 7A-7D illustrate another embodiment where metals such as platinum or palladium fill vacancies generated by an irradiation process. According to this embodiment, themetal silicide layer 600 is formed on the substrate 106 (FIG. 7A ) and diffused at a relatively low temperature to create a substantialinterstitial concentration 602 of metal atoms within the silicon lattice of the substrate 106 (FIG. 7B ). The metal can also be formed on the upper surface of thesubstrate 106 or implanted before the first diffusion process as described above. Either way, themetal silicide layer 600 is then removed and thesubstrate 106 irradiated at a relatively high energy level as indicated by the arrows inFIG. 7C . Accordingly, end-of-range vacancies are created between adjacent ones of thetrench structures 104 below thebody region 110 instead of within thebody region 110. The diffused metals occupy the end-of-range vacancies as indicated by label ‘M’ inFIG. 7D by performing a second diffusion process step at a higher temperature. The high temperature second diffusion process anneals out damage caused to the gate insulator region of thetrenches 104 during the previous high-energy irradiation treatment. - According to the metal diffusion embodiments described herein, the homogenous metal diffusion profile results in an optimum decrease of the stored charge of the integrated diode of the RC-IGBT. Particularly, the metal diffusion profile, in conjunction with the availability of end-of-range vacancies between adjacent ones of the
transistor gate structures 102, yield a significantly higher concentration of potentially electrically-active metals as opposed to simply diffusing metals into thesubstrate 106 without any substrate irradiation. Moreover, the specific characteristics of the diffused metals, in particular the energy levels within the band gap and the capture cross section, have a positive effect on the electrical characteristics of the RC-IGBT. - That is, any irradiation damage caused in the
gate insulator 112 or at the border between thebody region 110 andgate insulator 112 are mostly repaired when thesubstrate 106 is annealed at a relatively high temperature for redistributing the interstitial metal atoms into the end-of-range vacancies. As such, instabilities in the threshold voltage of the IGBT during operation are significantly reduced. In addition, the secondary defect complexes created by conventional irradiation techniques and low temperature treatment are effectively repaired during high-temperature annealing. Hence, undesirable doping effects resulting from the irradiation processing are corrected without negatively influencing the recombination effect. -
FIG. 8 illustrates an embodiment of several of thepower semiconductor devices 100 fabricated on thesame substrate 106. According to this embodiment, the end-of-rangeregion irradiation regions 130 are arranged in thebody regions 110. Alternatively, the end-of-rangeregion irradiation regions 130 may arranged below thebody regions 110 between adjacent ones of thetransistor gate structures 102 as shown inFIGS. 9 and 10 . In either embodiment, the highly-dopedcollector contact region 124 formed below thedrift zone 122 comprises an n-type region 800 arranged under some of thetransistor gate structures 102 and a p-type region 802 arranged under the othertransistor gate structures 102. The end-of-range irradiation regions 130 are arranged above the n-type region 800 of the highly-dopedcollector contact region 124, but not above the p-type region 802. Thegate conductor 108 above the n-type region 800 is connected to the gate conductor above the p-type region 802. Alternatively thegate conductor 108 above the n-type region 800 is not connected to the gate conductor above the p-type region 802, but connected to theemitter contact layer 118. - With the above range of variations and applications in mind, it should be understood that the present invention is not limited by the foregoing description, nor is it limited by the accompanying drawings. Instead, the present invention is limited only by the following claims and their legal equivalents.
Claims (31)
1. A method of manufacturing a reduced free-charge carrier lifetime semiconductor structure, comprising:
forming a plurality of transistor gate structures in trenches arranged in a semiconductor substrate;
forming a body region between adjacent ones of the transistor gate structures; and
forming an end-of-range irradiation region between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.
2. The method of claim 1 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises forming the end-of-range irradiation region in the body region between adjacent ones of the transistor gate structures.
3. The method of claim 1 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises forming the end-of-range irradiation region below the body region between adjacent ones of the transistor gate structures.
4. The method of claim 1 , further comprising forming an insulating layer on the semiconductor substrate before the end-of-range irradiation region is formed.
5. The method of claim 4 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises:
forming an opening in the insulating layer in a region of the insulating layer arranged over the body region; and
irradiating the semiconductor substrate through the opening formed in the insulating layer.
6. The method of claim 5 , further comprising forming a resist layer on the insulating layer before the opening is formed in the insulating layer.
7. The method of claim 6 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises irradiating the semiconductor substrate through the resist layer and the opening formed in the insulating layer.
8. The method of claim 6 , wherein forming the end-of-range irradiation region between adjacent ones of the transistor gate structures comprises:
forming an opening in the resist layer in a region of the opening formed in the insulating layer; and
irradiating the semiconductor substrate through the openings formed in the resist and insulating layers.
9. The method of claim 1 , further comprising occupying at least some of the vacancies in the end-of-range irradiation region with metals.
10. The method of claim 9 , wherein occupying at least some of the vacancies in the end-of-range irradiation region with metals comprises:
diffusing the metals into the semiconductor substrate; and
annealing the semiconductor substrate at a relatively high temperature.
11. The method of claim 10 , wherein diffusing the metals into the semiconductor substrate comprises:
forming a metal silicide layer on the semiconductor substrate or implanting metal into the semiconductor substrate; and
heating the semiconductor substrate.
12. The method of claim 11 , wherein the semiconductor substrate is heated to a temperature ranging between approximately 600° and 800° C. for a duration ranging between approximately 30 minutes and 120 minutes.
13. The method of claim 10 , wherein the metals are diffused into the semiconductor substrate before the end-of-range irradiation region is formed.
14. The method of claim 13 , wherein the metals are diffused into the semiconductor substrate before the end-of-range irradiation region is formed at a temperature ranging between approximately 700° and 900° C. for a duration ranging between approximately 30 minutes and 120 minutes.
15. A reduced free-charge carrier lifetime semiconductor structure, comprising:
a plurality of transistor gate structures arranged in trenches formed in a semiconductor substrate;
a body region arranged between adjacent ones of the transistor gate structures; and
an end-of-range irradiation region arranged between adjacent ones of the transistor gate structures, the end-of-range irradiation region having a plurality of vacancies.
16. The reduced free-charge carrier lifetime semiconductor structure of claim 15 , wherein at least some of the vacancies in the end-of-range irradiation region are occupied by metals.
17. The reduced free-charge carrier lifetime semiconductor structure of claim 16 , wherein the metals comprise palladium or platinum.
18. The reduced free-charge carrier lifetime semiconductor structure of claim 15 , wherein the end-of-range irradiation region is arranged in the body region between adjacent ones of the transistor gate structures.
19. The reduced free-charge carrier lifetime semiconductor structure of claim 15 , wherein the end-of-range irradiation region is arranged below the body region between adjacent ones of the transistor gate structures.
20. A method of manufacturing a power semiconductor device, comprising:
providing a semiconductor substrate;
forming a transistor gate structure in a trench arranged in the semiconductor substrate;
forming a body region of a first conductivity type adjacent the transistor gate structure;
forming a first highly-doped region of a second conductivity type in an upper portion of the body region;
forming a drift zone of the second conductivity type below the body region;
forming a second highly-doped region of the second conductivity type below the drift zone; and
forming an end-of-range irradiation region adjacent the transistor gate structure, the end-of-range irradiation region having a plurality of vacancies.
21. The method of claim 20 , wherein forming the end-of-range irradiation region adjacent the transistor gate structure comprises forming the end-of-range irradiation region in the body region adjacent the transistor gate structure.
22. The method of claim 20 , wherein forming the end-of-range irradiation region adjacent the transistor gate structure comprises forming the end-of-range irradiation region below the body region in the drift zone adjacent the transistor gate structure.
23. The method of claim 20 , further comprising occupying at least some of the vacancies in the end-of-range irradiation region with metals.
24. A power semiconductor device, comprising:
a semiconductor substrate;
a transistor gate structure arranged in a trench formed in the semiconductor substrate;
a body region of a first conductivity type arranged adjacent the transistor gate structure;
a first highly-doped region of a second conductivity type arranged in an upper portion of the body region;
a drift zone of the second conductivity type arranged below the body region;
a second highly-doped region of the second conductivity type arranged below the drift zone; and
an end-of-range irradiation region arranged adjacent the transistor gate structure, the end-of-range irradiation region having a plurality of vacancies.
25. The power semiconductor device of claim 24 , wherein at least some of the vacancies in the end-of-range irradiation region are occupied by metals.
26. The power semiconductor device of claim 25 , wherein the metals comprise palladium or platinum.
27. The power semiconductor device of claim 24 , wherein the end-of-range irradiation region is arranged in the body region adjacent the transistor gate structure.
28. The power semiconductor device of claim 24 , wherein the end-of-range irradiation region is arranged below the body region in the drift zone adjacent the transistor gate structure.
29. A power semiconductor device, comprising:
a semiconductor substrate;
a plurality of transistor gate structures arranged in trenches formed in the semiconductor substrate;
a body region of a first conductivity type arranged between adjacent ones of the transistor gate structures;
a first highly-doped region of a second conductivity type arranged in an upper portion of the body regions;
a drift zone of the second conductivity type arranged below the body regions;
a contact region having a first doped region of the first conductivity type arranged below the drift zone under some of the transistor gate structures and a second doped region of the second conductivity type arranged below the drift zone under the other transistor gate structures; and
an end-of-range irradiation region having a plurality of vacancies arranged between adjacent ones of the transistor gate structures disposed above the second doped region of the contact region, but not between adjacent ones of the transistor gate structures disposed above the first doped region of the contact region.
30. The power semiconductor device of claim 29 , wherein the end-of-range irradiation region is arranged in the body region adjacent the transistor gate structure.
31. The power semiconductor device of claim 29 , wherein the end-of-range irradiation region is arranged below the body region in the drift zone adjacent the transistor gate structure.
Priority Applications (2)
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US12/267,793 US20100117117A1 (en) | 2008-11-10 | 2008-11-10 | Vertical IGBT Device |
US14/228,330 US9543405B2 (en) | 2008-11-10 | 2014-03-28 | Method of manufacturing a reduced free-charge carrier lifetime semiconductor structure |
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US12/267,793 US20100117117A1 (en) | 2008-11-10 | 2008-11-10 | Vertical IGBT Device |
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US14/228,330 Active 2028-12-06 US9543405B2 (en) | 2008-11-10 | 2014-03-28 | Method of manufacturing a reduced free-charge carrier lifetime semiconductor structure |
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Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8449703B2 (en) | 2009-03-09 | 2013-05-28 | The Boeing Company | Predictable bonded rework of composite structures using tailored patches |
US8524356B1 (en) | 2009-03-09 | 2013-09-03 | The Boeing Company | Bonded patch having multiple zones of fracture toughness |
US20140306283A1 (en) * | 2013-04-16 | 2014-10-16 | Rohm Co., Ltd. | Superjunction semiconductor device and manufacturing method therefor |
US9583578B2 (en) * | 2013-01-31 | 2017-02-28 | Infineon Technologies Ag | Semiconductor device including an edge area and method of manufacturing a semiconductor device |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP6736531B2 (en) * | 2017-09-14 | 2020-08-05 | 株式会社東芝 | Semiconductor device |
CN113053991A (en) * | 2019-12-26 | 2021-06-29 | 株洲中车时代半导体有限公司 | Cell structure of reverse conducting IGBT and reverse conducting IGBT |
Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5360984A (en) * | 1991-11-29 | 1994-11-01 | Fuji Electric Co., Ltd. | IGBT with freewheeling diode |
US6404045B1 (en) * | 1996-02-01 | 2002-06-11 | International Rectifier Corporation | IGBT and free-wheeling diode combination |
US20050006796A1 (en) * | 1998-08-05 | 2005-01-13 | Memc Electronic Materials, Inc. | Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices |
US20050258493A1 (en) * | 2004-04-28 | 2005-11-24 | Mitsubishi Denki Kabushiki Kaisha | Reverse conducting semiconductor device and a fabrication method thereof |
US20060073684A1 (en) * | 2004-09-22 | 2006-04-06 | Hans-Joachim Schulze | Method for fabricating a doped zone in a semiconductor body |
US20070108468A1 (en) * | 2005-11-14 | 2007-05-17 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US20070231973A1 (en) * | 2006-03-30 | 2007-10-04 | Infineon Technologies Austria Ag | Reverse conducting IGBT with vertical carrier lifetime adjustment |
US20090283799A1 (en) * | 2008-05-13 | 2009-11-19 | Infineon Technologies Ag | Reduced Free-Charge Carrier Lifetime Device |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7485920B2 (en) * | 2000-06-14 | 2009-02-03 | International Rectifier Corporation | Process to create buried heavy metal at selected depth |
JP4723816B2 (en) * | 2003-12-24 | 2011-07-13 | 株式会社豊田中央研究所 | Semiconductor device |
DE102007036147B4 (en) * | 2007-08-02 | 2017-12-21 | Infineon Technologies Austria Ag | Method for producing a semiconductor body with a recombination zone |
EP2061084A1 (en) * | 2007-11-14 | 2009-05-20 | ABB Technology AG | Reverse-conducting insulated gate bipolar transistor and corresponding manufacturing method |
JP5763514B2 (en) * | 2011-12-13 | 2015-08-12 | トヨタ自動車株式会社 | Method for manufacturing switching element |
JP6117602B2 (en) * | 2013-04-25 | 2017-04-19 | トヨタ自動車株式会社 | Semiconductor device |
US9419080B2 (en) * | 2013-12-11 | 2016-08-16 | Infineon Technologies Ag | Semiconductor device with recombination region |
-
2008
- 2008-11-10 US US12/267,793 patent/US20100117117A1/en not_active Abandoned
-
2014
- 2014-03-28 US US14/228,330 patent/US9543405B2/en active Active
Patent Citations (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5360984A (en) * | 1991-11-29 | 1994-11-01 | Fuji Electric Co., Ltd. | IGBT with freewheeling diode |
US6404045B1 (en) * | 1996-02-01 | 2002-06-11 | International Rectifier Corporation | IGBT and free-wheeling diode combination |
US20050006796A1 (en) * | 1998-08-05 | 2005-01-13 | Memc Electronic Materials, Inc. | Process for making non-uniform minority carrier lifetime distribution in high performance silicon power devices |
US20050258493A1 (en) * | 2004-04-28 | 2005-11-24 | Mitsubishi Denki Kabushiki Kaisha | Reverse conducting semiconductor device and a fabrication method thereof |
US20060073684A1 (en) * | 2004-09-22 | 2006-04-06 | Hans-Joachim Schulze | Method for fabricating a doped zone in a semiconductor body |
US20070108468A1 (en) * | 2005-11-14 | 2007-05-17 | Mitsubishi Electric Corporation | Semiconductor device and method of manufacturing the same |
US20070231973A1 (en) * | 2006-03-30 | 2007-10-04 | Infineon Technologies Austria Ag | Reverse conducting IGBT with vertical carrier lifetime adjustment |
US20090283799A1 (en) * | 2008-05-13 | 2009-11-19 | Infineon Technologies Ag | Reduced Free-Charge Carrier Lifetime Device |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8449703B2 (en) | 2009-03-09 | 2013-05-28 | The Boeing Company | Predictable bonded rework of composite structures using tailored patches |
US8524356B1 (en) | 2009-03-09 | 2013-09-03 | The Boeing Company | Bonded patch having multiple zones of fracture toughness |
US9583578B2 (en) * | 2013-01-31 | 2017-02-28 | Infineon Technologies Ag | Semiconductor device including an edge area and method of manufacturing a semiconductor device |
US20140306283A1 (en) * | 2013-04-16 | 2014-10-16 | Rohm Co., Ltd. | Superjunction semiconductor device and manufacturing method therefor |
US9041096B2 (en) * | 2013-04-16 | 2015-05-26 | Rohm Co., Ltd. | Superjunction semiconductor device and manufacturing method therefor |
US9490359B2 (en) | 2013-04-16 | 2016-11-08 | Rohm Co., Ltd. | Superjunction semiconductor device with columnar region under base layer and manufacturing method therefor |
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US20140213022A1 (en) | 2014-07-31 |
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