JP2014063961A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device which can reduce on-state voltage.SOLUTION: A skipped semiconductor device in which a channel region 14 where an emitter region 15 is formed and a skipped region 19 where the emitter region 15 is not formed but an HS layer 20 is formed are alternately arranged on a semiconductor substrate 11 in a planar direction comprises: a first conductivity type carrier storage layer 21 which is formed between the channel region 14 and a drift layer 10 and has an impurity concentration higher than that of the drift layer 10. With this configuration, since it becomes difficult for holes to escape from the channel region 14 to an emitter electrode 23 due to the carrier storage layer 21, the on-state voltage can be reduced.

Description

  The present invention relates to a semiconductor device including an insulated gate bipolar transistor (hereinafter simply referred to as IGBT) element.

  Conventionally, for example, Patent Document 1 has proposed a semiconductor device including an IGBT element as a switching element used in an inverter or the like.

Specifically, in this semiconductor device, a channel region in which an emitter region is formed and a thinned region in which no emitter region is formed are formed on one surface of the semiconductor substrate in a surface layer portion of a semiconductor substrate constituting an N ⁻ type drift layer. They are repeatedly arranged in a predetermined arrangement order in parallel plane directions. That is, it is a thinning-type semiconductor device.

  In the thinning region, a hole stopper layer (hereinafter simply referred to as an HS layer) that divides the thinning region in the depth direction is formed. In other words, the thinning region is divided into the first region on one side of the semiconductor substrate and the second region on the bottom side by the HS layer.

  In such a semiconductor device, since the HS layer is formed in the thinning region, it is difficult to remove holes from the thinning region to the emitter electrode. For this reason, a large amount of holes can be accumulated in the drift layer, and the on-voltage can be reduced.

JP 2012-28719 A

  However, even in the semiconductor device described above, since holes are extracted from the channel region to the emitter electrode, there is a limit to reducing the on-voltage only by forming the HS layer in the thinning region.

  In view of the above points, an object of the present invention is to provide a semiconductor device capable of reducing on-voltage.

  In order to achieve the above object, according to the first aspect of the present invention, there is provided a semiconductor substrate (11) having one surface (11a) and constituting a first conductivity type drift layer (10), on one surface side of the semiconductor substrate. A plurality of channel regions (14) of the second conductivity type formed, a first conductivity type emitter region (15) formed in the surface layer portion of the channel region, and a channel region separated from the one surface side of the semiconductor substrate A plurality of thinned regions (19) of the second conductivity type formed, a thinned region formed in the thinned region, a first region (19a) on one surface side of the semiconductor substrate, and a second region (19b) on the bottom side of the thinned region. A first conductivity type HS layer (20) that is electrically separated from each other), an emitter electrode (23) electrically connected to the emitter region and the first region, and a channel region and a thinning region of the semiconductor substrate; Formed in spaced positions A thinning layer comprising a collector layer (25) of the second conductivity type and a collector electrode (26) electrically connected to the collector layer, and a thinning region in which no emitter region is formed between the channel regions. This type of semiconductor device is characterized by the following points.

  That is, the first conductivity type carrier storage layer (21) having an impurity concentration higher than that of the drift layer is formed between the channel region and the drift layer.

  According to this, the HS layer is formed in the thinned region, and the carrier storage layer having an impurity concentration higher than that of the drift layer is formed between the drift layer and the channel region. The supplied holes are difficult to escape from the channel region to the emitter electrode. Therefore, a larger amount of holes can be accumulated in the drift layer, and the on-voltage can be reduced.

  For example, as in the second aspect of the present invention, the semiconductor substrate has a second conductivity type base layer (12) formed on one side and a plurality of layers reaching the drift layer through the base layer. A trench (13) is extended in a predetermined direction, the base layer is separated into a plurality by the trench, and the separated base layer constitutes a channel region and a thinned region, and the trench has a gate insulating film ( 17) and a gate electrode (18) may be disposed on the gate insulating film.

  In this case, as in the invention described in claim 3, at least a part of the channel region in contact with the trench may be connected to the drift layer.

  Specifically, the carrier storage layer can be formed away from the side surface of the trench as in the invention described in claim 4. Further, as in the invention described in claim 5, the carrier storage layer can be formed by being separated into a plurality in the extending direction of the trench.

  According to the third to fifth aspects of the present invention, since the carrier storage layer is not in contact with the trench, it is possible to suppress the concentration of the electric field at the bottom of the trench and to improve the collector breakdown voltage.

  In addition, the code | symbol in the bracket | parenthesis of each means described in this column and the claim shows the correspondence with the specific means as described in embodiment mentioned later.

1 is a plan view of a semiconductor device according to a first embodiment of the present invention. It is sectional drawing along the II-II line | wire in FIG. It is sectional drawing which shows the structure of the minimum unit in FIG. It is sectional drawing along the IV-IV line in FIG. It is a figure which shows the relationship between an ON voltage and a collector withstand pressure | voltage. It is a plane layout of the drift layer, trench, and carrier storage layer of the minimum unit of the IGBT element in the second embodiment of the present invention. It is sectional drawing along the VII-VII line in FIG. It is the plane layout of the drift layer of the minimum unit of the IGBT element in the 3rd Embodiment of this invention, a trench, and a carrier storage layer. It is sectional drawing along the IX-IX line in FIG. It is sectional drawing along the XX line in FIG. It is the plane layout of the drift layer of the minimum unit of the IGBT element in the modification of 3rd Embodiment of this invention, a trench, and a carrier storage layer. It is sectional drawing of the semiconductor device in 4th Embodiment of this invention. It is sectional drawing of the minimum unit of the diode element in the diode area | region shown in FIG. FIG. 13 is a plan view of the semiconductor device shown in FIG. 12. It is a cross-sectional perspective view of the semiconductor device in 5th Embodiment of this invention. FIG. 16 is a plan view of the semiconductor device shown in FIG. 15.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be described with the same reference numerals.

(First embodiment)
A first embodiment of the present invention will be described. Note that the semiconductor device of this embodiment is preferably used as a power switching element used in a power supply circuit such as an inverter or a DC / DC converter.

  As shown in FIG. 1, the semiconductor device 1 includes a cell area 2, a guard ring portion 3 located on the outer periphery of the cell area 2, and a plurality of pads 4.

  The cell area 2 is a region where an IGBT element is formed as shown in FIG. 2, and is configured by reversing the structure repeatedly using the structure shown in FIG. 3 as a minimum unit.

Specifically, as shown in FIGS. 2 and 3, the IGBT element is configured using an N ⁻ type semiconductor substrate 11 that functions as the drift layer 10, and one surface 11 a of the semiconductor substrate 11. A P-type base layer 12 having a predetermined thickness is formed on the side. A plurality of trenches 13 are formed so as to penetrate the base layer 12 and reach the drift layer 10, and the base layer 12 is separated into a plurality of trenches 13. In the present embodiment, a silicon substrate is used as the semiconductor substrate 11.

  The trench 13 extends in parallel to the longitudinal direction, with one direction (the depth direction in the drawing in FIG. 2) of the surface direction of the one surface 11a of the semiconductor substrate 11 as the longitudinal direction. In the present embodiment, each trench 13 has an annular structure by having its tip portion drawn around. In the following, a case where the trench 13 has an annular structure will be described. However, the trench 13 may have a stripe structure in which the tip portion is not routed.

The base layer 12 disposed between adjacent trenches 13 (that is, the base layer 12 not surrounded by the annular trench 13) is a P-type channel region. In the surface layer portion of the channel region 14, an N ⁺ type emitter region 15 and a P ⁺ type body region 16 are formed so as to be sandwiched between the emitter regions 15.

  The emitter region 15 has a higher impurity concentration than the drift layer 10, terminates in the base layer 12, and is disposed so as to be in contact with the side surface of the trench 13. On the other hand, the body region 16 is configured with a higher impurity concentration than the channel region 14 and terminates in the base layer 12 like the emitter region 15. The body region 16 is formed deeper than the emitter region 15 with respect to the one surface 11 a of the semiconductor substrate 11.

  More specifically, the emitter region 15 extends in a rod shape so as to be in contact with the side surface of the trench 13 along the longitudinal direction of the trench 13 in the region between the trenches 13 and has a structure in which the emitter region 15 terminates inside the tip of the trench 13. Has been. The body region 16 is sandwiched between the two emitter regions 15 and extends in a rod shape along the longitudinal direction of the trench 13 (that is, the emitter region 15).

  Each trench 13 includes a gate insulating film 17 formed so as to cover the inner wall surface of each trench 13, and a gate electrode 18 formed of P-type polysilicon or the like formed on the gate insulating film 17. Embedded by. Thereby, a trench gate structure is configured.

  The gate electrode 18 is electrically connected to a gate wiring formed on the one surface 11a of the semiconductor substrate 11 in a cross section different from those in FIGS. 2 and 3, and the gate electrode 18 is shown in FIG. The pad 4 is connected to the gate pad.

  Further, the thinning region 19 is constituted by the base layer 12 surrounded by the trenches 13 forming the annular structure, that is, the base layer 12 in which the emitter region 15 is not formed.

  As described above, the base layer 12 is divided by the trench 13, and among the divided base layers 12, the channel region 14 is formed with the emitter region 15 and the emitter region 15 is not formed. Is the thinning region 19. The emitter regions 15 are alternately formed in the base layer 12 divided into a plurality of portions, so that the channel region 14 and the thinned region 19 are repeatedly arranged in a fixed arrangement order in a plane direction parallel to the one surface 11a of the semiconductor substrate 11. Has been placed. That is, in the cell area 2, IGBT cells and so-called dummy cells are alternately arranged. For this reason, it can be said that a thinned-out IGBT element is formed in the cell area 2 of the present embodiment. Here, the plane direction parallel to the one surface 11 a of the semiconductor substrate 11 is a normal direction to the side surface of the trench 13.

  In the thinned region 19 of the base layer 12, the thinned region 19 is divided into a first region 19 a on the opening side of the trench 13 and a second region 19 b on the bottom side of the trench 13 in the depth direction of the trench 13. The N-type HS layer 20 is formed, and the first region 19a and the second region 19b are completely separated in terms of potential by the HS layer 20.

  The HS layer 20 is formed only in the thinning region 19 of the base layer 12 and is not formed in the channel region 14 of the base layer 12. That is, the HS layer 20 does not exist in the IGBT cell but exists only in the dummy cell.

In addition, the HS layer 20 is on the surface layer side of the thinned region 19 (that is, on the one surface 11a side of the semiconductor substrate 11) in the depth direction of the trench 13 in order to suppress a decrease in collector breakdown voltage. It is preferably formed at a position shallower than the bottom of the provided body region 16. Although not particularly limited, the HS layer 20 of the present embodiment has an impurity concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ^−3, and has a depth of 0.5 μm from the one surface 11 a of the semiconductor substrate 11. It is formed with a thickness of 0.2 μm.

  An N-type carrier storage layer (hereinafter simply referred to as a CS layer) 21 is formed between the drift layer 10 and the channel region 14, and the drift layer 10 and the channel region 14 are electrically connected to each other by the CS layer 21. Are completely separated.

  The CS layer 21 exists only in the IGBT cell, and does not exist in the dummy cell in which the channel region 14 is not formed. That is, in the IGBT cell, it can be said that the drift layer 10, the CS layer 21, and the channel region 14 are laminated in this order.

Although not particularly limited, the CS layer 21 of the present embodiment has an impurity concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁷ cm ⁻³ and is 2 μm in depth of 3 μm from the one surface 11 a of the semiconductor substrate 11. It is formed with a thickness.

  An interlayer insulating film 22 such as BPSG is formed on the base layer 12. A contact hole 22 a is formed in the interlayer insulating film 22, and a part of the emitter region 15, the body region 16, and a part of the first region 19 a of the thinning region 19 are exposed from the interlayer insulating film 22. ing.

  An emitter electrode 23 is formed on the interlayer insulating film 22, and the emitter electrode 23 is electrically connected to the emitter region 15, the body region 16, and the first region 19a through a contact hole 22a.

  The first region 19a is connected to the emitter electrode 23 by reducing the mirror capacitance formed in the path from the collector electrode 26, which will be described later, to the gate electrode 18 through the thinning region 19, thereby reducing the switching loss. It is for aiming at.

  Further, an N-type field stop layer (hereinafter simply referred to as an FS layer) 24 is formed on the other surface 11b side of the semiconductor substrate 11 opposite to the one surface 11a. The FS layer 24 is not necessarily required, but is provided for improving the breakdown voltage and steady loss performance by preventing the depletion layer from spreading and for controlling the injection amount of holes injected from the back side of the substrate. It is.

  A P-type collector layer 25 is formed on the opposite side of the drift layer 10 across the FS layer 24, and a collector electrode 26 is formed on the collector layer 25 (the other surface 11b of the semiconductor substrate 11).

  The above is the configuration of the cell area 2 in the present embodiment. As shown in FIG. 4, the guard ring portion 3 formed around the cell area 2 includes an annular P-type well region 12 a and a plurality of P-type so as to surround the cell area 2 on the surface layer portion of the semiconductor substrate 11. The guard ring 12b is formed as a multiple ring structure.

  An oxide film 22b is provided on the guard ring 12b, and an opening is provided in a portion of the oxide film 22b corresponding to the guard ring 12b. The outer peripheral electrode 23a is electrically connected to the guard ring 12b through the opening of the oxide film 22b. Further, the outer peripheral electrode 23a is covered with a passivation film 23b.

  In FIG. 4, the trench gate structure is simplified and only the trench 13 is illustrated.

  A part of the plurality of pads 4 shown in FIG. 1 is a connection portion for electrically connecting the IGBT element and an external circuit, and the gate electrode 18 is formed on the one surface 11a of the semiconductor substrate 11 as described above. It is connected to the pad 4 through the formed gate wiring. The remaining part of the pad 4 is used for temperature sensing or the like.

As described above, the semiconductor device 1 of this embodiment is configured. In the present embodiment, the N type, N ⁻ type, and N ⁺ type correspond to the first conductivity type of the present invention, and the P type and P ⁺ type correspond to the second conductivity type of the present invention.

Next, a method for manufacturing the semiconductor device 1 will be described. First, an N ⁻ type wafer is prepared, and a P type base layer 12 is formed on the surface of the wafer by thermal diffusion. Then, a trench gate structure is formed in each chip formation region of the wafer. The specific manufacturing process of the trench gate structure is the same as a well-known one, and although not described in detail, a trench 13 is formed, and polysilicon serving as a gate insulating film 17 and a gate electrode 18 on the inner wall surface of the trench 13. Can be formed.

Next, a mask in which a region where the CS layer 21 is to be formed is opened is placed on the wafer, and N-type impurity ions are implanted using this mask. In order to form the CS layer 21 deeply, the ion implantation is performed by a high acceleration implantation of about 1 MeV or a channeling implantation of about 600 KeV. The dose amount is about 1 × 10 ¹¹ to 1 × 10 ¹³ cm ⁻² in any case.

  Subsequently, a mask in which a region where the emitter region 15 is to be formed is opened is placed on the wafer, and N-type impurity ions are implanted using this mask. In addition, after removing the previously used mask, a mask in which a region where the body region 16 is to be formed is opened is placed on the wafer, and ion implantation of P-type impurities is performed using the mask. Then, after removing the mask again, the emitter region 15 and the body region 16 are formed by activating the impurities implanted by the heat treatment.

Next, a mask in which a region where the HS layer 20 is to be formed is opened is placed on the wafer, and N-type impurity ions are implanted using this mask and heat treatment is performed. For example, ion implantation may be performed by implanting P (phosphorus) with an acceleration voltage of 500 KeV and a dose of 1 × 10 ¹² to 1 × 10 ¹⁴ cm ⁻² . Alternatively, P (phosphorus) may be ion-implanted and heat-treated, and then B (boron) may be ion-implanted to adjust the impurity concentration of the first region 19a.

  The heat treatment for activating the impurities is performed simultaneously after, for example, ion implantation of all of the impurities constituting the CS layer 21, the impurities constituting the emitter region 15, the impurities constituting the body region 16, and the impurities constituting the HS layer 20. You may go.

  Thereafter, an interlayer insulating film 22 is formed on the base layer 12, and a part of the emitter region 15, the body region 16, and a part of the first region 19 a of the thinning region 19 are exposed to the interlayer insulating film 22. Thus, the contact hole 22a is formed. Subsequently, an emitter electrode 23 is formed on the interlayer insulating film 22, and the emitter electrode 23 and the first region 19a of the thinned region 19 are electrically connected through the contact hole 22a. Note that the pad 4 and the like are formed simultaneously with the formation of the emitter electrode 23.

  Further, the FS layer 24 is formed on the back surface side of the wafer, and the collector layer 25 is formed on the opposite side of the drift layer 10 with the FS layer 24 interposed therebetween. Then, the collector electrode 26 is formed on the collector layer 25 (the back surface of the wafer), and the wafer is individually diced to manufacture the semiconductor device 1. In addition, the guard ring part 3 etc. are formed in said process or a dedicated process.

  Next, the operation of the IGBT element in the semiconductor device 1 will be described.

  First, the on state will be described. In the IGBT element, when a voltage equal to or higher than the threshold voltage of the MOS gate is applied to the gate electrode 18, an inversion layer is formed in a portion of the channel region 14 in contact with the trench 13. Then, electrons are supplied from the emitter region 15 to the drift layer 10 through the inversion layer, and holes are supplied from the collector layer 25 to the drift layer 10, and the resistance value of the drift layer 10 decreases due to conductivity modulation and is turned on. It becomes a state.

  At this time, in the present embodiment, holes supplied to the drift layer 10 are difficult to escape to the emitter electrode 23 by the HS layer 20 in the dummy cell, and difficult to escape to the emitter electrode 23 by the CS layer 21 in the IGBT cell. For this reason, the on-voltage can be reduced.

  Next, the off state will be described. When a voltage lower than the threshold voltage of the MOS gate is applied to the gate electrode 18, the inversion layer formed in the channel region 14 disappears, electrons are no longer supplied from the emitter region 15, and holes are supplied from the collector layer 25. It will not be done. Thereafter, the electrons and holes accumulated in the drift layer 10 are recombined with each other and disappear, or are discharged through the emitter electrode 23 or the collector electrode 26.

  As described above, in the present embodiment, the HS layer 20 is formed in the thinning region 19, and the CS layer 21 is formed between the drift layer 10 and the channel region 14. Therefore, the holes supplied to the drift layer 10 are difficult to escape from the channel region 14 to the emitter electrode 23, and a larger amount of holes can be accumulated in the drift layer 10. Therefore, the ON voltage can be further reduced.

Further, the impurity concentration of the CS layer 21 can be appropriately changed. As shown in FIG. 5, the CS layer 21 becomes a potential wall as the impurity concentration of the CS layer 21 is increased. It can be difficult to escape. Specifically, when the impurity concentration of the CS layer 21 is 7.0 × 10 ¹⁶ cm ⁻³ , the on-voltage can be reduced to about 2.83 V, and the collector breakdown voltage can be about 1320 V. FIG. 5 is a diagram showing the relationship between the ON voltage and the collector breakdown voltage when the impurity concentration of the CS layer 21 is increased in order from the plot without the CS layer to the plot of 7.0 × 10 ¹⁶ cm ⁻³ .

  Further, the present inventors have also proposed a semiconductor device in which the thinning region 19 is not formed and the CS layer 21 is formed between the drift layer 10 and the channel region 14 as a semiconductor device that can reduce the on-voltage. Study was carried out. Note that the semiconductor device in which the thinning region 19 is not formed is, in other words, a semiconductor device in which no dummy cell is formed and the base layer 12 functions as the channel region 14. Further, in FIG. 5, such a semiconductor device is shown as an entire surface CS structure.

As shown in FIG. 5, in the semiconductor device having the entire surface CS structure, when the impurity concentration of the CS layer 21 is 7.0 × 10 ¹⁶ cm ⁻³ , the on-voltage can be reduced to about 2.7V. The collector breakdown voltage is reduced to about 880V.

  That is, in the semiconductor device 1 in which the HS layer 20 is formed in the thinning region 19 and the CS layer 21 is formed between the channel region 14 and the drift layer 10 as in the present embodiment, the reduction in collector breakdown voltage is suppressed. However, the on-voltage can be reduced.

(Second Embodiment)
A second embodiment of the present invention will be described. In the present embodiment, the configuration of the CS layer 21 is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment, and thus the description thereof is omitted here.

  As shown in FIGS. 6 and 7, in the present embodiment, the CS layer 21 is formed away from the trench 13. That is, the channel region 14 is connected to the drift layer 10 at a portion in contact with the side surface of the trench 13. In FIG. 6, the gate insulating film 17 and the gate electrode 18 in the trench 13 are omitted.

  According to this, since the CS layer 21 is not in contact with the trench 13, it is possible to suppress the concentration of the electric field at the bottom of the trench 13 and improve the collector breakdown voltage.

(Third embodiment)
A third embodiment of the present invention will be described. In the present embodiment, the configuration of the CS layer 21 is changed with respect to the first embodiment, and the other aspects are the same as those in the first embodiment, and thus the description thereof is omitted here.

  As shown in FIGS. 8 to 10, in the present embodiment, the CS layer 21 is formed to be spaced apart from each other in the extending direction of the trench 13. In other words, the CS layer 21 is partially thinned out in the extending direction of the trench 13. In FIG. 8, the gate insulating film 17 and the gate electrode 18 in the trench 13 are omitted.

  Even in such a semiconductor device 1, since there is a portion where the CS layer 21 does not contact the trench 13, the same effect as in the second embodiment can be obtained.

  Note that this embodiment can be combined with the second embodiment. That is, as shown in FIG. 11, the CS layer 21 may be thinned out in the extending direction of the trench 13 while the CS layer 21 is formed away from the side surface of the trench 13. This further suppresses the concentration of the electric field at the bottom of the trench 13.

(Fourth embodiment)
A fourth embodiment of the present invention will be described. In the present embodiment, a so-called RC-IGBT element in which a diode element is formed together with an IGBT element is formed in the cell area 2 with respect to the first embodiment, and the other aspects are the same as those in the first embodiment. Therefore, the description is omitted here.

  As shown in FIG. 12, in the present embodiment, an RC-IGBT element is formed in the cell area 2. Specifically, this structure is repeatedly mirror-inverted with the structure shown in FIG. 3 as a minimum unit to form an IGBT region 27, and this structure is repeatedly mirror-inverted with the structure shown in FIG. 13 as a minimum unit to form a diode region. 28 is configured.

  In the IGBT region 27, as shown in FIGS. 3 and 12, a collector layer 25 is formed on the opposite side of the drift layer 10 with the FS layer 24 interposed therebetween. As a result, the IGBT region 27 has a structure in which holes are supplied from the collector layer 25.

  On the other hand, in the diode region 28, as shown in FIGS. 12 and 13, an N-type cathode layer 29 is formed on the opposite side of the drift layer 10 with the FS layer 24 interposed therebetween. As a result, the diode region 28 has a structure in which a diode element is formed between the emitter and the collector. That is, on the other surface 11 b side of the semiconductor substrate 11, the IGBT region 27 and the diode region 28 are partitioned depending on whether the layer formed on the FS layer 24 is the collector layer 25 or the cathode layer 29. Yes. In the diode region 28, only the trench gate structure formed in the IGBT region 27 is formed, and the emitter region 15, the body region 16, and the HS layer 20 are not formed.

  In the surface direction of the one surface 11a of the semiconductor substrate 11, the IGBT region 27 in which the collector layer 25 is formed operates as an IGBT element, and the diode region 28 in which the cathode layer 29 is formed operates as a diode element. That is, the collector electrode 26 of the present embodiment also serves as a cathode electrode.

  In the present embodiment, as shown in FIG. 14, IGBT regions 27 and diode regions 28 are alternately formed in the cell area 2, and FIG. 12 is along the line XII-XII in FIG. 14. It is sectional drawing.

  As described above, the semiconductor device 1 according to this embodiment is configured. Thus, the present invention can also be applied to the semiconductor device 1 in which the RC-IGBT element is formed in the cell area 2.

  Note that the base layer 12 in the diode region 28 is a portion that functions as an anode layer, and may have the same impurity concentration as the base layer 12 in the IGBT region 27, and has a lower impurity concentration than the base layer 12 in the IGBT region 27. May be.

  When the base layer 12 in the diode region 28 has a lower impurity concentration than the base layer 12 in the IGBT region 27, the amount of hole injection during diode operation can be reduced, and the recovery loss can be reduced. . In such a semiconductor device 1, for example, the base layer 12 in the IGBT region 27 and the base layer (anode layer) 12 in the diode region 28 may be formed in separate steps.

  In the above description, the emitter region 15, the body region 16, and the HS layer 20 are not formed in the diode region 28. However, the emitter region 15, the body region 16, and the HS layer 20 are formed in the diode region 28. It may be. That is, the semiconductor device 1 in which a part of the collector layer 25 is the cathode layer 29 in the cell area 2 shown in FIG.

  Furthermore, in the present embodiment, the diode region 28 may not have a trench gate structure.

(Fifth embodiment)
A fifth embodiment of the present invention will be described. The present embodiment is different from the first embodiment in that planar type IGBT elements are formed in the cell area 2, and the other aspects are the same as those of the first embodiment, and thus the description thereof is omitted here.

As shown in FIG. 15, a plurality of P-type regions are formed on the one surface 11 a side of the N ⁻ -type semiconductor substrate 11. Each P-type region corresponds to the channel region 14 and the thinning region 19 described above. In this embodiment, as shown in FIG. 16, the channel region 14 and the thinning region 19 include the semiconductor substrate 11. It is formed in a staggered pattern alternately in the surface direction of the one surface 11a. In FIGS. 15 and 16, the emitter electrode 23 is omitted.

Emitter regions 15 are formed on the surface layer of the channel region 14 so as to be separated from each other. A P ⁺ -type body region 16 is formed between the spaced emitter regions 15. A CS layer 21 is formed along the channel region 14 between the drift layer 10 and the channel region 14. Specifically, the CS layer 21 is formed so that the end portion on the thinning region 19 side reaches the one surface 11 a of the semiconductor substrate 11.

  On the other hand, the thinning region 19 is formed with an N-type HS layer 20 that divides the thinning region 19 into a first region 19a on the one surface 11a side of the semiconductor substrate 11 and a second region 19b on the other surface 11b side. . Specifically, the HS layer 20 is formed so that the end on the channel region 14 side reaches the one surface 11 a of the semiconductor substrate 11. Also in the present embodiment, the HS layer 20 is formed shallower than the bottom of the body region 16 in order to suppress a decrease in collector breakdown voltage.

  A gate insulating film 17 is formed on one surface 11 a of the semiconductor substrate 11. The gate insulating film 17 includes a body region 16 in the channel region 14, a part of the emitter region 15, and a first one in the thinning region 19. A contact 17a is formed so that a part of one region 19a is exposed. A gate electrode 18 is formed on the gate insulating film 17, and the gate electrode 18 is covered with the gate insulating film 17. An emitter electrode 23 (not shown) is provided so as to contact the body region 16, the emitter region 15, and the first region 19 a exposed from the gate insulating film 17.

  An FS layer 24 and a collector layer 25 are formed on the other surface 11b side of the semiconductor substrate 11, and a collector electrode 26 is formed on the collector layer 25 (the other surface 11b of the semiconductor substrate 11).

  As described above, the semiconductor device 1 according to this embodiment is configured. As described above, the present invention can also be applied to the semiconductor device 1 in which the planar IGBT element is formed in the cell area 2.

(Other embodiments)
The structures shown in the above embodiments are examples, and the present invention is not limited to the structures shown above, and other structures including the characteristics of the present invention can be used.

For example, although the gate electrode 18 is P-type polysilicon, the gate electrode 18 may be N ⁺ -type polysilicon if the voltage can be controlled by an external circuit.

  In each of the embodiments described above, the emitter region 15 and the body region 16 are provided along the longitudinal direction of the trench 13 in the first region 19 a. However, the emitter region 15 and the body region 16 are disposed along the longitudinal direction of the trench 13. And may be arranged alternately.

  In the first to fourth embodiments, the example in which the channel regions 14 and the thinning regions 19 are alternately arranged has been described. For example, two thinning regions 19 are disposed between the adjacent channel regions 14. It may be. That is, the order of arrangement of the channel region 14 and the thinning region 19 can be changed as appropriate. Similarly, in the fifth embodiment, the channel region 14 and the thinning region 19 may not be formed in a staggered pattern.

  Further, in each of the above embodiments, the vertical semiconductor device 1 that flows current in the thickness direction of the semiconductor substrate 11 has been described. However, the present invention is applied to the horizontal semiconductor device 1 that flows current in the plane direction of the semiconductor substrate 11. You can also That is, the semiconductor device 1 in which the collector layer 25 is formed at a position separated from the base layer 12 (the channel region 14 and the thinning region 19) on the one surface 11a side of the semiconductor substrate 11 may be used. In this case, in the fourth embodiment, a semiconductor device in which the cathode layer 29 is formed together with the collector layer 25 at a position separated from the base layer 12 (the channel region 14 and the thinning region 19) on the one surface 11a side of the semiconductor substrate 11. 1 may be used.

  And in the said 3rd Embodiment, the part thinned out among the CS layers 21 may be one area | region. That is, if there is even a portion where the CS layer 21 is not in contact with the trench 13, it is possible to suppress the concentration of the electric field at the bottom of the trench 13 in that region and improve the collector breakdown voltage.

DESCRIPTION OF SYMBOLS 1 Semiconductor device 10 Drift layer 11 Semiconductor substrate 11a One surface 11b Other surface 12 Base layer 13 Trench 14 Channel region 15 Emitter region 17 Gate insulating film 18 Gate electrode 19 Thinned-out region 19a First region 19b Second region 20 HS layer 21 CS layer 23 Emitter electrode 25 Collector layer 26 Collector electrode

Claims (7)

A semiconductor substrate (11) having one surface (11a) and constituting a first conductivity type drift layer (10);
A plurality of second conductivity type channel regions (14) formed on the one surface side;
A first conductivity type emitter region (15) formed in a surface layer portion of the channel region;
A plurality of thinning regions (19) of the second conductivity type formed on the one surface side separately from the channel region;
A hole stopper layer of a first conductivity type that is formed in the thinning region and is potential-separated into a first region (19a) on the one surface side and a second region (19b) on the bottom side of the thinning region. (20) and
An emitter electrode (23) electrically connected to the emitter region and the first region;
A collector layer (25) of a second conductivity type formed at a position spaced apart from the channel region and the thinning region of the semiconductor substrate;
A collector electrode (26) electrically connected to the collector layer,
A thinning-type semiconductor device in which the thinning region in which the emitter region is not formed between the channel regions is disposed,
A semiconductor device, wherein a first conductivity type carrier storage layer (21) having an impurity concentration higher than that of the drift layer is formed between the channel region and the drift layer. In the semiconductor substrate, a second conductivity type base layer (12) is formed on the one surface side, and a plurality of trenches (13) penetrating the base layer and reaching the drift layer extend in a predetermined direction. Has been
The base layer is separated into a plurality by the trench, and the channel region and the thinning region are constituted by the separated base layer,
2. The semiconductor device according to claim 1, wherein a gate insulating film (17) is formed on a wall surface of the trench and a gate electrode (18) is disposed on the gate insulating film.   The semiconductor device according to claim 2, wherein at least a part of the channel region in contact with the trench is connected to the drift layer.   The semiconductor device according to claim 3, wherein the carrier storage layer is formed apart from a side surface of the trench.   The semiconductor device according to claim 3, wherein the carrier storage layer is separated into a plurality in the extending direction of the trench.   The semiconductor device according to claim 1, wherein a gate insulating film (17) is formed on the channel region of the one surface, and a gate electrode (18) is formed on the gate insulating film. . 7. The semiconductor device according to claim 1, wherein a part of the collector layer is a first conductivity type cathode layer (27).

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