JP2010153622A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010153622A
JP2010153622A JP2008330661A JP2008330661A JP2010153622A JP 2010153622 A JP2010153622 A JP 2010153622A JP 2008330661 A JP2008330661 A JP 2008330661A JP 2008330661 A JP2008330661 A JP 2008330661A JP 2010153622 A JP2010153622 A JP 2010153622A
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layer
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semiconductor
pillar
base layer
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Nana Hatano
菜名 羽田野
Wataru Saito
渉 齋藤
Shotaro Ono
昇太郎 小野
Hiroshi Ota
浩史 大田
Yoshio Watanabe
美穂 渡辺
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Toshiba Corp
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    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
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    • H01L29/063—Reduced surface field [RESURF] pn-junction structures
    • H01L29/0634—Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
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    • H01L29/66409—Unipolar field-effect transistors
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    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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Abstract

<P>PROBLEM TO BE SOLVED: To increase a high breakdown voltage and decrease an on-state resistance for a semiconductor device having superjunction structure, even when a lateral pitch is narrow. <P>SOLUTION: In a power MOSFET 70, a p-type pillar layer 2 and an n-type pillar layer 5 are periodically and alternately formed on an n<SP>+</SP>-type substrate 1, and a pillar layer used as a superjunction structure is prepared. On the p-type pillar layer 2 and at top side face of the n-type pillar layer 5 in contact with the p-type pillar layer 2, a p-type base layer 3 with a depth of 3 μm and a region having a constant impurity concentration up to 90% in the depth direction is prepared, using the silicon epitaxial method. Since elevated temperature thermal diffusion is not used for formation of the p-type base layer 3 for the power MOSFET 70, deterioration in the effective pillar density is suppressed. Thereby, the power MOSFET 70 has a region with an effective pillar density of 50% or more up to a diffusion length of 2 μm. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体素子に係り、特にドリフト層にｐ型ピラー層とｎ型ピラー層が横方向に交互に設けられたスーパージャンクション構造を有する半導体素子に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a super junction structure in which p-type pillar layers and n-type pillar layers are alternately provided in a lateral direction on a drift layer.

縦型パワーＭＯＳＦＥＴのオン抵抗は、伝導層としてのドリフト層部分の電気抵抗に大きく依存する。このドリフト層の電気抵抗は、その不純物濃度で決定され、不純物濃度を高くすればオン抵抗を下げることができる。しかし、不純物濃度が高くなるとドリフト層とベース層から形成されるＰＮ接合の耐圧が低下するので、不純物濃度は耐圧に応じて決定する限界以上に上げることができない。このため、素子耐圧とオン抵抗との間にはトレードオフの関係が存在する。このトレードオフの関係を解決するＭＯＳＦＥＴの一例として、ドリフト層にスーパージャンクション構造と呼称されるｐ型ピラー層とｎ型ピラー層を半導体基板上の横方向に交互に埋め込んだ構造が知られている。スーパージャンクション構造は、ｐ型ピラー層とｎ型ピラー層に含まれるチャージ量（不純物量）を同じにすることにより、擬似的にノンドープ層を作り出し、高耐圧を保持しながら高ドープされたｎ型ピラー層を通して電流を流すことで材料限界を超えた低オン抵抗を実現している（例えば、特許文献１参照。）。   The on-resistance of the vertical power MOSFET greatly depends on the electric resistance of the drift layer portion as the conductive layer. The electrical resistance of the drift layer is determined by the impurity concentration, and the on-resistance can be lowered by increasing the impurity concentration. However, since the breakdown voltage of the PN junction formed from the drift layer and the base layer decreases as the impurity concentration increases, the impurity concentration cannot be increased beyond the limit determined according to the breakdown voltage. For this reason, there is a trade-off relationship between element breakdown voltage and on-resistance. As an example of a MOSFET that solves this trade-off relationship, a structure is known in which a p-type pillar layer and an n-type pillar layer called a super junction structure are alternately embedded in a drift layer in a lateral direction on a semiconductor substrate. . The super junction structure creates a pseudo non-doped layer by making the charge amount (impurity amount) contained in the p-type pillar layer and the n-type pillar layer the same, and highly doped n-type while maintaining a high breakdown voltage. A low on-resistance exceeding the material limit is realized by passing a current through the pillar layer (see, for example, Patent Document 1).

特許文献１などに記載される縦型パワーＭＯＳＦＥＴでは、横方向のピッチを縮小化した場合、ベース層形成に必要な高温度で、且つ長時間の熱拡散によりｐ型ピラー層とｎ型ピラー層の濃度の打ち消しあいが発生し、実効的に不純物濃度が低下してオン抵抗が増加するという問題点がある。
特開２００７−１９１４６号公報 In the vertical power MOSFET described in Patent Document 1 or the like, when the pitch in the horizontal direction is reduced, the p-type pillar layer and the n-type pillar layer are formed at a high temperature necessary for base layer formation and by long-time thermal diffusion. There is a problem that the concentration of each other cancels out, the impurity concentration is effectively lowered, and the on-resistance is increased.
JP 2007-19146 A

本発明は、横方向のピッチが狭い場合でも耐圧が高く、且つオン抵抗を低くすることができるスーパージャンクション構造を有する半導体素子を提供する。   The present invention provides a semiconductor element having a super junction structure that has high breakdown voltage and low on-resistance even when the lateral pitch is narrow.

本発明の一態様の半導体素子は、第１導電型の半導体基板と、前記半導体基板上に設けられ、断面が短冊状の第１導電型の第１半導体ピラー層と第２導電型の第２半導体ピラー層とが前記半導体基板の表面に沿って横方向に交互に形成されるピラー層と、前記半導体基板に電気的に接続される第１の主電極と、前記第２半導体ピラー層の表面に設けられる第２導電型の半導体ベース層と、前記半導体ベース層の表面に設けられる第１導電型の半導体層と、前記半導体ベース層と前記半導体層に接するように設けられる第２の主電極と、前記半導体層と前記第１半導体ピラー層に亘る領域にゲート絶縁膜を介して設けられる制御電極とを具備し、前記半導体ベース層は横方向及び縦方向の不純物プロファイルが一定な領域を有することを特徴とする。   A semiconductor element of one embodiment of the present invention includes a first conductivity type semiconductor substrate, a first conductivity type first semiconductor pillar layer having a strip-shaped cross section, and a second conductivity type second substrate provided on the semiconductor substrate. Pillar layers in which semiconductor pillar layers are alternately formed in the lateral direction along the surface of the semiconductor substrate, a first main electrode electrically connected to the semiconductor substrate, and a surface of the second semiconductor pillar layer A second conductive type semiconductor base layer provided on the semiconductor base layer, a first conductive type semiconductor layer provided on a surface of the semiconductor base layer, and a second main electrode provided in contact with the semiconductor base layer and the semiconductor layer And a control electrode provided through a gate insulating film in a region extending between the semiconductor layer and the first semiconductor pillar layer, and the semiconductor base layer has a region having a constant lateral and vertical impurity profile. With features That.

本発明によれば、横方向のピッチが狭い場合でも耐圧が高く、且つオン抵抗を低くすることができるスーパージャンクション構造を有する半導体素子を提供することができる。   According to the present invention, it is possible to provide a semiconductor element having a super junction structure that has high breakdown voltage and low on-resistance even when the lateral pitch is narrow.

以下本発明の実施例について図面を参照しながら説明する。   Embodiments of the present invention will be described below with reference to the drawings.

まず、本発明の実施例１に係る半導体素子について、図面を参照して説明する。図１は半導体素子としてのパワーＭＯＳＦＥＴを示す断面図である。本実施例では、横方向に交互に設けられたｐ型ピラー層とｎ型ピラー層において、横方向及び縦方向の不純物プロファイルが一定な領域を設けている。ｐ型ピラー層上には、エピタキシャル法により不純物プロファイルが一定な領域を有するｐ型ベース層を設けている。   First, a semiconductor element according to Example 1 of the present invention will be described with reference to the drawings. FIG. 1 is a cross-sectional view showing a power MOSFET as a semiconductor element. In this embodiment, regions having constant impurity profiles in the horizontal direction and the vertical direction are provided in the p-type pillar layer and the n-type pillar layer alternately provided in the horizontal direction. A p-type base layer having a region having a constant impurity profile is provided on the p-type pillar layer by an epitaxial method.

図１に示すように、縦型パワーＭＯＳＦＥＴであるパワーＭＯＳＦＥＴ７０は、ｐ型ピラー層（第２半導体ピラー層）２とｎ型ピラー層（第１半導体ピラー層）５がドレイン層としてのｎ＋型基板１上の図中横方向に交互に周期的に形成されるピラー層を有する（スーパージャンクション構造）。ここでは、ピラー層を図中直交方向に延びるストライプ状に形成しているが、代わりに格子状或いは千鳥状に形成してもよい。 As shown in FIG. 1, a power MOSFET 70, which is a vertical power MOSFET, has an n + type in which a p-type pillar layer (second semiconductor pillar layer) 2 and an n-type pillar layer (first semiconductor pillar layer) 5 serve as drain layers. The substrate 1 has pillar layers alternately and periodically formed in the horizontal direction in the drawing (super junction structure). Here, the pillar layer is formed in a stripe shape extending in the orthogonal direction in the figure, but may alternatively be formed in a lattice shape or a staggered shape.

ピラー層が設けられるドレイン層としてのｎ＋型基板１の第１主面と相対向するｎ＋型基板１の第２主面には、ｎ＋型基板１と電気的に接続される第１の主電極としてのドレイン電極６が設けられる。 A first main surface electrically connected to the n + type substrate 1 is connected to a second main surface of the n + type substrate 1 opposite to the first main surface of the n + type substrate 1 as a drain layer provided with a pillar layer. A drain electrode 6 is provided as a main electrode.

ｐ型ピラー層２上と、ｐ型ピラー層２と接するｎ型ピラー層５の上側面部分にはｐ型ベース層（半導体ベース層）３が設けられる。ｎ型ピラー層５及びｎ型ピラー層５と接するｐ型ベース層３上には、ゲート絶縁膜８を介して制御電極としてのゲート電極９が設けられる。ゲート電極９は、側面及び上面部分が絶縁膜１０により分離される。   A p-type base layer (semiconductor base layer) 3 is provided on the p-type pillar layer 2 and on the upper surface portion of the n-type pillar layer 5 in contact with the p-type pillar layer 2. On the n-type pillar layer 5 and the p-type base layer 3 in contact with the n-type pillar layer 5, a gate electrode 9 as a control electrode is provided via a gate insulating film 8. The gate electrode 9 has a side surface and an upper surface portion separated by an insulating film 10.

ゲート電極９の両端部直下のｐ型ベース層３の表面には、ｎ型ソース層４が設けられる。ｎ型ソース層４と隣接配置される他のゲート電極９に設けられるｎ型ソース層４の間には、ｐ型ベース層３が残置される。ｐ型ベース層３、ｎ型ソース層４、及び絶縁膜１０上には、ｐ型ベース層３及びｎ型ソース層４と電気的に接続される第２電極としてのソース電極７が設けられる。   An n-type source layer 4 is provided on the surface of the p-type base layer 3 immediately below both ends of the gate electrode 9. The p-type base layer 3 is left between the n-type source layer 4 provided in the other gate electrode 9 disposed adjacent to the n-type source layer 4. On the p-type base layer 3, the n-type source layer 4, and the insulating film 10, a source electrode 7 as a second electrode that is electrically connected to the p-type base layer 3 and the n-type source layer 4 is provided.

次に、パワーＭＯＳＦＥＴの製造方法について図２乃至９を参照して説明する。図２乃至９はパワーＭＯＳＦＥＴの製造工程を示す断面図である。   Next, a method for manufacturing a power MOSFET will be described with reference to FIGS. 2 to 9 are cross-sectional views showing the manufacturing process of the power MOSFET.

図２に示すように、まず、Ｎ型不純物が高濃度にドープされたシリコン基板であるｎ＋型基板１上に、シリコンエピタキシャル成長法によりｐ型ピラー層２を形成する。ここで、エピタキシャル成長には、ｎ＋型基板１中の高濃度の不純物がオートドーピングしにくい比較的低温度の条件を用いるのが好ましい。オートドーピングが発生するとｎ＋型基板１側のｐ型ピラー層２の不純物濃度が低下する。 As shown in FIG. 2, first, a p-type pillar layer 2 is formed on an n + -type substrate 1 which is a silicon substrate doped with an N-type impurity at a high concentration by a silicon epitaxial growth method. Here, for the epitaxial growth, it is preferable to use a relatively low temperature condition in which high-concentration impurities in the n + -type substrate 1 are difficult to be auto-doped. When auto-doping occurs, the impurity concentration of the p-type pillar layer 2 on the n + -type substrate 1 side decreases.

次に、図３に示すように、ｎ＋型基板１表面が露呈するまでｐ型ピラー層２をエッチングして断面が矩形型形状を有する複数の溝１１を形成する。ここで、ピッチが同一になるように複数の溝１１が形成される。溝１１の形成は、例えばＲＩＥ（Reactive Ion Etching）法を用いる。その場合、ｐ型ピラー層２とｎ＋型基板１に発生するダメージや表面汚染を除去する目的でＲＩＥ後処理が行われる。 Next, as shown in FIG. 3, the p-type pillar layer 2 is etched until the surface of the n + -type substrate 1 is exposed to form a plurality of grooves 11 having a rectangular cross section. Here, the plurality of grooves 11 are formed so as to have the same pitch. For example, the RIE (Reactive Ion Etching) method is used to form the groove 11. In that case, RIE post-processing is performed for the purpose of removing damage and surface contamination occurring in the p-type pillar layer 2 and the n + -type substrate 1.

続いて、図４に示すように、シリコンエピタキシャル成長法により、溝１１の部分にｎ型ピラー層５を埋設する。ｎ型ピラー層５の形成は、ｐ型ピラー層２上に絶縁膜を形成し、例えば、ＵＨＶ−ＣＶＤ法を用いて選択エピタキシャル成長（ＳＥＧ：Selective Epitaxial Growth）により形成する。選択エピタキシャル成長は、ｎ＋型基板１中の高濃度の不純物がオートドーピングしにくい比較的低温度のエピタキシャル成長条件を用いるのが好ましい。その後、絶縁膜、ｐ型ピラー層２、及びｎ型ピラー層５を、例えばＣＭＰ（Chemical Mechanical Polishing）法を用いて研磨し、平坦化する。 Subsequently, as shown in FIG. 4, an n-type pillar layer 5 is buried in the groove 11 by a silicon epitaxial growth method. The n-type pillar layer 5 is formed by forming an insulating film on the p-type pillar layer 2 and performing, for example, selective epitaxial growth (SEG) using UHV-CVD. For selective epitaxial growth, it is preferable to use relatively low temperature epitaxial growth conditions in which high-concentration impurities in the n + -type substrate 1 are difficult to be auto-doped. Thereafter, the insulating film, the p-type pillar layer 2 and the n-type pillar layer 5 are polished and planarized by using, for example, a CMP (Chemical Mechanical Polishing) method.

ここで、ｐ型ピラー層２及びｎ型ピラー層５の不純物濃度は、例えば１×１０１５／ｃｍ３〜１×１０１６／ｃｍ３の範囲に設定される。ピラーのピッチは、例えば８μｍ〜１２μｍの範囲に設定される。ここでは、ｐ型ピラー層２を形成してからｎ型ピラー層５を形成しているが、ｎ型ピラー層５を形成してからｐ型ピラー層２を形成してもよい。 Here, the impurity concentration of the p-type pillar layer 2 and the n-type pillar layer 5 is set in a range of, for example, 1 × 10 15 / cm 3 to 1 × 10 16 / cm 3 . The pitch of the pillar is set in the range of 8 μm to 12 μm, for example. Here, the n-type pillar layer 2 is formed after the p-type pillar layer 2 is formed, but the p-type pillar layer 2 may be formed after the n-type pillar layer 5 is formed.

そして、図５に示すように、ｐ型ピラー層２の上部と、ｐ型ピラー層２と接するｎ型ピラー層５の側面部をエッチングして断面が矩形型形状を有する複数の溝１２を形成する。ここで、ピッチが同一になるように複数の溝１２が形成される。溝１２の形成は、例えばＲＩＥ（Reactive Ion Etching）法を用いる。その場合、ｐ型ピラー層２とｎ型ピラー層５に発生するダメージや表面汚染を除去する目的でＲＩＥ後処理が行われる。   Then, as shown in FIG. 5, the upper part of the p-type pillar layer 2 and the side surface portion of the n-type pillar layer 5 in contact with the p-type pillar layer 2 are etched to form a plurality of grooves 12 having a rectangular cross section. To do. Here, the plurality of grooves 12 are formed so as to have the same pitch. For example, the RIE (Reactive Ion Etching) method is used to form the groove 12. In that case, RIE post-treatment is performed for the purpose of removing damage and surface contamination occurring in the p-type pillar layer 2 and the n-type pillar layer 5.

次に、図６に示すように、選択エピタキシャル成長（ＳＥＧ：Selective Epitaxial Growth）により、溝１２の部分にｐ型ベース層３を埋設する。ｎ型ピラー層５の形成は、ｎ型ピラー層５上に絶縁膜を形成し、例えば、選択エピタキシャル成長（ＳＥＧ：Selective Epitaxial Growth）により形成する。その後、絶縁膜、ｎ型ピラー層５、及びｐ型ベース層３を、例えばＣＭＰ（Chemical Mechanical Polishing）法を用いて研磨し、平坦化する。ここで、ｐ型ベース層３の不純物濃度は、例えば５×１０１６／ｃｍ３〜１×１０１７／ｃｍ３の範囲に設定される。ここでは、ｐ型ベース層３の幅をｐ型ピラー層２の幅よりも広く形成しているが、同じ幅或いは狭く形成してもよい。 Next, as shown in FIG. 6, the p-type base layer 3 is buried in the groove 12 by selective epitaxial growth (SEG). The n-type pillar layer 5 is formed by forming an insulating film on the n-type pillar layer 5, for example, by selective epitaxial growth (SEG). Thereafter, the insulating film, the n-type pillar layer 5 and the p-type base layer 3 are polished and planarized by using, for example, a CMP (Chemical Mechanical Polishing) method. Here, the impurity concentration of the p-type base layer 3 is set in a range of, for example, 5 × 10 16 / cm 3 to 1 × 10 17 / cm 3 . Here, although the width of the p-type base layer 3 is formed wider than the width of the p-type pillar layer 2, it may be formed to be the same width or narrower.

続いて、図７に示すように、ｎ型ピラー層５及びｐ型ベース層３上にゲート絶縁膜８とゲート電極９を積層形成し、周知のリソグラフィー法を用いて形成された図示しないレジスト膜をマスクとして、例えばＲＩＥ（Reactive Ion Etching）法によりゲート電極９とゲート絶縁膜８をエッチングする。その後、レジスト膜の除去及びＲＩＥ後処理する。   Subsequently, as shown in FIG. 7, a gate insulating film 8 and a gate electrode 9 are laminated on the n-type pillar layer 5 and the p-type base layer 3, and a resist film (not shown) formed by using a well-known lithography method. As a mask, the gate electrode 9 and the gate insulating film 8 are etched by, for example, RIE (Reactive Ion Etching). Thereafter, the resist film is removed and post-RIE processing is performed.

そして、図８に示すように、周知のリソグラフィー法を用いて形成された図示しないレジスト膜をマスクとして、ｐ型ベース層３の表面にｎ型不純物をイオン注入する。レジスト膜を除去後、このイオン注入層を熱処理により活性化させてｎ型ソース層４を形成する。   Then, as shown in FIG. 8, n-type impurities are ion-implanted into the surface of the p-type base layer 3 using a resist film (not shown) formed using a known lithography method as a mask. After removing the resist film, the ion-implanted layer is activated by heat treatment to form the n-type source layer 4.

次に、図９に示すように、ｐ型ベース層３、ｎ型ソース層４、及びゲート電極９上に絶縁膜１０を形成し、絶縁膜１０をエッチングしてソース開口部を形成する。ソース開口部を覆うように、ｐ型ベース層３及びｎ型ソース層４と電気的に接続される第２の主電極としてのソース電極７を形成する。ソース電極７形成後、ｎ＋型基板１の裏面にｎ＋型基板１と電気的に接続される第１の主電極としてのドレイン電極６を形成し、パワーＭＯＳＦＥＴ７０が完成する。 Next, as shown in FIG. 9, an insulating film 10 is formed on the p-type base layer 3, the n-type source layer 4, and the gate electrode 9, and the insulating film 10 is etched to form a source opening. A source electrode 7 as a second main electrode electrically connected to the p-type base layer 3 and the n-type source layer 4 is formed so as to cover the source opening. After the source electrode 7 formed, to form a drain electrode 6 as a first main electrode connected to the back surface of the n + -type substrate 1 n + -type substrate 1 and electrically, power MOSFET70 is completed.

次に、パワーＭＯＳＦＥＴの特性について図１０乃至１２を参照して説明する。図１０はパワーＭＯＳＦＥＴのベース層の不純物プロファイルを示す図、図１１は実効ピラー濃度と拡散長の関係を示す図、図１２は高加速イオン注入法を用いた場合のベース層の不純物プロファイルを示す図である。   Next, the characteristics of the power MOSFET will be described with reference to FIGS. 10 is a diagram showing the impurity profile of the base layer of the power MOSFET, FIG. 11 is a diagram showing the relationship between the effective pillar concentration and the diffusion length, and FIG. 12 shows the impurity profile of the base layer when the high acceleration ion implantation method is used. FIG.

なお、図１０は図１のＡ１−Ａ２線に沿うベース層の不純物プロファイルを示す図、図１１は図１のＢ１−Ｂ２線に沿う実効ピラー濃度と拡散長の関係を示す図である。図１１は、ｐ型ピラー層２の中央部からｎ型ピラー層５との境界部に向かう方向の距離（拡散長と表記）に対する実効ピラー濃度を示す図である。ピラー濃度とは、ｐ型ピラー層２とｎ型ピラー層５の不純物濃度の打ち消しあいが起こった後でのｐ型ピラー層２とｎ型ピラー層５の不純物濃度である。図１１では、打ち消しあいが起こった後でのｐ型ピラー層２の不純物濃度を実効ピラー濃度と表記している。実効ピラー濃度が１００％というのは、ｐ型ピラー層２とｎ型ピラー層５の不純物濃度の打ち消しあいが発生しない場合の不純物濃度である。   10 is a diagram showing the impurity profile of the base layer along the line A1-A2 in FIG. 1, and FIG. 11 is a diagram showing the relationship between the effective pillar concentration and the diffusion length along the line B1-B2 in FIG. FIG. 11 is a diagram showing the effective pillar concentration with respect to the distance (denoted as the diffusion length) in the direction from the center of the p-type pillar layer 2 toward the boundary with the n-type pillar layer 5. The pillar concentration is the impurity concentration of the p-type pillar layer 2 and the n-type pillar layer 5 after the cancellation of the impurity concentration of the p-type pillar layer 2 and the n-type pillar layer 5 occurs. In FIG. 11, the impurity concentration of the p-type pillar layer 2 after cancellation has been expressed as an effective pillar concentration. The effective pillar concentration of 100% is the impurity concentration when the impurity concentrations of the p-type pillar layer 2 and the n-type pillar layer 5 do not cancel each other.

図１０に示すように、本実施例では、シリコンエピタキシャル法を用いて、例えば、深さが３μｍで、深さ方向の不純物濃度が一定（ここでは、深さ方向の９０％までの領域が一定な不純物濃度１×１０１７／ｃｍ３）のｐ型ベース層３を形成している。しかも比較的低温度のシリコンエピタキシャル法を用いてｐ型ベース層３を形成している。 As shown in FIG. 10, in this embodiment, the silicon epitaxial method is used, for example, the depth is 3 μm and the impurity concentration in the depth direction is constant (here, the region up to 90% in the depth direction is constant). forming a p-type base layer 3 of an impurity concentration 1 × 10 17 / cm 3) . Moreover, the p-type base layer 3 is formed using a relatively low temperature silicon epitaxial method.

このため、ｐ型ピラー層２とｎ型ピラー層５の不純物濃度の打ち消しあいによる実効的な不純物濃度の低下が抑制され、オン抵抗を低減することができる。また、実効的な不純物濃度の低下が抑制されるので、予め不純物濃度の打ち消しあいを考慮してｐ型ピラー層２とｎ型ピラー層５の不純物濃度を上げておく必要がない。この結果、スーパージャンクション構造を構成するｐ型ピラー層２とｎ型ピラー層５のバラツキが抑制され、高耐圧化を図りやすくなる。ｐ型ベース層３を浅く形成してもトータルドーパント量を維持することができ、ｐ型ベース層３の横方向の幅を溝１２の幅で任意に調整することができ、表面のチャネル部の抵抗を低減することができる。   For this reason, a decrease in effective impurity concentration due to cancellation of impurity concentrations of the p-type pillar layer 2 and the n-type pillar layer 5 is suppressed, and the on-resistance can be reduced. In addition, since the effective decrease in the impurity concentration is suppressed, it is not necessary to increase the impurity concentrations of the p-type pillar layer 2 and the n-type pillar layer 5 in advance in consideration of the cancellation of the impurity concentration. As a result, variations in the p-type pillar layer 2 and the n-type pillar layer 5 constituting the super junction structure are suppressed, and a high breakdown voltage can be easily achieved. Even if the p-type base layer 3 is formed shallowly, the total dopant amount can be maintained, the lateral width of the p-type base layer 3 can be arbitrarily adjusted by the width of the groove 12, and the surface channel portion can be adjusted. Resistance can be reduced.

一方、イオン注入法と高温処理（高温熱拡散）を用いてｐ型ベース層３を形成した比較例では、ｐ型ベース層３の深さが本実施例よりも深く（４μｍ）、深さ方向の不純物濃度が一定ではない（表面不純物濃度が最も高く、深さ方向で徐々に不純物濃度が低下する）。しかもピラー層形成後に、比較的高温度の熱処理が行われる。   On the other hand, in the comparative example in which the p-type base layer 3 is formed using the ion implantation method and the high-temperature treatment (high-temperature thermal diffusion), the depth of the p-type base layer 3 is deeper than that of the present embodiment (4 μm), and the depth direction. The impurity concentration is not constant (the surface impurity concentration is the highest, and the impurity concentration gradually decreases in the depth direction). In addition, a relatively high temperature heat treatment is performed after the pillar layer is formed.

このため、ｐ型ピラー層２とｎ型ピラー層５の不純物濃度の打ち消しあいによる実効的な不純物濃度の低下が発生し、オン抵抗を低減することが困難となる（特に横方向のピッチが縮小化された場合、より顕著となる）。また、実効的な不純物濃度の低下が発生するので、予め不純物濃度の打ち消しあいを考慮してｐ型ピラー層２とｎ型ピラー層５の不純物濃度を上げておく必要がある。この結果、スーパージャンクション構造を構成するｐ型ピラー層２とｎ型ピラー層５のバラツキが発生し、高耐圧化を図りにくくなる（特に横方向のピッチが縮小化された場合、より顕著となる）。   For this reason, the effective impurity concentration is lowered due to the cancellation of the impurity concentrations of the p-type pillar layer 2 and the n-type pillar layer 5, and it becomes difficult to reduce the on-resistance (particularly, the lateral pitch is reduced). It becomes more prominent if Further, since the effective impurity concentration is lowered, it is necessary to increase the impurity concentrations of the p-type pillar layer 2 and the n-type pillar layer 5 in advance in consideration of the cancellation of the impurity concentration. As a result, the p-type pillar layer 2 and the n-type pillar layer 5 constituting the super junction structure vary, making it difficult to achieve a high breakdown voltage (particularly when the lateral pitch is reduced). ).

図１０に示すように、本実施例では高温熱拡散を行っていないことにより、ｐ型ベース層３の表面から深さの（２／３）である２μｍまでの不純物濃度が表面不純物濃度の９０％以上ある。また、図１１に示すように、本実施例では、高温熱拡散による実効ピラー濃度の低下が抑制され、p型ピラー層２の中央部から拡散長２μｍまで実効ピラー濃度が５０％以上となる領域を確保することができる。図示していないがｎ型ピラー層５でも同様に実効ピラー濃度が５０％以上となる領域を確保することができる。   As shown in FIG. 10, in this embodiment, since high-temperature thermal diffusion is not performed, the impurity concentration from the surface of the p-type base layer 3 to 2 μm, which is (2/3) of the depth, is 90% of the surface impurity concentration. % Or more. Further, as shown in FIG. 11, in this embodiment, a reduction in effective pillar concentration due to high-temperature thermal diffusion is suppressed, and the effective pillar concentration is 50% or more from the central portion of the p-type pillar layer 2 to the diffusion length of 2 μm. Can be secured. Although not shown, the n-type pillar layer 5 can also ensure a region where the effective pillar concentration is 50% or more.

図１２に示すように、ｐ型ベース層の形成をシリコンエピタキシャル法の代わりに、加速電圧を可変し、深さ方向に複数のピークを有するイオン注入層を形成し、比較的低温度の熱処理によりこのイオン注入層を活性化させる方法によりｐ型ベース層を形成してもよい。   As shown in FIG. 12, instead of the silicon epitaxial method, the p-type base layer is formed by changing the acceleration voltage, forming an ion implantation layer having a plurality of peaks in the depth direction, and performing heat treatment at a relatively low temperature. The p-type base layer may be formed by a method of activating this ion implantation layer.

ここでは、深さ方向で互いにピークが異なる４つのプロファイルが有するｐ型ベース層が形成される。このプロファイルの形成には、ｐ型の不純物（ボロン等）のイオン注入の加速電圧を、例えば数十ＫｅＶから数ＭｅＶの範囲の条件を適宜選択することにより達成できる。ｐ型ベース層の不純物濃度は、ピーク間のバレー濃度がピーク濃度の１０％以上に設定するのが好ましい。具体的には、ｐ型ベース層の不純物濃度を５×１０１６／ｃｍ３〜１×１０１７／ｃｍ３の範囲に設定し、ピラー濃度を１×１０１５／ｃｍ３〜１×１０１６／ｃｍ３の範囲に設定する。ここで、バレー濃度とは、ピークとピークの間の底部の不純物濃度を言う。 Here, a p-type base layer having four profiles having different peaks in the depth direction is formed. Formation of this profile can be achieved by appropriately selecting the acceleration voltage for ion implantation of p-type impurities (boron or the like), for example, in the range of several tens KeV to several MeV. The impurity concentration of the p-type base layer is preferably set so that the valley concentration between peaks is 10% or more of the peak concentration. Specifically, the impurity concentration of the p-type base layer is set in a range of 5 × 10 16 / cm 3 to 1 × 10 17 / cm 3 , and the pillar concentration is 1 × 10 15 / cm 3 to 1 × 10 16 / Set in the range of cm 3 . Here, the valley concentration refers to the impurity concentration at the bottom between the peaks.

このような設定により、シリコンエピタキシャル法と同様に、ｐ型ベース層３の表面から深さの（２／３）である２μｍまでの不純物濃度が表面不純物濃度の９０％以上を確保でき、シリコンエピタキシャル法を用いて形成されたｐ型ベース層３の場合（図１１に示す）と同様に、拡散長２μｍまで実効ピラー濃度が５０％以上となる領域を確保することができる。   With this setting, as in the silicon epitaxial method, the impurity concentration from the surface of the p-type base layer 3 to 2 μm, which is (2/3) of the depth, can ensure 90% or more of the surface impurity concentration. Similar to the case of the p-type base layer 3 formed by the method (shown in FIG. 11), a region where the effective pillar concentration is 50% or more can be secured up to a diffusion length of 2 μm.

ピーク間のバレー濃度がピーク濃度の１０％以下に設定した場合、バレー濃度が５×１０１５／ｃｍ３〜１×１０１６／ｃｍ３の範囲以下となりピラー濃度と同等となる。この結果、高電圧を印加した場合にｐ型ベース層のバレー部分が空乏化してしまうという問題点が発生するので好ましくない。 When the valley concentration between the peaks is set to 10% or less of the peak concentration, the valley concentration is equal to or less than the range of 5 × 10 15 / cm 3 to 1 × 10 16 / cm 3 and the pillar concentration. As a result, when a high voltage is applied, the valley portion of the p-type base layer is depleted, which is not preferable.

次に、パワーＭＯＳＦＥＴの終端部について図１３を参照して説明する。図１３はパワーＭＯＳＦＥＴの終端部を示す断面図である。   Next, the termination portion of the power MOSFET will be described with reference to FIG. FIG. 13 is a cross-sectional view showing a termination portion of the power MOSFET.

図１３に示すように、パワーＭＯＳＦＥＴ７０の終端部には、ｎ−層２１の表面にｐ型ベース層３と離間し、終端のｐ型ベース層３の外周を囲うように複数のｐ型ガードリング層２２が設けられる。ｐ型ガードリング層２２上には、絶縁膜２３をエッチングした開口部を覆うように、ｐ型ガードリング層２２と電気的に接続されるガードリング電極２４が設けられる。 As shown in FIG. 13, the power MOSFET 70 has a terminal portion with a plurality of p-type guard rings spaced from the p-type base layer 3 on the surface of the n − layer 21 and surrounding the outer periphery of the terminal p-type base layer 3. A layer 22 is provided. A guard ring electrode 24 electrically connected to the p type guard ring layer 22 is provided on the p type guard ring layer 22 so as to cover the opening obtained by etching the insulating film 23.

次に、パワーＭＯＳＦＥＴの終端部の製造方法について図１４を参照して説明する。   Next, a method for manufacturing the terminal portion of the power MOSFET will be described with reference to FIG.

図１４に示すように、ｐ型ガードリング層２２は、ｐ型ベース層３の形成と同じ工程で行われる。具体的には、ｐ型ピラー層２の上部と、ｐ型ピラー層２と接するｎ型ピラー層５の側面部、及びｎ−層２１の上部をエッチングして断面が矩形型形状を有する複数の溝１２を形成する。なお、これ以降の工程については、図示及び説明を省略する。 As shown in FIG. 14, the p-type guard ring layer 22 is performed in the same process as the formation of the p-type base layer 3. Specifically, the upper part of the p-type pillar layer 2, the side surface part of the n-type pillar layer 5 in contact with the p-type pillar layer 2, and the upper part of the n − layer 21 are etched to have a plurality of cross sections having a rectangular shape. A groove 12 is formed. In addition, illustration and description are abbreviate | omitted about the process after this.

上述したように、本実施例の半導体素子では、ｐ型ピラー層２とｎ型ピラー層５がｎ＋型基板１上に交互に周期的に形成され、スーパージャンクション構造となるピラー層が設けられる。ｐ型ピラー層２上と、ｐ型ピラー層２と接するｎ型ピラー層５の上側面部分には、シリコンエピタキシャル法により、深さが３μｍで、深さ方向の９０％までの領域が一定な不純物濃度を有するｐ型ベース層３が設けられる。ｎ型ピラー層５及びｎ型ピラー層５と接するｐ型ベース層３上には、ゲート絶縁膜８を介してゲート電極９が設けられる。ゲート電極９は、側面及び上面部分が絶縁膜１０により分離される。ゲート電極９の両端部直下のｐ型ベース層３の表面には、ｎ型ソース層４が設けられる。 As described above, in the semiconductor element of this embodiment, the p-type pillar layer 2 and the n-type pillar layer 5 are alternately and periodically formed on the n + -type substrate 1 to provide a pillar layer having a super junction structure. . On the p-type pillar layer 2 and on the upper side surface portion of the n-type pillar layer 5 in contact with the p-type pillar layer 2, a depth of 3 μm and a region up to 90% in the depth direction are constant by silicon epitaxial method. A p-type base layer 3 having an impurity concentration is provided. A gate electrode 9 is provided on the n-type pillar layer 5 and the p-type base layer 3 in contact with the n-type pillar layer 5 with a gate insulating film 8 interposed therebetween. The gate electrode 9 has a side surface and an upper surface portion separated by an insulating film 10. An n-type source layer 4 is provided on the surface of the p-type base layer 3 immediately below both ends of the gate electrode 9.

このため、パワーＭＯＳＦＥＴ７０では、横方向のピッチを縮小化した場合でも、高温熱拡散によって発生するｐ型ピラー層２とｎ型ピラー層５の不純物濃度の打ち消しあいによる実効ピラー濃度の低下が抑制され、拡散長２μｍまで実効ピラー濃度が５０％以上となる領域を確保することができる。ｐ型ベース層３と同様にｐ型ピラー層２とｎ型ピラー層５の不純物は拡散が抑制されているので、ｐ型ピラー層２とｎ型ピラー層５の中心部では不純物濃度が変化せず、一定である。したがって、実効的な不純物濃度の低下を抑制でき、パワーＭＯＳＦＥＴ７０の高耐圧化を図りながら、低オン抵抗化を達成することができる。   For this reason, in the power MOSFET 70, even when the lateral pitch is reduced, a reduction in effective pillar concentration due to cancellation of impurity concentrations of the p-type pillar layer 2 and the n-type pillar layer 5 caused by high-temperature thermal diffusion is suppressed. A region where the effective pillar concentration is 50% or more can be secured up to a diffusion length of 2 μm. Similar to the p-type base layer 3, since the diffusion of impurities in the p-type pillar layer 2 and the n-type pillar layer 5 is suppressed, the impurity concentration changes at the center of the p-type pillar layer 2 and the n-type pillar layer 5. It is constant. Therefore, it is possible to suppress a decrease in effective impurity concentration, and it is possible to achieve a low on-resistance while increasing the breakdown voltage of the power MOSFET 70.

なお、本実施例では、Ｎｃｈ型のスーパージャンクション構造を有するパワーＭＯＳＦＥＴ７０に適用しているが、Ｐｃｈ型のスーパージャンクション構造を有するパワーＭＯＳＦＥＴにも適用することができる。   In this embodiment, the present invention is applied to the power MOSFET 70 having the Nch type super junction structure, but can also be applied to the power MOSFET having the Pch type super junction structure.

次に、本発明の実施例２に係る半導体素子について、図面を参照して説明する。図１５は半導体素子としてのパワーＭＯＳＦＥＴを示す断面図である。本実施例では、パワーＭＯＳＦＥＴをトレンチ形状にしている。   Next, a semiconductor element according to Example 2 of the present invention will be described with reference to the drawings. FIG. 15 is a cross-sectional view showing a power MOSFET as a semiconductor element. In this embodiment, the power MOSFET has a trench shape.

以下、実施例１と同一構成部分には、同一符号を付してその部分の説明を省略し、異なる部分のみ説明する。   In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

図１５に示すように、パワーＭＯＳＦＥＴ７１は、ゲートが基板に埋設されたトレンチ形状を有する縦型パワーＭＯＳＦＥＴである。   As shown in FIG. 15, the power MOSFET 71 is a vertical power MOSFET having a trench shape with a gate embedded in a substrate.

ｐ型ピラー層２上には、ｐ型ベース層３が形成される。ｎ型ピラー層５上とｐ型ベース層３の側面には、ゲート絶縁膜８を介してゲート電極９が基板に埋設される。ｐ型ベース層３の両側の上端部には、ゲート絶縁膜８と接するようにｎ型ソース層４が設けられる。   A p-type base layer 3 is formed on the p-type pillar layer 2. A gate electrode 9 is embedded in the substrate via a gate insulating film 8 on the n-type pillar layer 5 and the side surface of the p-type base layer 3. An n-type source layer 4 is provided on the upper ends on both sides of the p-type base layer 3 so as to be in contact with the gate insulating film 8.

ゲート絶縁膜８及びゲート電極９の上部には、絶縁膜１０が設けられ、ゲート電極９を周囲から電気的に分離している。ｐ型ベース層３、ｎ型ソース層４、及び絶縁膜１０上には、ｐ型ベース層３及びｎ型ソース層４と電気的に接続される第２電極としてのソース電極７が設けられる。   An insulating film 10 is provided on the gate insulating film 8 and the gate electrode 9 to electrically isolate the gate electrode 9 from the surroundings. On the p-type base layer 3, the n-type source layer 4, and the insulating film 10, a source electrode 7 as a second electrode that is electrically connected to the p-type base layer 3 and the n-type source layer 4 is provided.

次に、パワーＭＯＳＦＥＴの製造方法について図１６及び図１７を参照して説明する。図１６及び図１７はパワーＭＯＳＦＥＴの製造工程を示す断面図である。   Next, a method for manufacturing a power MOSFET will be described with reference to FIGS. 16 and 17 are cross-sectional views showing the manufacturing process of the power MOSFET.

図１６に示すように、ｐ型ピラー層２及びｎ型ピラー層５を形成後、シリコンエピタキシャル法により、ｐ型ピラー層２及びｎ型ピラー層５上にｐ型ベース層３を形成する。   As shown in FIG. 16, after forming the p-type pillar layer 2 and the n-type pillar layer 5, the p-type base layer 3 is formed on the p-type pillar layer 2 and the n-type pillar layer 5 by silicon epitaxial method.

次に、図１７に示すように、ｎ型ピラー層５まで達するように断面が矩形型形状を有する複数の溝１３を形成する。ここで、ピッチが同一になるように複数の溝１３が形成される。溝１３の形成は、例えばＲＩＥ（Reactive Ion Etching）法を用いる。その場合、ｐ型ピラー層２とｎ型ピラー層５に発生するダメージや表面汚染を除去する目的でＲＩＥ後処理が行われる。ここでは、トレンチゲートの横幅となる溝１３の幅をｎ型ピラー層５の横幅と等しく形成しているが、溝１３の幅をｎ型ピラー層５の横幅よりも広く、或いは狭く形成してもよい。   Next, as shown in FIG. 17, a plurality of grooves 13 having a rectangular cross section are formed so as to reach the n-type pillar layer 5. Here, the plurality of grooves 13 are formed so as to have the same pitch. For example, the RIE (Reactive Ion Etching) method is used to form the groove 13. In that case, RIE post-treatment is performed for the purpose of removing damage and surface contamination occurring in the p-type pillar layer 2 and the n-type pillar layer 5. Here, the width of the trench 13 which is the lateral width of the trench gate is formed to be equal to the lateral width of the n-type pillar layer 5, but the width of the trench 13 is formed to be wider or narrower than the lateral width of the n-type pillar layer 5. Also good.

なお、これ以降、周知の技術を用いてトレンチゲート形成、ｎ型ソース形成、層間膜形成、電極形成などが行われパワーＭＯＳＦＥＴ７１が完成する。   Thereafter, trench gate formation, n-type source formation, interlayer film formation, electrode formation, and the like are performed using well-known techniques to complete the power MOSFET 71.

ここで、本実施例のトレンチゲートパワーＭＯＳＦＥＴ７１と実施例１のプレーナ型パワーＭＯＳＦＥＴ７０を比較すると、パワーＭＯＳＦＥＴ７１ではｐ型ベース層３とゲート電極９の位置合わせズレが発生しない。このため、チャネル長のバラツキを抑制することができる。また、ｐ型ベース層３を浅く形成することが可能となり、チャネル長を短くし、チャネル抵抗を小さくすることができる。   Here, when the trench gate power MOSFET 71 of the present embodiment is compared with the planar power MOSFET 70 of the first embodiment, there is no misalignment between the p-type base layer 3 and the gate electrode 9 in the power MOSFET 71. For this reason, variation in channel length can be suppressed. Further, the p-type base layer 3 can be formed shallowly, the channel length can be shortened, and the channel resistance can be reduced.

上述したように、本実施例の半導体素子では、ｐ型ピラー層２とｎ型ピラー層５がｎ＋型基板１上に交互に周期的に形成され、スーパージャンクション構造となるピラー層が設けられる。ｐ型ピラー層２上には、シリコンエピタキシャル法により、深さ方向の９０％までの領域が一定な不純物濃度を有するｐ型ベース層３が設けられる。ｎピラー層５上と、ｐ型ベース層３の側面とには、ゲート絶縁膜８を介してゲート電極９が基板に埋設される。ｐ型ベース層３の上部の両側面部には、ｎ型ソース層４が設けられる。 As described above, in the semiconductor element of this embodiment, the p-type pillar layer 2 and the n-type pillar layer 5 are alternately and periodically formed on the n + -type substrate 1 to provide a pillar layer having a super junction structure. . On the p-type pillar layer 2, a p-type base layer 3 having a constant impurity concentration in a region up to 90% in the depth direction is provided by a silicon epitaxial method. A gate electrode 9 is embedded in the substrate via the gate insulating film 8 on the n pillar layer 5 and the side surface of the p-type base layer 3. An n-type source layer 4 is provided on both side surfaces of the upper portion of the p-type base layer 3.

このため、パワーＭＯＳＦＥＴ７１では、横方向のピッチを縮小化した場合でも、高温熱拡散によって発生するｐ型ピラー層２とｎ型ピラー層５の不純物濃度の打ち消しあいによる実効ピラー濃度の低下が抑制される。したがって、実効的な不純物濃度の低下を抑制でき、パワーＭＯＳＦＥＴ７１の高耐圧化を図りながら、オン抵抗の低下を達成することができる。また、ｐ型ベース層３とゲート電極９の位置合わせズレが発生しないのでチャネル長のバラツキを抑制することができる。更に、ｐ型ベース層３を浅く形成することが可能となり、チャネル長を短くし、チャネル抵抗を小さくすることができる。   Therefore, in the power MOSFET 71, even when the lateral pitch is reduced, a reduction in effective pillar concentration due to cancellation of impurity concentrations of the p-type pillar layer 2 and the n-type pillar layer 5 caused by high-temperature thermal diffusion is suppressed. The Therefore, it is possible to suppress a reduction in effective impurity concentration, and to achieve a reduction in on-resistance while increasing the breakdown voltage of the power MOSFET 71. Further, since there is no misalignment between the p-type base layer 3 and the gate electrode 9, variations in channel length can be suppressed. Furthermore, the p-type base layer 3 can be formed shallowly, the channel length can be shortened, and the channel resistance can be reduced.

なお、本実施例では、Ｎｃｈ型のスーパージャンクション構造を有するトレンチゲートパワーＭＯＳＦＥＴ７０に適用しているが、Ｐｃｈ型のスーパージャンクション構造を有するトレンチゲートパワーＭＯＳＦＥＴにも適用することができる。また、ゲート電極９の上部をｐ型ベース層３よりも高く形成しているが、ゲート電極９の上端をｐ型ベース層３と同じ高さに形成、或いはゲート電極をｐ型ベース層３よりも低く形成してもよい。   In this embodiment, the present invention is applied to the trench gate power MOSFET 70 having an Nch type super junction structure, but can also be applied to a trench gate power MOSFET having a Pch type super junction structure. Moreover, although the upper part of the gate electrode 9 is formed higher than the p-type base layer 3, the upper end of the gate electrode 9 is formed at the same height as the p-type base layer 3, or the gate electrode is formed higher than the p-type base layer 3. May be formed low.

次に、本発明の実施例３に係る半導体素子について、図面を参照して説明する。図１８は半導体素子としてのパワーＭＯＳＦＥＴを示す断面図である。本実施例では、パワーＭＯＳＦＥＴのベース層、ソース層、及びドリフト層を高不純物濃度化している。   Next, a semiconductor element according to Example 3 of the present invention will be described with reference to the drawings. FIG. 18 is a cross-sectional view showing a power MOSFET as a semiconductor element. In this embodiment, the base layer, the source layer, and the drift layer of the power MOSFET are increased in impurity concentration.

以下、実施例１と同一構成部分には、同一符号を付してその部分の説明を省略し、異なる部分のみ説明する。   In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

図１８に示すように、縦型パワーＭＯＳＦＥＴであるパワーＭＯＳＦＥＴ７２は、ｐ型ピラー層２とｎ型ピラー層５がドレイン層としてのｎ＋型基板１上の図中横方向に交互に周期的に形成されるピラー層を有する（スーパージャンクション構造）。また、ベース層、ソース層、及びドリフト層を高不純物濃度化している。 As shown in FIG. 18, a power MOSFET 72 which is a vertical power MOSFET has a p-type pillar layer 2 and an n-type pillar layer 5 alternately and periodically in the horizontal direction in the figure on an n + -type substrate 1 as a drain layer. It has a pillar layer to be formed (super junction structure). In addition, the impurity concentration of the base layer, the source layer, and the drift layer is increased.

ｐ型ピラー層２上と、ｐ型ピラー層２と接するｎ型ピラー層５の上端部上にはｐ＋型ベース層３１が設けられる。ｎ型ピラー層５の上部の中央部上には、ｎ＋ドリフト層３２が設けられる。ｎ＋ドリフト層３２上と、ｎ＋ドリフト層３２に隣接するｐ＋型ベース層３１の上端部上には、ゲート絶縁膜８を介して制御電極としてのゲート電極９が設けられる。ゲート電極９は、側面及び上面部分が絶縁膜１０により分離される。ゲート電極９の両端部直下のｐ＋型ベース層３１の表面には、ｎ＋型ソース層３３が設けられる。ｎ＋型ソース層３３と隣接配置される他のゲート電極９に設けられるｎ＋型ソース層３３の間には、ｐ＋型ベース層３１が残置される。ｐ＋型ベース層３１、ｎ＋型ソース層３３、及び絶縁膜１０上には、ｐ＋型ベース層３１及びｎ＋型ソース層３３と電気的に接続される第２電極としてのソース電極７が設けられる。 A p + -type base layer 31 is provided on the p-type pillar layer 2 and on the upper end portion of the n-type pillar layer 5 in contact with the p-type pillar layer 2. An n + drift layer 32 is provided on the central portion of the upper part of the n-type pillar layer 5. n + a drift layer 32 above the upper end portion of the p + -type base layer 31 adjacent to the n + drift layer 32, the gate electrode 9 as a control electrode via a gate insulating film 8 is provided. The gate electrode 9 has a side surface and an upper surface portion separated by an insulating film 10. An n + -type source layer 33 is provided on the surface of the p + -type base layer 31 immediately below both ends of the gate electrode 9. Between the n + -type source layer 33 and is provided in addition to the gate electrode 9 disposed adjacent n + -type source layer 33, p + -type base layer 31 is left. On the p + type base layer 31, the n + type source layer 33, and the insulating film 10, a source electrode 7 as a second electrode that is electrically connected to the p + type base layer 31 and the n + type source layer 33. Is provided.

ここで、ｐ＋型ベース層３１は実施例１のｐ型ベース層３よりもｐ型不純物が高濃度にドープされる。ｎ＋ドリフト層３２は実施例１のｎ型ピラー層５の上部領域に相当し、ｎ型不純物がｎ型ピラー層５よりも高濃度にドープされる。ｎ＋型ソース層３３は実施例１のｎ型ソース層４よりもｎ型不純物が高濃度にドープされる。 Here, the p + type base layer 31 is doped with a higher concentration of p type impurities than the p type base layer 3 of the first embodiment. The n + drift layer 32 corresponds to the upper region of the n-type pillar layer 5 of the first embodiment, and the n-type impurity is doped at a higher concentration than the n-type pillar layer 5. The n + type source layer 33 is doped with an n type impurity at a higher concentration than the n type source layer 4 of the first embodiment.

次に、パワーＭＯＳＦＥＴの製造方法について図１９乃至図２１を参照して説明する。図１９乃至図２１はパワーＭＯＳＦＥＴの製造工程を示す断面図である。   Next, a method for manufacturing a power MOSFET will be described with reference to FIGS. 19 to 21 are cross-sectional views showing the manufacturing process of the power MOSFET.

図１９に示すように、シリコンエピタキシャル成長法により、ｐ型ピラー層２及びｎ型ピラー層５上にｎ＋ドリフト層３２を形成する。ここで、ｎ＋ドリフト層３２の形成は、ｎ＋ドリフト層３２中の高濃度の不純物がｐ型ピラー層２及びｎ型ピラー層５に拡散されにくい比較的低温度のエピタキシャル成長条件を用いるのが好ましい。 As shown in FIG. 19, an n + drift layer 32 is formed on the p-type pillar layer 2 and the n-type pillar layer 5 by a silicon epitaxial growth method. Here, formation of the n + drift layer 32, a high concentration of impurities in n + drift layer 32 is to use epitaxial growth conditions of a relatively low temperature less likely to be diffused into the p-type pillar layer 2 and the n-type pillar layer 5 preferable.

次に、図２０に示すように、ｐ型ピラー層２上部のｎ＋ドリフト層３２と、ｎ型ピラー層５の上端部のｎ＋ドリフト層３２とをエッチングして断面が矩形型形状を有する複数の溝１４を形成する。ここで、ピッチが同一になるように複数の溝１４が形成される。溝１４の形成は、例えばＲＩＥ（Reactive Ion Etching）法を用いる。その場合、ｐ型ピラー層２、ｎ型ピラー層５、及びｎ＋ドリフト層３２に発生するダメージや表面汚染を除去する目的でＲＩＥ後処理が行われる。 Next, as shown in FIG. 20, the p-type pillar layer 2 the upper portion of the n + drift layer 32, is etched and n + drift layer 32 of the upper portion of the n-type pillar layer 5 is cross-sectional has a rectangular shape A plurality of grooves 14 are formed. Here, the plurality of grooves 14 are formed so as to have the same pitch. For example, the RIE (Reactive Ion Etching) method is used to form the groove 14. In that case, RIE post-treatment is performed for the purpose of removing damage and surface contamination generated in the p-type pillar layer 2, the n-type pillar layer 5, and the n + drift layer 32.

続いて、図２１に示すように、選択エピタキシャル成長（ＳＥＧ：Selective Epitaxial Growth）により、溝１４の部分にｐ＋型ベース層３１を埋設する。ｐ＋型ベース層３１の形成は、ｎ＋ドリフト層３２上に絶縁膜を形成し、例えば、選択エピタキシャル成長（ＳＥＧ：Selective Epitaxial Growth）により形成する。その後、絶縁膜、ｎ＋ドリフト層３２、及びｐ＋型ベース層３１を、例えばＣＭＰ（Chemical Mechanical Polishing）法を用いて研磨し、平坦化する。 Subsequently, as shown in FIG. 21, a p + -type base layer 31 is embedded in the groove 14 by selective epitaxial growth (SEG). The p + -type base layer 31 is formed by forming an insulating film on the n + drift layer 32, for example, by selective epitaxial growth (SEG). Thereafter, the insulating film, the n + drift layer 32, and the p + type base layer 31 are polished and planarized using, for example, a CMP (Chemical Mechanical Polishing) method.

そして、ｐ＋型ベース層３１及びｎ＋ドリフト層３２上にゲート絶縁膜８とゲート電極９を積層形成し、レジスト膜をマスクとして、例えばＲＩＥ（Reactive Ion Etching）法によりゲート電極９とゲート絶縁膜８をエッチングする。その後、レジスト膜の除去及びＲＩＥ後処理する。 Then, the gate insulating film 8 and the gate electrode 9 are laminated on the p + type base layer 31 and the n + drift layer 32, and the gate electrode 9 and the gate insulating film are insulated by, for example, RIE (Reactive Ion Etching) using the resist film as a mask. The film 8 is etched. Thereafter, the resist film is removed and post-RIE processing is performed.

続いて、レジスト膜をマスクとして、ｐ＋型ベース層３１の表面にｎ型不純物をイオン注入する。レジスト膜を除去後、このイオン注入層を熱処理により活性化させてｎ＋型ソース層３３を形成する。 Subsequently, n-type impurities are ion-implanted into the surface of the p + -type base layer 31 using the resist film as a mask. After removing the resist film, the ion-implanted layer is activated by heat treatment to form the n + -type source layer 33.

なお、これ以降、周知の技術を用いて層間膜形成、電極形成などが行われパワーＭＯＳＦＥＴ７２が完成する。   Thereafter, interlayer film formation, electrode formation, and the like are performed using well-known techniques, and the power MOSFET 72 is completed.

上述したように、本実施例の半導体素子では、ｐ型ピラー層２とｎ型ピラー層５がｎ＋型基板１上に交互に周期的に形成され、スーパージャンクション構造となるピラー層が設けられる。ｐ型ピラー層２上と、ｐ型ピラー層２と接するｎ型ピラー層５の上側面部分には、シリコンエピタキシャル法により、深さ方向の９０％までの領域が一定な不純物濃度を有するｐ＋型ベース層３１が設けられる。ｎ型ピラー層５の中央部上には、シリコンエピタキシャル法により、ｎ＋型ドリフト層３２が設けられる。ｐ＋型ベース層３１とｎ＋型ドリフト層３２上には、ゲート絶縁膜８を介してゲート電極９が設けられる。ゲート電極９は、側面及び上面部分が絶縁膜１０により分離される。ゲート電極９の両端部直下のｐ＋型ベース層３１の表面には、ｎ＋型ソース層３３が設けられる。 As described above, in the semiconductor element of this embodiment, the p-type pillar layer 2 and the n-type pillar layer 5 are alternately and periodically formed on the n + -type substrate 1 to provide a pillar layer having a super junction structure. . On the p-type pillar layer 2 and the upper side surface portion of the n-type pillar layer 5 in contact with the p-type pillar layer 2, p + having a constant impurity concentration in a region up to 90% in the depth direction by silicon epitaxial method. A mold base layer 31 is provided. On the central portion of the n-type pillar layer 5, an n + -type drift layer 32 is provided by a silicon epitaxial method. A gate electrode 9 is provided on the p + type base layer 31 and the n + type drift layer 32 with a gate insulating film 8 interposed therebetween. The gate electrode 9 has a side surface and an upper surface portion separated by an insulating film 10. An n + -type source layer 33 is provided on the surface of the p + -type base layer 31 immediately below both ends of the gate electrode 9.

このため、実施例１と同様な効果を有する。したがって、実効的な不純物濃度の低下を抑制でき、パワーＭＯＳＦＥＴ７２の高耐圧化を図りながら、低オン抵抗化を達成することができる。   For this reason, it has the same effect as Example 1. Therefore, a reduction in effective impurity concentration can be suppressed, and a low on-resistance can be achieved while increasing the breakdown voltage of the power MOSFET 72.

次に、本発明の実施例４に係る半導体素子について、図面を参照して説明する。図２２は半導体素子としてのパワーＭＯＳＦＥＴを示す断面図である。本実施例では、パワーＭＯＳＦＥＴの終端部にｐ型ガードリング層及びｐ型リサーフ層を設けている。   Next, a semiconductor element according to Example 4 of the present invention will be described with reference to the drawings. FIG. 22 is a cross-sectional view showing a power MOSFET as a semiconductor element. In this embodiment, a p-type guard ring layer and a p-type RESURF layer are provided at the terminal portion of the power MOSFET.

以下、実施例１と同一構成部分には、同一符号を付してその部分の説明を省略し、異なる部分のみ説明する。   In the following, the same components as those in the first embodiment are denoted by the same reference numerals, and the description thereof is omitted, and only different portions are described.

図２２に示すように、縦型パワーＭＯＳＦＥＴであるパワーＭＯＳＦＥＴ７３の終端部には、ｎ−層２１上に、ｐ型ベース層３の側面及びｐ型ピラー層２の上部側面と接し、ｐ型ベース層３よりも深いｐ型ガードリング層４１がｐ型ベース層３の最外周端に沿って設けられる。ｐ型ガードリング層４１の外周には、ｎ−層２１上に、ｐ型ガードリング層４１の側面と接し、ｐ型ガードリング層４１よりも浅く、幅広なｐ型リサーフ層４２が設けられる。ｐ型リサーフ層４２はソース電極７と電気的に接続される。ｐ型ガードリング層４１は、ｐ型ピラー層２及びｎ型ピラー層５よりも先に形成される。 As shown in FIG. 22, the end portion of the power MOSFET 73 that is a vertical power MOSFET is in contact with the side surface of the p-type base layer 3 and the upper side surface of the p-type pillar layer 2 on the n − layer 21. A p-type guard ring layer 41 deeper than the layer 3 is provided along the outermost peripheral edge of the p-type base layer 3. On the outer periphery of the p-type guard ring layer 41, a wide p-type RESURF layer 42 that is in contact with the side surface of the p-type guard ring layer 41 and shallower than the p-type guard ring layer 41 is provided on the n − layer 21. The p-type RESURF layer 42 is electrically connected to the source electrode 7. The p-type guard ring layer 41 is formed before the p-type pillar layer 2 and the n-type pillar layer 5.

ここで、ｐ型ガードリング層４１及びｐ型リサーフ層４２を設けることにより、横方向に空乏層が伸び、ｐ型ベース層３の端部での電界集中が緩和され、高耐圧のパワーＭＯＳＦＥＴを実現することができる。なお、ｐ型ガードリング層４１及びｐ型リサーフ層４２の直下部分と、ｐ型リサーフ層４２よりも外周部のｎ−層２１部とをｐ型ピラー層２及びｎ型ピラー層５が交互に繰り返し形成されるスーパージャンクション構造にしてもよい。 Here, by providing the p-type guard ring layer 41 and the p-type RESURF layer 42, the depletion layer extends in the lateral direction, the electric field concentration at the end of the p-type base layer 3 is reduced, and a high breakdown voltage power MOSFET is formed. Can be realized. In addition, the p-type pillar layer 2 and the n-type pillar layer 5 are alternately arranged between the portion immediately below the p-type guard ring layer 41 and the p-type RESURF layer 42 and the n − layer 21 portion at the outer peripheral portion than the p-type RESURF layer 42. A super junction structure formed repeatedly may be used.

上述したように、本実施例の半導体素子では、終端部のｎ−層２１上に、ｐ型ベース層３の側面及びｐ型ピラー層２の上部側面と接し、ｐ型ベース層３よりも深いｐ型ガードリング層４１がｐ型ベース層３の最外周端に沿って設けられる。ｐ型ガードリング層４１の外周には、ｎ−層２１上に、ｐ型ガードリング層４１の側面と接し、ｐ型ガードリング層４１よりも浅く、幅広なｐ型リサーフ層４２が設けられる。 As described above, in the semiconductor element of this example, the side surface of the p-type base layer 3 and the upper side surface of the p-type pillar layer 2 are in contact with the upper surface of the p-type base layer 3 on the n − layer 21 at the termination portion. A p-type guard ring layer 41 is provided along the outermost periphery of the p-type base layer 3. On the outer periphery of the p-type guard ring layer 41, a wide p-type RESURF layer 42 that is in contact with the side surface of the p-type guard ring layer 41 and shallower than the p-type guard ring layer 41 is provided on the n − layer 21.

このため、ｐ型ガードリング層４１及びｐ型リサーフ層４２により、横方向に空乏層が伸び、ｐ型ベース層３の端部での電界集中が緩和され、低オン抵抗を有する高耐圧のパワーＭＯＳＦＥＴ７３を実現することができる。   For this reason, the p-type guard ring layer 41 and the p-type RESURF layer 42 extend the depletion layer in the lateral direction, the electric field concentration at the end of the p-type base layer 3 is relaxed, and a high withstand voltage power having a low on-resistance. MOSFET 73 can be realized.

本発明は、上記実施例に限定されるものではなく、発明の趣旨を逸脱しない範囲で、種々、変更してもよい。   The present invention is not limited to the above-described embodiments, and various modifications may be made without departing from the spirit of the invention.

例えば、実施例ではシリコン（Ｓｉ）を用いたＭＯＳＦＥＴに適用しているが、シリコンカーバイド（ＳｉＣ）や窒化ガリウム（ＧａＮ）などの化合物半導体、或いはダイヤモンドなどのワイドバンドギャップを有する半導体に適用することができる。また、スーパージャンクション構造を有するＳＢＤ、ＳＩＴ、ＩＧＢＴなどにも適用することができる。   For example, although the embodiment is applied to a MOSFET using silicon (Si), it is applied to a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN), or a semiconductor having a wide band gap such as diamond. Can do. Further, the present invention can also be applied to SBD, SIT, IGBT and the like having a super junction structure.

本発明は、以下の付記に記載されているような構成が考えられる。
（付記１） 第１導電型の半導体基板と、前記半導体基板上に設けられ、断面が短冊状の第１導電型の第１半導体ピラー層と第２導電型の第２半導体ピラー層とが前記半導体基板の表面に沿って横方向に交互に形成されるピラー層と、前記半導体基板に電気的に接続される第１の主電極と、前記第２半導体ピラー層の表面に設けられる第２導電型の半導体ベース層と、前記半導体ベース層の表面に設けられる第１導電型の半導体層と、前記半導体ベース層と前記半導体層に接するように設けられる第２の主電極と、前記半導体層と前記第１半導体ピラー層に亘る領域にゲート絶縁膜を介して設けられる制御電極とを具備し、前記半導体層と前記第１半導体ピラー層の間に縦方向にチャネルが形成され、前記半導体ベース層は横方向及び縦方向の不純物プロファイルが一定な領域を有することを特徴とする半導体素子。 The present invention can be configured as described in the following supplementary notes.
(Supplementary Note 1) A first conductivity type semiconductor substrate, a first conductivity type first semiconductor pillar layer and a second conductivity type second semiconductor pillar layer which are provided on the semiconductor substrate and have a strip-like cross section. Pillar layers alternately formed in the lateral direction along the surface of the semiconductor substrate, a first main electrode electrically connected to the semiconductor substrate, and a second conductive provided on the surface of the second semiconductor pillar layer Type semiconductor base layer, a first conductive type semiconductor layer provided on the surface of the semiconductor base layer, a second main electrode provided in contact with the semiconductor base layer and the semiconductor layer, and the semiconductor layer, A control electrode provided through a gate insulating film in a region extending over the first semiconductor pillar layer, wherein a channel is formed in a vertical direction between the semiconductor layer and the first semiconductor pillar layer, and the semiconductor base layer Is horizontal and vertical A semiconductor element having a region having a constant impurity profile.

（付記２） 前記半導体ベース層のプロファイルは複数のピークを有し、前記半導体ベース層の表面から深さの（１／２）までの間でのピーク濃度が前記半導体ベース層表面の濃度の９０％以上である付記１に記載の半導体素子。 (Supplementary Note 2) The profile of the semiconductor base layer has a plurality of peaks, and the peak concentration from the surface of the semiconductor base layer to (1/2) of the depth is 90% of the concentration of the surface of the semiconductor base layer. The semiconductor element according to appendix 1, which is at least%.

（付記３） バレー濃度がピーク濃度の１０％以上である付記２に記載の半導体素子。 (Additional remark 3) The semiconductor element of Additional remark 2 whose valley concentration is 10% or more of peak concentration.

（付記４） 前記半導体ベース層の深さは、前記半導体ベース層に隣接配置される素子終端部のガードリング層の深さよりも浅い付記１乃至３のいずれかに記載の半導体素子。 (Additional remark 4) The semiconductor element in any one of additional remark 1 thru | or 3 with which the depth of the said semiconductor base layer is shallower than the depth of the guard ring layer of the element termination part arrange | positioned adjacent to the said semiconductor base layer.

本発明の実施例１に係るパワーＭＯＳＦＥＴを示す断面図。Sectional drawing which shows power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴのベース層の不純物プロファイルを示す図。The figure which shows the impurity profile of the base layer of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係る実効ピラー濃度と拡散長の関係を示す図。The figure which shows the relationship between the effective pillar density | concentration and diffusion length which concern on Example 1 of this invention. 本発明の実施例１に係る高加速イオン注入法を用いた場合のベース層の不純物プロファイルを示す図。The figure which shows the impurity profile of the base layer at the time of using the high acceleration ion implantation method which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの終端部を示す断面図。Sectional drawing which shows the termination | terminus part of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例１に係るパワーＭＯＳＦＥＴの終端部の製造工程を示す断面図。Sectional drawing which shows the manufacturing process of the termination | terminus part of power MOSFET which concerns on Example 1 of this invention. 本発明の実施例２に係るパワーＭＯＳＦＥＴを示す断面図。Sectional drawing which shows power MOSFET which concerns on Example 2 of this invention. 本発明の実施例２に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 2 of this invention. 本発明の実施例２に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 2 of this invention. 本発明の実施例３に係るパワーＭＯＳＦＥＴを示す断面図。Sectional drawing which shows power MOSFET which concerns on Example 3 of this invention. 本発明の実施例３に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 3 of this invention. 本発明の実施例３に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 3 of this invention. 本発明の実施例３に係るパワーＭＯＳＦＥＴの製造工程を示す断面図。Sectional drawing which shows the manufacturing process of power MOSFET which concerns on Example 3 of this invention. 本発明の実施例４に係るパワーＭＯＳＦＥＴを示す断面図。Sectional drawing which shows power MOSFET which concerns on Example 4 of this invention.

符号の説明Explanation of symbols

１ ｎ＋型基板
２ ｐ型ピラー層
３ ｐ型ベース層
４ ｎ型ソース層
５ ｎ型ピラー層
６ ドレイン電極
７ ソース電極
８ ゲート絶縁膜
９ ゲート電極
１０、２３ 絶縁膜
１１〜１４ 溝
２１ ｎ−層
２２ ｐ型ガードリング層
２４ ガードリング電極
３１ ｐ＋型ベース層
３２ ｎ＋型ドリフト層
３３ ｎ＋型ソース層
４１ ｐ型ガードリング層
４２ ｐ型リサーフ層
７０〜７３ パワーＭＯＳＦＥＴ 1 n + type substrate 2 p-type pillar layer 3 p-type base layer 4 n-type source layer 5 n-type pillar layer 6 drain electrode 7 source electrode 8 gate insulating film 9 gate electrodes 10 and 23 insulating films 11 to 14 groove 21 n − Layer 22 p-type guard ring layer 24 guard ring electrode 31 p + -type base layer 32 n + -type drift layer 33 n + -type source layer 41 p-type guard ring layer 42 p-type resurf layers 70 to 73 Power MOSFET

Claims (5)

第１導電型の半導体基板と、
前記半導体基板上に設けられ、断面が短冊状の第１導電型の第１半導体ピラー層と第２導電型の第２半導体ピラー層とが前記半導体基板の表面に沿って横方向に交互に形成されるピラー層と、
前記半導体基板に電気的に接続される第１の主電極と、
前記第２半導体ピラー層の表面に設けられる第２導電型の半導体ベース層と、
前記半導体ベース層の表面に設けられる第１導電型の半導体層と、
前記半導体ベース層と前記半導体層に接するように設けられる第２の主電極と、
前記半導体層と前記第１半導体ピラー層に亘る領域にゲート絶縁膜を介して設けられる制御電極と、
を具備し、前記半導体ベース層は横方向及び縦方向の不純物プロファイルが一定な領域を有することを特徴とする半導体素子。 A first conductivity type semiconductor substrate;
A first conductive type first semiconductor pillar layer and a second conductive type second semiconductor pillar layer which are provided on the semiconductor substrate and have a strip-like cross section are alternately formed in the lateral direction along the surface of the semiconductor substrate. With pillar layer
A first main electrode electrically connected to the semiconductor substrate;
A second conductivity type semiconductor base layer provided on a surface of the second semiconductor pillar layer;
A first conductivity type semiconductor layer provided on a surface of the semiconductor base layer;
A second main electrode provided in contact with the semiconductor base layer and the semiconductor layer;
A control electrode provided via a gate insulating film in a region extending between the semiconductor layer and the first semiconductor pillar layer;
The semiconductor base layer has a region having a constant impurity profile in the horizontal direction and the vertical direction. 前記第１半導体ピラー層の濃度と前記第２半導体ピラー層の濃度に対して、実効ピラー濃度が５０％以上となる領域が前記第１半導体ピラー層及び前記第２半導体ピラー層に設けられることを特徴とする請求項１に記載の半導体素子。   A region having an effective pillar concentration of 50% or more with respect to the concentration of the first semiconductor pillar layer and the concentration of the second semiconductor pillar layer is provided in the first semiconductor pillar layer and the second semiconductor pillar layer. The semiconductor device according to claim 1, wherein 前記半導体ベース層の表面から深さの（１／２）までの濃度が、前記半導体ベース表面の濃度の９０％以上であることを特徴とする請求項１又は２に記載の半導体素子。   3. The semiconductor element according to claim 1, wherein a concentration from a surface of the semiconductor base layer to (1/2) of a depth is 90% or more of a concentration of the surface of the semiconductor base. 前記半導体ベース層は、互いに異なるピークを有するプロファイルが複数設けられることを特徴とする請求項１乃至３のいずれか１項に記載の半導体素子。   4. The semiconductor device according to claim 1, wherein the semiconductor base layer is provided with a plurality of profiles having different peaks. 5. 前記半導体ベース層の表面から深さの（１／２）までの間での複数のピーク濃度が、それぞれ前記半導体ベース層表面の濃度の９０％以上であることを特徴とする請求項４に記載の半導体素子。   The plurality of peak concentrations from the surface of the semiconductor base layer to (1/2) of the depth are 90% or more of the concentration of the surface of the semiconductor base layer, respectively. Semiconductor element.
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