JP2007019146A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which has high breakdown voltage and a super-junction structure with low on-state resistance. <P>SOLUTION: The MOSFET has a super-junction structure wherein a first n-type pillar layer 13, a p-type pillar layer 14, and an n-type pillar layer 15 are periodically and alternately placed on an n<SP>+</SP>-type drain layer 12. The pillar layers 14 and 15 are higher in impurity concentration on the side of a source electrode 20 than the side of a drain electrode 11. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device, and more particularly to a semiconductor device having a super junction structure in which p-type pillar layers and n-type pillar layers are alternately buried in a drift layer in a lateral direction.

  The on-resistance of the vertical power MOSFET greatly depends on the electric resistance of the conductive layer (drift layer) portion. The electrical resistance of the drift layer is determined by the impurity concentration. If the impurity concentration is increased, the on-resistance can be lowered. However, since the breakdown voltage of the PN junction formed by the drift layer and the base layer decreases as the impurity concentration increases, the impurity concentration cannot be increased beyond the limit determined according to the breakdown voltage. Thus, there is a trade-off relationship between element breakdown voltage and on-resistance. Improving this trade-off is an important issue when trying to provide a semiconductor device with low power consumption. This trade-off has a limit determined by the element material, and exceeding this limit is the way to realizing a low on-resistance semiconductor element.

  As an example of a MOSFET that solves this problem, a structure is known in which a p-type pillar layer and an n-type pillar layer called a super junction structure are alternately embedded in a drift layer in a lateral direction (see, for example, Patent Document 1). The super junction structure makes the charge amount (impurity amount) contained in the p-type pillar layer and the n-type pillar layer the same, thereby creating a pseudo non-doped layer, maintaining a high breakdown voltage, and highly doped n-type. By passing a current through the pillar layer, a low on-resistance exceeding the material limit is realized.

  By using the super junction structure in this way, it is possible to realize an on-resistance / withstand voltage trade-off that exceeds the material limit. To improve this trade-off, that is, to reduce the on-resistance, super junction It is necessary to narrow the lateral period of the structure. Since the super junction structure is easily depleted by shortening the horizontal period, the p / n pillar concentration can be increased. As a result, the on-resistance can be reduced.

  As a method of forming a super junction structure having a narrow lateral period, for example, a method of forming a trench in an n-type semiconductor layer and then embedding a p-type semiconductor layer in the trench by crystal growth is known. As a method for realizing a narrower period, after forming a trench, a p-type pillar is formed on the trench sidewall by ion implantation from an oblique direction into the trench sidewall, and then an n-type semiconductor layer is crystal-grown in the trench Is disclosed in Patent Document 2. By using this method, the cycle can be halved compared to the case where ion implantation from an oblique direction is not performed.

However, in the case of the method of burying the semiconductor layer in the trench by crystal growth in this way, the n-type semiconductor layer by the burying has a high impurity concentration on the surface side and a low impurity concentration on the bottom surface side. Such distribution reduces the maximum breakdown voltage of the semiconductor element. Further, such a distribution causes a decrease in the maximum breakdown voltage when a charge imbalance occurs between adjacent pillar layers.
JP 2003-273355 A JP 2002-368216 A

  An object of the present invention is to provide a semiconductor device having a super junction structure with high breakdown voltage and low on-resistance.

  A semiconductor element according to one embodiment of the present invention includes a first conductivity type first semiconductor layer, a first conductivity type first semiconductor pillar layer, and a second conductivity type second semiconductor pillar layer over the first semiconductor layer. And pillar layers formed by alternately arranging first conductive type third semiconductor pillar layers, a first main electrode electrically connected to the first semiconductor layer, and the second semiconductor pillar. A second conductivity type semiconductor base layer selectively formed on the surface of the layer; a first conductivity type semiconductor diffusion layer selectively formed on the surface of the semiconductor base layer; and the semiconductor base layer and semiconductor diffusion A second main electrode formed so as to be bonded to the layer, and a control electrode formed on the semiconductor base layer, the semiconductor diffusion layer, and the first semiconductor pillar layer via an insulating film, The second and third semiconductor pillar layers are closer to the first main electrode than the first main electrode side. Serial towards the side of the second main electrode, characterized in that it is formed to have an impurity concentration distribution high impurity concentration.

  According to the present invention, it is possible to provide a semiconductor element having a super junction structure having a high breakdown voltage and a low on-resistance.

  Next, embodiments of the present invention will be described in detail with reference to the drawings. In the following embodiments, the first conductivity type is n-type and the second conductivity type is p-type.

  First Embodiment FIG. 1 is a cross-sectional view schematically showing a configuration of a power MOSFET according to a first embodiment of the present invention. In this MOSFET, a pillar layer in which a first n-type pillar layer 13, a p-type pillar layer 14, and a second n-type pillar layer 15 are alternately and periodically formed in a lateral direction on an n + -type drain layer 12. Is formed. Each pillar layer 13-15 shall have a stripe shape extended in a paper surface orthogonal direction here. However, instead of the stripe shape, for example, the pillar layers 13 to 15 may be replaced with ones that are formed in a lattice shape or a zigzag shape in a cross section along the surface of the n + -type drain layer 12. A drain electrode 11 is formed on the back surface of the n + type drain layer 12.

  A p-type base layer 16 is formed on the surface of the p-type pillar layer 14, and n-type source diffusion layers 17 are selectively formed in a stripe shape on the surface of the p-type base layer 16. . Further, from the p-type base layer 16 and the n-type source diffusion layer 17 to another adjacent p-type base layer 16 and n-type source diffusion layer 17 via the first n-type pillar layer 13 or the second n-type pillar layer 15. On the region, a gate electrode 19 is formed in a stripe shape via a gate insulating film 18 made of, for example, a silicon oxide film having a thickness of about 0.1 μm. Further, the source electrode 20 is formed in a stripe shape so as to be in contact with the p-type base layer 16 and the n-type source diffusion layer 17.

  Since the first n-type pillar layer 13 is formed by crystal growth over the entire surface of the n + -type drain layer 12 as will be described later, as shown by a straight line aa ′ in the graph on the right side of FIG. The concentration distribution in the direction is constant. On the other hand, since the second n-type pillar layer 15 is formed by being embedded in a narrow trench by crystal growth, the impurity concentration is formed on the source electrode 20 side as indicated by a two-dot chain line cc ′ in the graph of FIG. The impurity concentration is such that the concentration decreases toward the drain electrode 11. What is characteristic in this embodiment is that, similarly to the second n-type pillar layer 15, the p-type pillar layer 14 also has a high impurity concentration on the source electrode 20 side, and the impurity concentration increases toward the drain electrode 11. It has a distribution that becomes lower. Since the p-type pillar layer 14 has such a distribution, the balance of the impurity amount can be maintained in the depth direction, and the maximum breakdown voltage of the power MOSFET can be maintained high.

  Consider a case where the impurity concentration distribution in the depth direction of the p-type pillar layer 14 is constant in a situation where the concentration of the n-type pillar layers 13 and 15 has an impurity concentration distribution as shown in the graph of FIG. . In this case, even if the total amount of impurities in the entire super junction structure is made equal, the n-type impurity concentration is higher than the p-type impurity concentration on the surface side (source electrode 20 side). Conversely, on the bottom surface side (drain electrode 11 side), the n-type (donor) impurity concentration is lower than the p-type (acceptor) impurity concentration. That is, the balance of the amount of impurities changes in the depth direction. Then, a flat distribution, which is an electric field distribution of an ideal super junction structure, cannot be obtained, and the electric field tends to concentrate at the upper and lower ends of the super junction structure, thereby decreasing the breakdown voltage.

  In order to suppress such a decrease in breakdown voltage, in this embodiment, the impurity concentration of the p-type pillar layer 14 is high on the source electrode 20 side as in the second n-type pillar layer 15, and the drain electrode 11 The distribution is such that the impurity concentration decreases as it goes. Preferably, the impurity concentration of the p-type pillar layer 14 at each depth position is equal to the average of the impurity concentration of the first n-type pillar layer 13 and the impurity concentration of the second n-type pillar layer 15 at the same depth position. To be. Thereby, the balance of the impurity amount does not change in the depth direction, a flat electric field distribution can be realized, and a decrease in breakdown voltage can be suppressed. Furthermore, when the balance of the impurity amount of the p / n pillar layer in the depth direction is constant, as shown in FIG. 2, it is possible to suppress a decrease in breakdown voltage when the impurity concentration varies in the lateral direction, that is, when charge imbalance occurs. it can.

  Next, an example of the manufacturing process of the power MOSFET of this embodiment will be described with reference to FIGS. First, as shown in FIG. 3, an n-type layer 13 ′ that becomes the first n-type pillar layer 13 is epitaxially grown on the entire surface of the n + -type drain layer 12, and a photolithography method is performed on the n-type layer 13 ′. Thus, a resist M1 is formed along the shape of the first n-type pillar layer 13. Subsequently, a trench 15 ′ for embedding and forming the second n-type pillar layer 15 is formed by reactive ion etching (RIE) using the resist M1 as a mask.

  Next, as shown in FIG. 4, boron (B) is ion-implanted from an oblique direction toward the side wall of the trench 15 '. Thereafter, as shown in FIG. 5, ion implantation is performed a plurality of times while changing the angle of ion implantation. Thereby, the amount of boron implanted increases toward the upper side, that is, toward the source electrode 20 side.

  Thereafter, for example, a thermal process of about 1150 ° C. × 8 hours is performed to diffuse boron, thereby forming the p-type pillar layer 14 along the side wall of the trench 15 ′. The p-type pillar layer 14 has a high impurity concentration on the upper side and a low impurity concentration on the lower side by changing the amount of boron implanted as described above.

Subsequently, after removing the resist M1, as shown in FIG. 7, an n-type semiconductor layer is buried and formed in the trench 15 ′ by epitaxial growth to form a second n-type pillar layer 15. In the middle of this embedding process, in order to prevent a void (void) as shown by a dotted line in FIG. 5 from being formed in the p-type pillar layer 15, the embedding layer in the trench is tapered so as to be appropriately etched. It is preferred to keep. For this reason, the width of the second n-type pillar layer 15 is wide on the surface side where the source electrode 20 is formed, and is narrow on the bottom side where the drain electrode 11 is formed. The charge balance in the super junction structure is determined by the amount of charge contained in the pillar layer, that is, the product of the impurity concentration and the width of the pillar layer. For this reason, changing the width of the pillar layer is synonymous with changing the impurity concentration. When the trench 15 ′ is formed and then tapered by etching, the trench width is changed in the depth direction, and the impurity concentration of the second n-type pillar layer 15 is changed.
Thereafter, the chemical mechanical polishing (CMP) is used to remove and planarize the n-type semiconductor layer formed outside the trench 15 ′ by the CMP method or the like. Finally, as shown in FIG. 8, a MOSFET is formed by performing a well-known MOSFET manufacturing process.

  By increasing the number of times of changing the ion implantation angle of FIGS. 4 and 5 and further increasing the time of the thermal process, the impurity concentration on a substantially straight line as shown by a straight line bb ′ in FIG. A p-type pillar layer 14 having a distribution can be formed.

  9 and 10 show a modification of the first embodiment. When the number of times of changing the ion implantation angle as shown in the steps of FIGS. 4 and 5 is reduced and the time of the thermal step is further shortened, the impurity concentration distribution of the p-type pillar layer 14 is changed from the drain electrode 11 side to the source electrode 12 side. In this direction, the impurity concentration increases stepwise. When the implantation angle is changed twice, as shown in the modification of FIG. 9, the impurity concentration distribution is as shown by the dotted line bb ′. Even in such an impurity concentration distribution, the impurity concentration of the p-type pillar layer 14 is constant in the depth direction as long as the balance of the impurity amount at the upper end portion of the pillar layer where the electric field tends to concentrate is maintained. Compared to the above, the withstand voltage can be made sufficiently large.

  It is also possible to form the trench 15 ′ to a depth that reaches the n + -type drain layer 12 as in the modification of FIG. In this case, even if boron is implanted into the bottom of the groove by ion implantation from an oblique direction, it is not connected to the p pillar layer 14 and does not affect the super junction structure.

  Second Embodiment FIG. 11 is a cross-sectional view schematically showing a configuration of a power MOSFET according to a second embodiment of the present invention. In this embodiment, the impurity concentration bb ′ of the p-type pillar layer 14 is larger than the impurity concentration distribution cc ′ of the second n-type pillar layer 15. Thus, the impurity concentration of the p-type pillar layer 14 is higher than the average impurity concentration of the n-type pillar layers 13 and 14 on the source electrode 20 side of the super junction structure, and the p-type pillar layer 14 of the p-type pillar layer 14 is on the drain electrode 11 side. The impurity concentration is lower than the average impurity concentration of the n-type pillar layers 13 and 15. Thereby, the electric field of the upper and lower ends of a super junction structure falls. Since the electric field distribution is not flat, the maximum withstand voltage is reduced as compared with the first embodiment, but the electric field concentration at the upper and lower ends is relaxed as compared with the first embodiment. As a result, variations in the impurity concentration in the lateral direction, that is, a decrease in breakdown voltage due to charge imbalance can be reduced, and a wide process margin can be obtained. Thus, the avalanche resistance is increased by making the impurity concentration distribution (gradient) in the depth direction of the p-type pillar layer 14 larger than the average impurity concentration distribution (gradient) in the depth direction of the n-type pillar layers 13 and 15. It is also possible to do. By increasing the impurity concentration distribution in the depth direction, the electric field concentration at the upper and lower ends of the superjunction structure is weakened, and avalanche breakdown is likely to occur in the central part of the superjunction structure, which makes it possible to increase the avalanche resistance. Become.

  Also, as shown in FIG. 12, the impurity concentration distribution of the p-type pillar layer 14 is stepped so that the p-type impurity concentration is high on the source electrode 20 side and the n-type impurity concentration is high on the drain electrode 11 side. It is also possible to make it. In this case, although not shown, the p-type pillar layer 14 may be configured to reach the n + drain layer 12.

  FIG. 12 shows an impurity concentration distribution in which the impurity concentration (bb ′) of the p-type pillar layer 14 is larger than the impurity concentration (cc ′) of the n-type pillar layer 15. If the impurity concentration of the p-type pillar layer 14 is higher on the source electrode 20 side of the super junction structure and lower on the drain electrode 11 side than the average impurity concentration of the pillar layer 13 and the second n-type pillar layer 15, the above embodiment The same effect can be obtained.

  Third Embodiment FIG. 13 is a cross-sectional view schematically showing the configuration of a power MOSFET according to a third embodiment of the present invention. In this embodiment, the super junction structure is formed not only in the element formation region where the MOSFET cell is formed, but also in the termination region surrounding it. A RESURF layer 24, which is a p-type semiconductor layer, is formed on the surface of the super junction structure. Thereby, when a high voltage is applied, the depletion layer is quickly extended in the lateral direction, and electric field concentration at the end of the p-type base layer 16 is suppressed, and a high breakdown voltage MOSFET can be obtained. A field insulating film 25 is formed on the surface of the RESURF layer 14. Further, an n-type field stop layer 27 for blocking the extension of the depletion layer is formed at the end of the termination region, and a field stop electrode 26 is formed thereon.

  As shown in FIG. 14, a field plate electrode 28 may be formed on the field insulating film 25 instead of or in addition to the RESURF layer 24. As with the RESURF layer 24, the field plate electrode 28 acts to quickly extend the depletion layer in the lateral direction when a high voltage is applied. In FIG. 14, the field plate electrode 18 is connected to the source electrode 20, but may be connected to the gate electrode 19.

  (4th Embodiment) FIG. 15: is sectional drawing which shows typically the structure of power MOSFET concerning the 4th Embodiment of this invention.

  In this embodiment, the super junction structure is not formed in the termination region, the n− type high resistance layer 30 is formed, and the p type guard ring layer 29 is formed on the surface thereof. As a result, the electric field concentration at the end of the p-type base layer 16 is alleviated, and a high breakdown voltage MOFET can be obtained. In such a structure, a trench groove is formed on the surface of the substrate having an n − type high resistance epitaxial growth layer, the first n-type pillar layer 13 is formed by ion implantation from an oblique direction, and then the p-type pillar layer 14 is obliquely formed. It can be formed by ion implantation from the direction and thermal diffusion, and further by forming the second n-type pillar layer 15 by buried growth. Although FIG. 15 shows an example of a MOSFET having three guard ring layers 29, the number of guard ring layers is not particularly limited and can be implemented if one or more guard ring layers are formed.

  Fifth Embodiment FIG. 16 is a cross-sectional view schematically showing the configuration of a power MOSFET according to a fifth embodiment of the present invention. This embodiment is different from the above-described embodiment in that the gate electrode 19 of the MOSFET cell has a so-called trench gate structure. That is, a trench reaching the second n-type pillar layer 15 is formed in the p-type base layer 16, and a gate electrode is embedded in the trench via the gate insulating film 18. Along with miniaturization of the super junction structure, it is necessary to reduce the lateral period of the gate structure of the MOSFET cell in order to reduce the on-resistance. In the case of the trench gate structure, the MOSFET gate structure can be further miniaturized than the planar gate structure. By using the trench gate structure, it is possible to form a MOSFET cell with the same lateral period as the super junction structure, and it is possible to reduce the on-resistance as the super junction structure is miniaturized.

  Sixth Embodiment FIG. 17 is a cross-sectional view schematically showing the configuration of a power MOSFET according to a sixth embodiment of the present invention. In this embodiment, the gate electrode structure of the MOSFET cell and the super junction structure are both formed in a stripe shape and arranged so that their extending directions are orthogonal to each other. By adopting such a structure, it is not necessary to make the period in the lateral direction of the super junction structure equal to the period of the MOS gate structure, and the former can be made smaller than the latter. For this reason, the lateral period of the super junction structure can be made narrower than that of the planar gate structure, which is difficult to miniaturize, and the on-resistance can be reduced without miniaturizing the gate electrode structure of the MOSFET cell. It becomes.

  As mentioned above, although embodiment of this invention was described, this invention is not limited to the said embodiment. For example, although the first conductivity type has been described as n-type and the second conductivity type as p-type, the first conductivity type may be p-type and the second conductivity type may be n-type.

In addition, although the MOSFET using silicon (Si) as the semiconductor has been described, a compound semiconductor such as silicon carbide (SiC) or gallium nitride (GaN) or a wide band gap semiconductor such as diamond is used as the semiconductor. Can do.
Further, although the MOSFET having a super junction structure has been described, the structure of the present invention can be applied to an element such as an SBD, a mixed element of MOSFET and SBD, or an element such as SIT or IGBT as long as the element has a super junction structure.
In addition, the following modifications and additions are possible.
(1) The impurity concentration on the second main electrode side of the second semiconductor pillar layer is different from the impurity concentration on the second main electrode side of the first semiconductor pillar layer and the second concentration of the third semiconductor pillar layer. 2. The semiconductor element according to claim 1, wherein the semiconductor element is set to be equal to or higher than an average value with respect to an impurity concentration on the main electrode side.
(2) The impurity concentration on the first main electrode side of the second semiconductor pillar layer is different from the impurity concentration on the first main electrode side of the first semiconductor pillar layer and the first concentration of the third semiconductor pillar layer. The semiconductor element according to (1), wherein the semiconductor element is set to be equal to or less than an average value of the impurity concentration on the main electrode side.
(3) The semiconductor element according to claim 1, wherein the impurity concentration of the second semiconductor pillar layer increases stepwise from the first main electrode toward the second main electrode.
(4) The semiconductor element according to claim 1, wherein the concentration change of the impurity concentration in the depth direction of the second semiconductor pillar layer is larger than the concentration change of the third semiconductor pillar layer in the depth direction.
(5) The semiconductor element according to claim 1, wherein the pillar layer is also formed at an element termination portion.
(6) The semiconductor element according to (5), wherein a second conductivity type semiconductor layer is formed on an upper portion of the pillar layer formed at the element termination portion.
(7) The semiconductor element according to claim 1, wherein a field plate electrode electrically connected to the second main electrode or the control electrode is formed at an element termination portion.
(8) The semiconductor device according to (1), wherein the first to third semiconductor pillar layers each have a stripe structure and are alternately formed in a horizontal direction at a predetermined period.
(9) The semiconductor base layer and the first and third semiconductor pillar layers are formed so that the surfaces thereof are substantially coincident with each other, and the control electrode is formed via an insulating film formed on the substantially coincident surfaces. The semiconductor device according to claim 1.
(10) The control electrode has a trench gate structure adjacent to the semiconductor base layer and the semiconductor diffusion layer through an insulating film embedded in a trench formed on the surface side of the first semiconductor pillar layer. The semiconductor element according to claim 1.
(11) a direction in which the first to third semiconductor pillar layers are alternately formed in a stripe shape in a horizontal direction;
2. The semiconductor element according to claim 1, wherein a direction in which the control electrodes are formed in a stripe shape at a predetermined interval is the same direction.
(12) a direction in which the first to third semiconductor pillar layers are alternately formed in a stripe shape in a horizontal direction;
The semiconductor element according to claim 1, wherein a direction in which the control electrodes are formed in a stripe shape at a predetermined interval is substantially orthogonal.
(13) The semiconductor element according to (12), wherein a period in which the first to third semiconductor pillar layers are formed in a lateral direction is smaller than a period in which the control electrode is formed.

It is sectional drawing which shows typically the structure of power MOSFET concerning the 1st Embodiment of this invention. It is explanatory drawing explaining the advantage of power MOSFET which concerns on 1st Embodiment. The manufacturing process of power MOSFET of a 1st embodiment is shown. The manufacturing process of power MOSFET of a 1st embodiment is shown. The manufacturing process of power MOSFET of a 1st embodiment is shown. The manufacturing process of power MOSFET of a 1st embodiment is shown. The manufacturing process of power MOSFET of a 1st embodiment is shown. The manufacturing process of power MOSFET of a 1st embodiment is shown. The 1st modification of 1st Embodiment is shown. The 2nd modification of 1st Embodiment is shown. It is sectional drawing which shows typically the structure of power MOSFET concerning the 2nd Embodiment of this invention. The modification of 2nd Embodiment is shown. It is sectional drawing which shows typically the structure of power MOSFET concerning the 3rd Embodiment of this invention. The modification of 3rd Embodiment is shown. It is sectional drawing which shows typically the structure of power MOSFET concerning the 4th Embodiment of this invention. It is sectional drawing which shows typically the structure of power MOSFET concerning the 5th Embodiment of this invention. It is sectional drawing which shows typically the structure of power MOSFET concerning the 6th Embodiment of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 11 ... Drain electrode, 12 ... n + type drain layer, 13 ... 1st n-type pillar layer, 14 ... p-type pillar layer, 15 ... 2nd n-type pillar layer, 16 ... p Type base layer, 17 ... n-type source diffusion layer, 18 ... gate insulating film, 19 ... gate electrode, 20 ... source electrode, 24 ... RESURF layer, 25 ... field insulating film 27 ... Field stop layer, 28 ... Field stop electrode, 30 ... High resistance layer.

Claims (5)

A first semiconductor layer of a first conductivity type;
A first conductive type first semiconductor pillar layer, a second conductive type second semiconductor pillar layer, and a first conductive type third semiconductor pillar layer are periodically and alternately arranged on the first semiconductor layer. The pillar layer,
A first main electrode electrically connected to the first semiconductor layer;
A second conductivity type semiconductor base layer selectively formed on a surface of the second semiconductor pillar layer;
A semiconductor diffusion layer of a first conductivity type selectively formed on the surface of the semiconductor base layer;
A second main electrode formed to be bonded to the semiconductor base layer and the semiconductor diffusion layer;
A control electrode formed through an insulating film along the semiconductor base layer, the semiconductor diffusion layer, and the first semiconductor pillar layer;
The second and third semiconductor pillar layers are formed so as to have an impurity concentration distribution with a higher impurity concentration on the second main electrode side than on the first main electrode side. A semiconductor element.   The impurity concentration on the second main electrode side of the second semiconductor pillar layer is different from the impurity concentration on the second main electrode side of the first semiconductor pillar layer and the second main electrode of the third semiconductor pillar layer. The semiconductor element according to claim 1, wherein the semiconductor element is set to be equal to or higher than an average value of the impurity concentration on the side.   2. The semiconductor device according to claim 1, wherein the impurity concentration of the second semiconductor pillar layer increases in a stepped manner from the first main electrode toward the second main electrode.   2. The semiconductor device according to claim 1, wherein a concentration change in the impurity concentration in the depth direction of the second semiconductor pillar layer is larger than a concentration change in the depth direction of the third semiconductor pillar layer.   2. The semiconductor element according to claim 1, wherein the second semiconductor pillar layer is formed to a depth reaching the first semiconductor layer.

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