JP2007207866A

JP2007207866A - Mos transistor and its fabrication process

Info

Publication number: JP2007207866A
Application number: JP2006022740A
Authority: JP
Inventors: Kazuhiro Tsumura; 和宏津村
Original assignee: Seiko Instruments Inc
Current assignee: Seiko Instruments Inc
Priority date: 2006-01-31
Filing date: 2006-01-31
Publication date: 2007-08-16

Abstract

<P>PROBLEM TO BE SOLVED: To provide an LOCOS offset MOS transistor exhibiting high driving capability and stabilized characteristics while ensuring high breakdown voltage. <P>SOLUTION: In an LOCOS offset MOS transistor, a low concentration diffusion region of 1×10<SP>16</SP>to 1×10<SP>18</SP>atoms/cm<SP>3</SP>is formed in the offset region; a high concentration diffusion region is formed in the drain region; and an intermediate concentration diffusion region surrounding the high concentration drain region and reaching the lower portion of a bird's beak on the drain region side of an LOCOS used for offset, and having a concentration 2-100 times as high as that of the low concentration diffusion region, is formed in the drain structure. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

この発明は、LOCOS酸化膜をドレインオフセットに用いたLOCOSオフセット型MOSトランジスタのドレイン構造と、その製造方法に関するものである。 The present invention relates to a drain structure of a LOCOS offset type MOS transistor using a LOCOS oxide film as a drain offset and a manufacturing method thereof.

従来のLOCOS酸化膜をドレインオフセットに用いたLOCOSオフセット型MOSトランジスタのドレイン構造を図2に、製造工程を示す断面図を図４に示す。半導体基板１において、Well領域を形成した後、半導体基板上に厚さ100〜500Å程度の薄い下敷き酸化膜を形成し、その上に500〜2000Å程度の窒化膜を成膜して、LOCOS酸化膜３を形成する領域の窒化膜を選択的に除去することによって、窒化膜パターン10を形成する。次にレジストと窒化膜１０をマスクに用いて所望の領域にリンをイオン注入する。同様にレジストと窒化膜１０をマスクに用いて所望の領域にボロンをイオン注入する（図４(a)参照）。次に、レジストマスクを除去して1000℃程度の温度でLOCOS酸化膜の形成を行う。LOCOS酸化膜下部でリンをイオン注入した領域はN−領域となり、LOCOSオフセット型NMOSトランジスタのオフセット領域として、また、PMOSトランジスタ領域の素子分離、或いはチャネルストッパとして利用される。一方、ボロンをイオン注入した領域はP−領域となり、NMOSトランジスタ領域の素子分離やチャネルストッパとして、また、LOCOSオフセット型PMOSトランジスタのオフセット領域に利用される。次に、窒化膜パターン１０を除去し（図４(b)参照）、アクティブ領域のシリコン表面を清浄にした後、ゲート酸化膜５を形成する。その上部にソース、ドレイン側のLOCOS酸化膜をまたがってポリシリコンからなるゲート電極６を形成する。続いてNMOSトランジスタではリン或いはヒ素を、PMOSトランジスタではBF₂等を高濃度にイオン注入してソース、ドレインとなる高濃度領域７を形成する（図４(c)参照）。次に図には示していないが、BPSG膜を成膜してから、ソース、ドレイン、ゲート電極それぞれにコンタクトホールを設けた後、アルミ配線を形成し、それらを覆うようにパッシベーション膜を成膜することにより、LOCOSオフセット型MOSトランジスタと呼ばれる半導体装置が完成する。この構造ではN−或いはP−の低濃度拡散領域の濃度が薄い場合に、オフセット領域の低濃度拡散領域２とソース、ドレインの高濃度拡散領域７の連接が不完全になりうるという問題があった。そのため、いくつかの対策がこれまでも考案されてきた。例えば、特許文献１のようにLOCOSのバーズビークの発生を抑制したり、或いは、特許文献２のようにLOCOSの形状に工夫を凝らしたりすることで低濃度拡散領域と高濃度拡散領域の連結を確実にする方法が考案されている。
特開平５−６３１９３号公報特開平６−２９３１３号公報 FIG. 2 shows a drain structure of a LOCOS offset type MOS transistor using a conventional LOCOS oxide film as a drain offset, and FIG. 4 is a sectional view showing a manufacturing process. In the semiconductor substrate 1, after forming the well region, a thin underlying oxide film having a thickness of about 100 to 500 mm is formed on the semiconductor substrate, and a nitride film having a thickness of about 500 to 2000 mm is formed thereon, and a LOCOS oxide film is formed. The nitride film pattern 10 is formed by selectively removing the nitride film in the region for forming 3. Next, phosphorus is ion-implanted into a desired region using the resist and the nitride film 10 as a mask. Similarly, boron is ion-implanted into a desired region using the resist and the nitride film 10 as a mask (see FIG. 4A). Next, the resist mask is removed and a LOCOS oxide film is formed at a temperature of about 1000.degree. The region where phosphorus is ion-implanted under the LOCOS oxide film becomes an N− region, which is used as an offset region of the LOCOS offset type NMOS transistor, as an element isolation of the PMOS transistor region, or as a channel stopper. On the other hand, the region into which boron is ion-implanted becomes a P− region, which is used as an element isolation in the NMOS transistor region, a channel stopper, and an offset region of the LOCOS offset type PMOS transistor. Next, after removing the nitride film pattern 10 (see FIG. 4B) and cleaning the silicon surface in the active region, the gate oxide film 5 is formed. A gate electrode 6 made of polysilicon is formed above the LOCOS oxide film on the source and drain sides. Subsequently, phosphorus or arsenic is ion-implanted at a high concentration in the NMOS transistor, and BF ₂ or the like is ion-implanted in the PMOS transistor to form a high concentration region 7 serving as a source and a drain (see FIG. 4C). Next, although not shown in the figure, after forming a BPSG film, after making contact holes in each of the source, drain, and gate electrodes, an aluminum wiring is formed, and a passivation film is formed to cover them Thus, a semiconductor device called a LOCOS offset type MOS transistor is completed. In this structure, when the concentration of the N− or P− low concentration diffusion region is low, the connection between the low concentration diffusion region 2 of the offset region and the high concentration diffusion region 7 of the source and drain may be incomplete. It was. Therefore, some measures have been devised so far. For example, the generation of LOCOS bird's beaks as in Patent Document 1 or the LOCOS shape as in Patent Document 2 is devised to ensure the connection between the low concentration diffusion region and the high concentration diffusion region. A method has been devised.
JP-A-5-63193 JP-A-6-29313

まず、N型トランジスタについて述べる。前述のように、LOCOSオフセット型NMOSトランジスタのオフセット領域の低濃度拡散領域（N−領域）２とドレインの高濃度拡散領域（N＋領域）７の連接が不完全になる場合がある。この場合に生じる課題は、N＋領域７の下部エッジの接合部８がN−領域２で覆われていない場合に、この接合部８でN＋とPwellの間の接合耐圧が不足すること、N＋とN−領域が完全に分離している場合はMOSトランジスタがONしないこと、である。また、バーズビークは窒化膜パターン１０の端から窒化膜パターンの内部方向に出来るものであるから、N−領域形成のための不純物はこのバーズビーク下部にドープされていない。よって、バーズビーク下部のN−領域は、不純物の熱拡散によって形成されるため、他のN−領域に較べて不純物濃度が薄くなっている。そのため、N−領域２とN＋領域７の連接が完全であっても、LOCOSのドレイン側バーズビーク下部９におけるN−領域２の不純物濃度が薄いことによる寄生抵抗の増大のために、MOSトランジスタの駆動能力が低下するという課題がある。また、N−濃度を濃くすることでN＋とN−領域の連接は確実にすることができ、寄生抵抗の低減もはかれるが、N−領域を濃くするとMOSトランジスタの耐圧が低下するため、耐圧で決まる濃度以上に濃くすることはできない。このように、オフセット型MOSトランジスタにおいて、耐圧を下げずに、高駆動能力で安定した特性をもたせることは難しい。以上、N型トランジスタについて述べてきたがP型トランジスタでも同様である。そこで、本発明では、高耐圧を確保し、且つ高駆動能力で安定した特性をもつLOCOSオフセット型MOSトランジスタの提供を目的とする。 First, an N-type transistor will be described. As described above, the connection between the low concentration diffusion region (N− region) 2 in the offset region of the LOCOS offset NMOS transistor and the high concentration diffusion region (N + region) 7 in the drain may be incomplete. The problem that arises in this case is that when the junction 8 at the lower edge of the N + region 7 is not covered with the N− region 2, the junction breakdown voltage between N + and Pwell is insufficient at the junction 8, N + If the N− region is completely separated, the MOS transistor is not turned on. Further, since the bird's beak is formed from the end of the nitride film pattern 10 to the inside of the nitride film pattern, the impurity for forming the N-region is not doped below the bird's beak. Therefore, since the N− region below the bird's beak is formed by thermal diffusion of impurities, the impurity concentration is lower than other N− regions. Therefore, even if the connection between the N− region 2 and the N + region 7 is complete, the MOS transistor is driven due to an increase in parasitic resistance due to the low impurity concentration in the N− region 2 at the drain side bird's beak lower portion 9 of the LOCOS. There is a problem that the ability is reduced. In addition, increasing the N− concentration can ensure the connection between the N + and N− regions and reduce the parasitic resistance. However, increasing the N− region decreases the breakdown voltage of the MOS transistor. It cannot be made higher than the determined density. Thus, it is difficult for the offset MOS transistor to have stable characteristics with high driving capability without lowering the breakdown voltage. Although the N-type transistor has been described above, the same applies to the P-type transistor. Accordingly, an object of the present invention is to provide a LOCOS offset type MOS transistor that secures a high breakdown voltage and has a stable characteristic with a high driving capability.

本発明では、ＭＯＳ型半導体装置に用いられるMOSトランジスタの高耐圧ドレイン構造のうちLOCOS酸化膜をドレインオフセットに用いたLOCOSオフセット型MOSトランジスタにおいて、オフセット領域には濃度1×10¹⁶〜1×10¹⁸atoms/cm³の低濃度拡散領域、ドレイン領域には高濃度拡散領域を配置し、さらに、高濃度ドレイン領域を囲んでオフセットに用いるLOCOSのドレイン領域側のバーズビーク下部まで達する濃度が低濃度拡散領域の２〜100倍である中濃度拡散領域を配置したＭＯＳ型半導体装置の高耐圧ドレイン構造を採用することで、前記の課題を解決する。 In the present invention, in the LOCOS offset type MOS transistor using the LOCOS oxide film for the drain offset in the high breakdown voltage drain structure of the MOS transistor used in the MOS type semiconductor device, the concentration in the offset region is 1 × 10 ¹⁶ to 1 × 10 ^18. A low-concentration diffusion region of atoms / cm ³ is arranged in the low-concentration diffusion region and the drain region, and the concentration reaching the lower part of the bird's beak on the drain region side of the LOCOS used for offset surrounding the high-concentration drain region By adopting the high breakdown voltage drain structure of the MOS type semiconductor device in which the medium concentration diffusion region which is 2 to 100 times as large as the above is adopted, the above problem is solved.

本発明により、高耐圧を確保し、且つ駆動能力の高い安定した特性をもつLOCOSオフセット型MOSトランジスタが得られる。以下、図１、２に沿って詳しく説明する。高濃度拡散領域７は同伝導型の中濃度拡散領域４で完全に覆われているため、高濃度拡散領域下部エッジの接合部８における接合耐圧の問題は無くなる。高濃度拡散領域７と低濃度拡散領域２が完全に離れてしまっても中濃度拡散領域４で連接されるため、MOSトランジスタがONしないという問題は無くなる。LOCOS酸化膜３のドレイン側バーズビーク下部９において低濃度拡散領域２の不純物濃度が薄いことによる寄生抵抗の増大は、領域９を中濃度拡散領域４が覆っているため低抵抗化が実現し、MOSトランジスタの高駆動能力化が図れる。また、中濃度拡散領域４はLOCOS酸化膜３に対してセルフアラインでインプラし、熱処理による拡散で低濃度拡散領域２と充分にオーバーラップさせるため、プロセスのばらつきに対して強く、安定した特性が得られる。また、中濃度拡散領域４はLOCOS酸化膜３のドレイン側バーズビーク下部９までしか拡散させないため、MOSトランジスタの耐圧、例えばソース・ドレイン間耐圧、表面ブレークダウン等の低下は起きない。 According to the present invention, it is possible to obtain a LOCOS offset type MOS transistor having a high breakdown voltage and a stable characteristic with high driving capability. Hereinafter, a detailed description will be given with reference to FIGS. Since the high-concentration diffusion region 7 is completely covered with the medium-concentration diffusion region 4 of the same conductivity type, the problem of junction breakdown voltage at the junction 8 at the lower edge of the high-concentration diffusion region is eliminated. Even if the high-concentration diffusion region 7 and the low-concentration diffusion region 2 are completely separated from each other, the problem is that the MOS transistor does not turn on because the middle-concentration diffusion region 4 is connected. The increase in parasitic resistance due to the low impurity concentration in the low-concentration diffusion region 2 at the drain-side bird's beak lower portion 9 of the LOCOS oxide film 3 realizes low resistance because the region 9 is covered with the medium-concentration diffusion region 4. High drive capability of the transistor can be achieved. In addition, since the intermediate concentration diffusion region 4 is implanted into the LOCOS oxide film 3 in a self-aligned manner and sufficiently overlaps with the low concentration diffusion region 2 by diffusion by heat treatment, it is strong against process variations and has stable characteristics. can get. Further, since the intermediate concentration diffusion region 4 is diffused only up to the drain side bird's beak lower portion 9 of the LOCOS oxide film 3, the breakdown voltage of the MOS transistor, for example, the breakdown voltage between the source and the drain, the surface breakdown or the like does not occur.

以下に本発明を実施するための最良の形態を、図１を用いて説明する。半導体基板１上に厚さ0.3〜1.0um程度のLOCOS酸化膜３を形成する。このLOCOS酸化膜はトランジスタのドレインオフセット領域や素子分離領域として利用される。ドレインオフセット領域となるLOCOS酸化膜３の下には、MOSトランジスタのオフセット領域に利用されるドレインと同伝導型で不純物濃度1×10¹⁶〜1×10¹⁸atoms/cm³程度の低濃度拡散領域２を形成する。この領域２は電界を緩和してMOSトランジスタの耐圧を上げるために配置される。ドレインには高濃度拡散領域７を形成し、この高濃度拡散領域７を囲むように、ドレインと同伝導型の不純物濃度1×10¹⁷〜1×10¹⁹atoms/cm³程度の中濃度拡散領域４を形成する。この中濃度拡散領域はLOCOS酸化膜３のドレイン側バーズビーク下部まで延びており、低濃度拡散領域２と充分にオーバーラップしている。ゲート電極６はLOCOS酸化膜３とオーバーラップするように形成しMOSトランジスタのON/OFFが確実に行えるようにする。 The best mode for carrying out the present invention will be described below with reference to FIG. A LOCOS oxide film 3 having a thickness of about 0.3 to 1.0 μm is formed on the semiconductor substrate 1. This LOCOS oxide film is used as a drain offset region and an element isolation region of a transistor. Under the LOCOS oxide film 3 serving as a drain offset region, a low concentration diffusion region having an impurity concentration of about 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ and having the same conductivity type as the drain used for the offset region of the MOS transistor. 2 is formed. This region 2 is arranged in order to relax the electric field and increase the breakdown voltage of the MOS transistor. A high concentration diffusion region 7 is formed in the drain, and an intermediate concentration diffusion region having an impurity concentration of about 1 × 10 ¹⁷ to 1 × 10 ¹⁹ atoms / cm ³ having the same conductivity type as the drain is formed so as to surround the high concentration diffusion region 7. 4 is formed. This middle concentration diffusion region extends to the lower part of the drain side bird's beak of the LOCOS oxide film 3 and sufficiently overlaps with the low concentration diffusion region 2. The gate electrode 6 is formed so as to overlap with the LOCOS oxide film 3 so that the MOS transistor can be turned on and off reliably.

本実施例を図１、図３に沿って説明する。半導体基盤上に厚さ100〜500Å程度の薄い下敷き酸化膜を形成し、その上に500〜2000Å程度の窒化膜を成膜して、LOCOS酸化膜を形成したい領域の窒化膜を選択的に除去することによって、窒化膜パターン10を形成する。次に、この窒化膜パターン10とレジストパターンをマスクに用いて、不純物をドープし、濃度が1×10¹⁶〜5×10¹⁷atoms/cm³くらいの低濃度拡散領域２を形成する。次にレジストマスクを除去（図３(a)参照）し、温度800〜1100℃程度で厚さ0.3〜1.0umくらいのLOCOS酸化膜３を形成した後、窒化膜を除去する（図３(b)参照）。次に、レジストマスクとLOCOS酸化膜をマスクに用いてドレイン領域に不純物をドープし、濃度が低濃度拡散領域の２〜100倍である中濃度拡散領域４を形成する（図３(c)参照）。この中濃度拡散領域４をLOCOS酸化膜３のバーズビーク下部まで熱拡散させる。次にアクティブ領域のシリコン表面を清浄にした後、ゲート酸化膜５を形成する（図３(d)参照）。ゲート酸化膜の厚さは所望するMOSトランジスタの動作電圧帯に応じて決める。次に厚さ2000〜5000Åくらいのポリシリコン膜を成膜して、ゲート電極として用いることができるように整形する。次に、高濃度拡散領域７を形成するために、ドレイン領域に不純物を高濃度にドープする（図３(e)参照）。これらの上に層間絶縁膜を成膜して、ソース、ドレイン、ゲート電極にコンタクトホールを設け、メタル膜を成膜する。次にメタル膜をパターニングした後その上にパッシベーション膜を成膜する。以上によって、高耐圧を確保し、高駆動能力で安定した特性をもつLOCOSオフセット型MOSトランジスタが得られる。 This embodiment will be described with reference to FIGS. A thin oxide film with a thickness of about 100 to 500 mm is formed on the semiconductor substrate, and a nitride film with a thickness of about 500 to 2000 mm is formed thereon, and the nitride film in the region where the LOCOS oxide film is to be formed is selectively removed. Thus, the nitride film pattern 10 is formed. Next, using the nitride film pattern 10 and the resist pattern as a mask, impurities are doped to form a low concentration diffusion region 2 having a concentration of about 1 × 10 ^{16 to} 5 × 10 ¹⁷ atoms / cm ³ . Next, the resist mask is removed (see FIG. 3A), a LOCOS oxide film 3 having a thickness of about 0.3 to 1.0 μm is formed at a temperature of about 800 to 1100 ° C., and then the nitride film is removed (FIG. 3B). )reference). Next, using the resist mask and the LOCOS oxide film as a mask, the drain region is doped with impurities to form a medium concentration diffusion region 4 whose concentration is 2 to 100 times that of the low concentration diffusion region (see FIG. 3C). ). This intermediate concentration diffusion region 4 is thermally diffused to the lower part of the bird's beak of the LOCOS oxide film 3. Next, after cleaning the silicon surface in the active region, a gate oxide film 5 is formed (see FIG. 3D). The thickness of the gate oxide film is determined according to the desired operating voltage band of the MOS transistor. Next, a polysilicon film having a thickness of about 2000 to 5000 mm is formed and shaped so that it can be used as a gate electrode. Next, in order to form the high concentration diffusion region 7, the drain region is doped with an impurity at a high concentration (see FIG. 3E). An interlayer insulating film is formed thereon, contact holes are provided in the source, drain and gate electrodes, and a metal film is formed. Next, after patterning the metal film, a passivation film is formed thereon. As described above, a LOCOS offset MOS transistor having a high breakdown voltage and stable characteristics with a high driving capability can be obtained.

中濃度拡散領域４をLOCOS酸化膜３のバーズビーク下にまで拡散させるための専用の熱処理を行わず、ゲート酸化やBPSG Densify等の他の熱行程を利用して拡散させる方法も可能である。 A method of diffusing by using other thermal processes such as gate oxidation or BPSG Densify is also possible without performing a dedicated heat treatment for diffusing the intermediate concentration diffusion region 4 under the bird's beak of the LOCOS oxide film 3.

中濃度拡散領域４形成のための不純物ドープは、LOCOS酸化膜３をマスクに用いることに特徴がある。よって、中濃度拡散領域４形成のための不純物ドープは、LOCOS酸化膜３形成直後でなくても良く、もっと後の工程で行なうことも可能である。 Impurity doping for forming the intermediate diffusion region 4 is characterized by using the LOCOS oxide film 3 as a mask. Therefore, the impurity doping for forming the intermediate concentration diffusion region 4 does not have to be performed immediately after the formation of the LOCOS oxide film 3 and can be performed in a later process.

中濃度拡散領域４と高濃度拡散領域７には異なる不純物種を用い、不純物の拡散速度の違いを利用して、中濃度拡散領域４と高濃度拡散領域７をつくり分ける方法も可能である。 A method is also possible in which different impurity species are used for the intermediate concentration diffusion region 4 and the high concentration diffusion region 7, and the intermediate concentration diffusion region 4 and the high concentration diffusion region 7 are separately produced by utilizing the difference in impurity diffusion rate.

中濃度拡散領域の形成において、LOCOS酸化膜の本来の厚さの領域は突き抜けないが、バーズビーク領域は突き抜ける加速エネルギーで不純物のイオン注入を行うことによって、熱拡散に頼らず、ドレイン側のバーズビーク下部まで達する中濃度拡散領域を形成することも可能である。 In the formation of the medium-concentration diffusion region, the original thickness region of the LOCOS oxide film does not penetrate, but the bird's beak region does not rely on thermal diffusion by performing ion implantation of impurities with the penetrating acceleration energy. It is also possible to form a medium concentration diffusion region that reaches the maximum.

本発明第一実施例のLOCOSオフセットドレイン構造の断面図。Sectional drawing of the LOCOS offset drain structure of 1st Example of this invention. 従来のLOCOSオフセットドレイン構造の断面図。Sectional drawing of the conventional LOCOS offset drain structure. 本発明第一実施例のLOCOSオフセットドレイン構造の行程断面図。1 is a cross-sectional view of a LOCOS offset drain structure according to a first embodiment of the present invention. 従来のLOCOSオフセットドレイン構造の行程断面図。The process sectional drawing of the conventional LOCOS offset drain structure.

Explanation of symbols

１半導体基盤
２低濃度拡散領域（N−領域、P−領域）
３ LOCOS酸化膜
４中濃度拡散領域（N±領域、P±領域）
５ゲート酸化膜
６ポリシリコンゲート電極
７高濃度拡散領域（N＋領域、P＋領域）
８高濃度領域下部エッジの接合部
９ LOCOSのドレイン側バーズビーク下部
１０窒化膜パターン 1 Semiconductor substrate 2 Low concentration diffusion region (N-region, P-region)
3 LOCOS oxide film 4 Medium concentration diffusion region (N ± region, P ± region)
5 Gate oxide film 6 Polysilicon gate electrode 7 High concentration diffusion region (N + region, P + region)
8 Junction at lower edge of high concentration region 9 Drain side bird's beak lower part of LOCOS 10 Nitride pattern

Claims

In a LOCOS offset type MOS transistor using a LOCOS oxide film as a drain offset, an offset region composed of a low concentration diffusion region having a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ³ and a drain region composed of a high concentration diffusion region A MOS transistor having a medium concentration diffusion region that surrounds the high concentration drain region and reaches the lower part of the bird's beak on the drain region side of the LOCOS used for offset, the concentration being 2 to 100 times that of the low concentration diffusion region.

A step of doping impurities into the drain region with a concentration of 1 × 10 ¹⁶ to 1 × 10 ¹⁸ atoms / cm ^{3 using the} LOCOS oxide film as a mask;
And a step of diffusing the impurity to a lower part of a bird's beak on the drain region side of LOCOS used as an offset in order to form an intermediate concentration diffusion region.

3. The impurity doping process according to claim 2, wherein in the step of doping the impurity, the ion implantation of the impurity is performed with an acceleration energy that does not penetrate the flat region where the LOCOS oxide film has an original thickness but penetrates the bird's beak region. MOS transistor manufacturing method.