JPS6254959A - Manufacture of mis semiconductor device - Google Patents

Abstract

PURPOSE:To prevent a current driving capacity from decreasing by forming the third impurity diffused region of lower density than the second impurity diffused region in higher density than the first impurity diffused region in source and drain regions with a gate electrode and the sidewall coating portion of the first insulating film layer as masks. CONSTITUTION:After a field oxide film 2 is formed on a P-type silicon substrate 1, a gate oxide film 3 is formed on an insular substrate 1 region surface to form a gate electrode 4. With the film 2 and the electrode 4 as masks phosphorus ions are implanted to form impurity diffused layer regions 51, 52. With multiplayer films 6, 7 and the electrode 4 as masks arsenic ions are implanted to be activated to form higher density N<+> type diffused regions 81, 82 together with low density N<-> type diffused regions 51, 52 on the substrate 1. The film 7 is removed, the film layer 6 is exposed, As or P ions are implanted to form lower density impurity diffused region than the regions 81, 82 in higher density than the regions 51, 52, then activated to form N<+> type diffused regions 91, 92. Thus, it can prevent a current driving capacity from decreasing upon increasing of a parasitic resistance.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing an MIS type semiconductor device, and more particularly to a method for manufacturing an MIS type semiconductor device in which the structure of a drain region is improved.

[Technical background of the invention and its problems]

Recently, as MIS type semiconductor devices (for example, MO8 type semiconductor integrated circuits) have become highly integrated and their transistors have become smaller, in order to alleviate the high electric field near the drain region and improve the breakdown voltage, A so-called LD whose drain range has a double structure of low concentration and high concentration impurity diffusion regions.
D (Light Doped Drain) structure was developed,
It has been put into practical use.

However, while the low concentration impurity diffusion region of the LDD structure suppresses the generation of hot carriers by relaxing the drain electric field, it is affected by the electric field generated by the hot carriers in the gate insulation film and other insulation films. , the surface of the low concentration impurity diffusion region becomes easily depleted. As a result, a peculiar deterioration phenomenon occurs in the LDD structure transistor in that the parasitic resistance increases by 1 compared to the low concentration impurity diffusion region, and the current driving ability decreases. In the LDD structure, the drain electric field relaxation effect increases as the concentration of the low-a-degree impurity diffusion region decreases, but the above-mentioned specific deterioration phenomenon also increases as the concentration decreases, resulting in contradictory requirements. There was a problem that the selection range became smaller.

[Purpose of the invention]

The present invention provides a high-performance and highly reliable MIS type semiconductor device that maintains the drain electric field relaxation effect of a low-concentration impurity diffusion region of LDDQ structure and prevents a decrease in current drive capability due to an increase in parasitic resistance due to the diffusion region. This is what we are trying to provide.

[Summary of the invention]

The present invention includes a semiconductor substrate of a first conductivity type, a source and drain region of a second conductivity type provided electrically isolated from each other on the surface of the substrate, and an insulated surface of the substrate including a channel region between these regions. A method for manufacturing an MI S type semiconductor device having a gate electrode provided through a film, wherein after forming the gate electrode, using the gate electrode as a mask, a low concentration first layer is applied to the source and drain regions. After forming an impurity diffusion layer region and depositing a first insulating film layer and a second insulating film layer, anisotropic etching is performed to form the first insulating film layer on the side wall portion of the gate electrode. , leaving a second insulating film layer and using the first insulating film layer and second insulating film layer on the side wall portion of the gate electrode and the gate electrode as a mask,
A second impurity diffusion region having a higher concentration than the first impurity diffusion region is formed in the source and drain regions, and after removing the second insulating film layer, the gate electrode and the first insulating film are removed. Using the sidewall adhering portion of the layer as a mask, the source and drain regions are doped at a higher concentration than the first impurity diffusion region,
A third impurity diffusion region having a lower concentration than the second impurity diffusion region is formed. [Effects of the Invention] According to the present invention, the I, DD tank structure low concentration impurity diffusion It is possible to obtain a high-performance and highly reliable MIS type semiconductor device that prevents a decrease in current drive capability due to an increase in parasitic resistance due to the diffused region while maintaining drain electric field relaxation due to the region.

[Embodiments of the invention]

Hereinafter, the present invention will be described as an n-channel MOS having an LDD structure.
An example of application to a transistor will be described with reference to the manufacturing method shown in FIG.

First, a field oxide film 2 is formed using the IK selective oxidation method on a P-type silicon substrate, and then a thermal oxidation treatment is performed to form a gate oxide film with a thickness of 250 A on the surface of the island-shaped substrate 1 area separated by the field oxide film 2. Film 3 was formed. Next, a polycrystalline silicon film with a thickness of 4000A was deposited on the entire surface, and the PO
After doping the polycrystalline silicon film with phosphorus to lower its resistance by performing phosphorus diffusion in a C/8 atmosphere, the gate electrode 4 is formed by patterning using a photo-etching technique.

(Illustrated in FIG. 1(a)) Next, using the field oxide film 2 and the goo electrode 4 as a mask, for example, phosphorus is accelerated at a voltage of 40 K f
Ion implantation with fk2 x 10"cm-"
Impurity diffusion layer regions 58, 5□ are formed. (Figure 1 (
b)) Next, as the first insulating film, a silicon nitride film 6 is deposited, for example, by the OVD method, and as the second insulating film, a silicon oxide film 7, for example, is deposited in sequence by the OVD method. Thereafter, anisotropic etching is performed using, for example, a reactive ion/etch/etching method to leave a multilayer film of the first insulating film 6 and the second insulating film 7 on the side walls of the gate electrode. Further, using the pole 4 as a mask, arsenic is applied to the multilayer films 6, 7 and the gate at an accelerating voltage of 50.
Ion implantation is performed under the conditions of KeV and a dose of 5 x 10"cm-".

Thereafter, it is activated and a low concentration n-diffusion region (first diffusion region) is formed on the surface of the substrate 15. ．． 5 □ and said n
− type diffusion region 51.52 and Q high concentration n4 type diffusion region (
second diffusion regions) 81 and 82 are formed. (Figure 1 (C
)) Next, Gate TI! , among the insulating film layers 6 and 7 on the pole side walls,
The second insulating film 7 is removed using, for example, NH, F solution to expose the frame-shaped insulating film layer 6. After that, using the @2 insulating film 6 attached to the gate electrode and the side walls of the gate electrode as a mask, an n-type impurity, for example, A
s or P ion implantation to form the first impurity diffusion region 5.
, 52 and the second impurity diffusion region 8.
, 8. After forming a third impurity diffusion region with a lower concentration, it is activated to form an n++ diffusion region (third diffusion region) 9□,
Form 92.

Through these steps, n-type diffusion regions 51+52, n-type diffusion regions 9. ,9. , n++ diffusion region8. , 8. Source and drain regions are formed. (Figure 1(d)
)) Then C! After depositing a VD-sio film 1o and opening contact holes in the 0VD-810 film 10 and gate oxide film 3 by photo-etching, an A7 film is deposited and patterned to form the source and drain regions. An n-channel MOS transistor was manufactured by forming an Al wiring 11 connected to the region through a contact hole (FIG. 1fe)). An n-1 Jl diffusion region 5 □ is provided on the surface of the substrate 1 near the end of the gate electrode 4 .

52, and an n-type diffusion region 9 which is provided on most of the surface of the diffusion regions 51+52 and has a high concentration of υ than the diffusion regions 58, 5□.
An n++ diffusion region 8.1°92 is provided on the surface of the substrate 1 at a position spaced apart from the end of the gate electrode 4, and has a higher concentration than the n-type diffusion regions 90, 9□. ．． It has an LDD structure in which source and drain regions are formed with 8 squares. Therefore, the n-type diffusion region 52 in the drain region can suppress the generation of hot carriers and relax the drain electric field. In addition, hot carriers cause the gate oxide film 3 to
5. The n-type diffusion region due to the influence of the electric field generated in it. The depletion of can be prevented by the n-type diffusion region 92 provided on the surface thereof, and as a result, the decrease in electric field driving ability can be eliminated.

Note that n as the first, second and third impurity diffusion regions
The conditions for forming the − type diffusion region, the n++ diffusion region, and the n type diffusion region are not limited to those in the above embodiments, and can be freely changed within the scope of achieving the object of the present invention.

Next, a comparative example will be explained using FIG. 2 (al to cl) manufacturing process cross-sectional views.

First, a field oxide film 2 is formed on a P-type silicon substrate 1 by selective oxidation, and then a thermal oxidation method is applied to the surface of the island-shaped substrate 1 separated by the field oxide film 2 to a thickness of 200 mm.
A human gate oxide film 3 is formed. Subsequently, a gate electrode 4 is formed of polycrystalline silicon doped with phosphorus using a normal photomask process. Next, using the field oxide film 2 and the gate electrode 4 as a mask, for example, phosphorus is accelerated at a voltage of 40 KeV 1 and a dose of 2 x 10"cm.
" On-implantation is performed under the conditions of 5. to form a low concentration n-type diffusion layer.
,5. (Figure (a)). Then apply 5-i to the entire surface.
02 film is deposited, and the entire surface is etched using a reactive ion etching method to form a wall body 6 made of Sin on the side surface of the gate electrode 4. After this, field oxide film 2,
The n-
N-type diffusion layer 91 + 9 with higher concentration than diffusion layer 58, 5□
．． For example, arsenic is accelerated at a voltage of 30 KeV and a dose of I.
It is formed by ion implantation under the condition of x 10"cm-" (Figure (b)). For example, a 5 in 2 film 8 is deposited on the entire surface again, and the entire surface is etched using a reactive ion etching method, thereby forming a wall 8 of mud 2 on the side surfaces of the gate electrode 4 and the wall 6. Next, using the field oxide film 2, gate electrode 4, and walls 6 and 8 as masks, an n+ type diffused layer 8 with a higher concentration than the n type diffused layers 91 + 92 is formed in a self-aligned manner.
, 8. For example, arsenic is accelerated at a voltage of 40 KeV and a dose of 5.
It is formed by ion implantation under the condition of ×10 cWt.

In the above embodiment, an example was explained in which the application was applied to an n-channel MOS transistor, but MIS using a material other than an oxide film as the gate insulating film of a p-channel MOS transistor, CMOS transistor, or MNOS, etc.
The same applies to type transistors.

As described in detail above, according to the present invention, the low concentration impurity diffusion region of the LDD structure maintains the drain electric field relaxation effect while preventing the decrease in current drive capability due to the increase in parasitic resistance due to the diffusion region. It is possible to provide reliable MIS type semiconductor devices such as MO8 type semiconductor devices.

[Brief explanation of the drawing]

FIG. 1 (al to tel are LDDs in the embodiment of the present invention.
A cross-sectional view showing a manufacturing process for obtaining an n-channel MO8) transistor having a structure, FIGS. 2(a) to 2(cl) are cross-sectional views of comparison rows. ...Field oxide film 3...Gate oxide film 4...Gate electrode 5, , 5...n-type diffusion region (first diffusion region)
6...First insulating film layer on the side wall of the gate electrode 7...Second insulating film layer on the side wall of the gate electrode 81.8□...N+ type diffusion region (second diffusion region) 98, 9□ ...N-type diffusion region (third diffusion region) 11 ...Al wiring agent Patent attorney Noriyuki Chika Yudo Kikuo Takehana

Claims (1)

[Scope of Claims] A substrate including a semiconductor substrate of a first conductivity type, source and drain regions of a second conductivity type provided electrically isolated from each other on the surface of the substrate, and a channel region between these regions. A method for manufacturing an MIS type semiconductor device including a gate electrode provided on the surface with an insulating film interposed therebetween, wherein after forming the gate electrode, using the gate electrode as a mask, a low concentration is applied to the source and drain regions. By forming a first impurity diffusion layer region, depositing a first insulating film layer and a second insulating film layer, and performing anisotropic etching, the first impurity diffusion layer region is formed on the side wall of the gate electrode. Insulating film layer, second
a first insulating film layer and a second insulating film layer on the side wall portion of the gate electrode and the gate electrode as a mask to the source and drain regions from the first impurity diffusion region. After forming a high concentration second impurity diffusion region and removing the second insulating film layer, using the gate electrode and the sidewall adhering portion of the first insulating film layer as a mask, a step of forming a third impurity diffusion region in a drain region at a higher concentration than the first impurity diffusion region and at a lower concentration than the second impurity diffusion region. manufacturing method.