JPH02237024A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PURPOSE:To restrain the re-distribution of a group V atom from occurring for making a semiconductor device highly integrated by a method wherein at least one layer comprising a V-group impurity and another impurity in high electric negative degree or a halogen element impurity is contained in a polycrystal Si, a high melting point metal or a silicide of a high melting point metal. CONSTITUTION:An N<+> diffused region 3 is formed of an N<+> diffused layer comprising V-group impurity elements such as As, P, etc., and the impurities such as F, Cl, O, Br, S, I, N, etc., in high electric negative degree. Since such elements as F, O, Cl, Br, S, I, N, etc., diffuse faster than the group V elements, the former elements can be located in a position wherein atoms are stabilized i.e., only inside the V-group element profile. Furthermore, the re-distribution of the group V element in a wiring can be restrained from occurring by containing the impurity in high electric negative degree in a polycrystal Si, a high melting point metal or a silicide of the high melting point metal.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices and semiconductor device manufacturing methods, particularly in bipolar transistors, MISFETs (insulated gate field transistors), or LSIs (large-scale semiconductor integrated circuit devices). This article relates to effective semiconductor devices and semiconductor device manufacturing methods. Moreover, the present invention
Regarding semiconductor devices having T (Thin Film Transistor) and high resistance elements. [Prior Art] In semiconductor integrated circuit II (IC), particularly in BiCMOS (bibolar complementary metal oxide semiconductor) integrated circuit technology, a P-well region is generally formed on an N-type semiconductor substrate, and the P-well region is N-channel MISFET in the area
is being formed. For example, Japanese Patent Application Laid-Open No. 57-130461 discloses a technique of utilizing this P-well region to form a bipolar transistor in place of a CMOS inverter with a small driving capacity in the final stage of the output section to configure an output transistor. It is known from public notices, etc. That is, in a CMOS integrated circuit, a P well region is formed on an N-type semiconductor substrate at the same time as a P well region is manufactured.
A type diffusion region is formed, and an N0 region, which will become an emitter region, is formed on this P-type diffusion region at the same time as the source and drain regions are formed. This attempts to construct an NPN type bibolar transistor on a CMOS integrated circuit without changing the process at all.

Furthermore, Japanese Patent Application Laid-Open No. 58-207671 discloses a semiconductor device having a base diffusion region on one main surface of a semiconductor substrate and an emitter diffusion region formed on a part of the surface. A semiconductor device characterized in that the part that becomes the emitter diffusion mask consists of a thin semiconductor oxide film and a polycrystalline semiconductor film formed thereon, and the part itself forms the peripheral part of the emitter contact. is disclosed. Further, in Japanese Patent Application Laid-Open No. 60-38856, an insulated gate electrode is formed of a polysilicon layer or metal silicide, and a source/drain diffusion layer is formed using this gate electrode and a field oxide film as a mask. In a method for manufacturing a semiconductor device in which wiring and electrodes of each transistor are formed by a second polysilicon layer with an insulating film interposed on the gate electrode, a base, which will become a base region, is placed in advance at an appropriate position on the substrate. A part of the insulating film on this base diffusion layer is removed at the same time as contact holes for providing source/drain electrodes made of polysilicon are formed, and then a second polysilicon layer is attached. A method of manufacturing a semiconductor device is disclosed in which an emitter diffusion layer is formed by thermal diffusion of impurities doped into the second polysilicon layer. In each of the semiconductor devices described above, when forming the N-type diffusion layer, a single group V impurity of the periodic table, such as As(
It was formed by implanting ions such as arsenic), P (phosphorus), and Sb (antimony). Furthermore, conventionally, the N-type diffusion layer in silicon contains V group elements, such as P or As.
had been introduced. However, when group V elements were present at a high immersion degree, secondary defects were present in the high purity region due to heat treatment. For example, add As to a silicon substrate in a size of 4X10"cm".
2 implantation and annealing, the single crystal and amorphous (a-C) interface region at the time of implantation and A s ? J1 degree is 5x
Secondary defects were present in areas where the depth was 20"am-" or more. Furthermore, the redistribution of As occurred due to accelerated diffusion due to the high concentration of As, resulting in a large redistribution of As. Therefore, the secondary defects impair the reliability of semiconductor devices, and the redistribution of As hinders the miniaturization and high integration of semiconductor devices. Other V group originals, p,
Similarly, secondary defects and redistribution exist for Sb. In addition, conventionally, for example, M in an IC using a silicon substrate
In an ISFET, a gate insulating film made of a silicon oxide film is formed by thermally oxidizing a silicon main plate, and a gate electrode made of, for example, polycrystalline silicon is formed on the gate insulating film. However, the interface between the gate insulator and the gate insulator or the gate insulator and the gate electrode is unstable, and the electrical characteristics of the MISFET become unstable during IC operation. for example,
Deterioration of threshold voltage and current gain coefficient became a problem. Conventionally, the above interface was stabilized by H2 forcin gas sintering, but the Si-H bond was weak and M
It has not been possible to completely suppress the deterioration of ISFET characteristics. In addition, conventional TPTs and high resistance elements used in LSIs such as TPTs used in LCD televisions and SRAMs are simply polycrystalline silicon or amorphous silicon into which group ■■ group or group V element impurities are introduced. silicon lfl
li is used. Furthermore, in the past, for example, Ti (titanium), Mo (molybdenum), W (tungsten), Ta
(tantalum), Pt (platinum), Pd (palladium)
, Zr (zirconium), or other metal silicide layers are used for part of the gate electrode, source, and drain regions. However, the diffusion of group V impurities (P and As) in the silicide layer is very fast, and it is impossible to selectively dope group V impurities, for example, only into the N-type region, through the silicide by heat treatment during LSI manufacturing. Met.
For example, in a gate electrode (poly cide) made of a two-layer stack of polycrystalline silicon and metal silicide, group V element ions (As) selectively implanted into the N-type MISFET region penetrate through the metal silicide through subsequent heat treatment. It diffuses and reaches the P-type MISFET region, doping As into the polycrystalline silicon of the gate electrode in the P-type region and deteriorating the electrical characteristics of the P-type MISFET. [Problems to be Solved by the Invention] As described above, secondary defects are formed in the high concentration region of the diffusion layer made of a high concentration group V impurity. Furthermore, high-temperature group V impurities diffuse at an accelerated rate during annealing, making it difficult to form shallow junctions. Furthermore, the redistribution of group V elements in polycrystalline Si, high melting point metals, and high melting point metal silicides is severe, making it impossible to miniaturize interconnects and elements. Furthermore, when forming an N-type diffusion layer by ion implantation, there is a problem in that device performance deteriorates because secondary defects also exist at the interface between the amorphous and single crystal at the time of implantation. The present invention provides a semiconductor device having a shallow N-type diffusion layer that does not cause secondary defects in a semiconductor including at least one N-type diffusion layer, and a method for manufacturing the same.
i. The purpose is to suppress the redistribution of group V atoms in refractory metal silicides and refractory metals, and to realize higher integration of semiconductor devices. Another object of the present invention is to provide a semiconductor device in which the interface between the gate electrode and the gate insulating film and the interface between the gate electrode and the gate insulating film are stabilized, and the electrical characteristics of the MISFET do not deteriorate during IC operation. In addition, high-definition TVs and L
As SI becomes more highly integrated, elements using polycrystalline silicon or amorphous silicon are miniaturized, which poses the following two problems. First, the redistribution of group V or group III impurities doped into the silicon thin film was large, resulting in short-circuiting of high-resistance parts in high-resistance elements, and short-circuiting of source and drain regions in TPTs. This made it difficult to repair the element. Second, the interface between the TPT gate insulating film and the silicon thin film is unstable due to silicon dangling bonds, and electrical characteristics such as On current and threshold voltage deteriorate during operation. There was also a reliability problem in that the resistance in the high resistance region also changed. It is an object of the present invention to solve the above two problems and provide a semiconductor device in which a polycrystalline silicon or amorphous silicon thin film is formed, which is miniaturized and highly reliable. Further, the purpose of the present invention is to compensate for such conventional drawbacks, to suppress the diffusion of group V impurities in the high melting point metal silicide, and to suppress the CMI generated by the redistribution of group V impurities through the high melting point metal silicide.
It is an object of the present invention to provide a semiconductor device having a structure that avoids SLSI defects. [Means for Solving the Problems] That is, the present invention is directed to amorphous, polycrystalline or single crystal silicon, Ti, Mo, W, Ta. Pt
, Pd, Zr and other high melting point metals, or silicides of these high melting point metals, group V impurities and highly electronegative impurities or halogen element impurities, such as F, Cl,
A semiconductor device characterized in that it includes at least one layer consisting of elemental impurities such as O, Br, S, I, N, etc., and a profile of the highly electronegative impurity or halogen element impurity. is a semiconductor device characterized by having a shallower concentration and lower concentration than the Group V impurity. Furthermore, the present invention provides a method for implanting group V impurity ions into amorphous, polycrystalline, or single crystal silicon, a refractory metal, or a silicide of the refractory metal, before, after, or simultaneously with the ion implantation. Highly concentrated elemental ions or halogen elemental ions, such as F, O,
A method for manufacturing a semiconductor device characterized by implanting Cl, Br, S, f, N, etc. and annealing, and the profile at the time of implanting the impurity with high electronegativity or the halogen element impurity is V. This is a method for manufacturing a semiconductor device characterized by the distribution of impurity ions deeper than the amorphous layer generated during implantation of group impurity ions. The present invention relates to the combination of group V impurity elements (such as S b + A s + P, etc.) and highly electronegative impurity elements or halogen element impurities ( F
+ Or CL Br. s, x, N
etc.) to form covalent or ionic bonds, etc., and to avoid group V impurity elements from troubling the interstitial silicon, accelerated propagation caused by interstitial silicon and secondary defects of the interstitial silicon type. This is thought to suppress the Also, compared to the V group original cable, F+ O+ CL Br
Since elements such as , S, I, and N spread rapidly, annealing allows these atoms to exist only in stable positions, that is, within the group V element profile. Furthermore, by including impurities with high electronegativity in polycrystalline Si, high-melting point metals, and silicides of high-melting point metals, redistribution of group V element groups in wiring is suppressed. Further, the present invention is characterized in that F atoms or the like are present at the interface between the gate insulating film and the substrate or between the gate electrode and the gate insulating film. Since F combines with Si to form a strong Si-F bond, there are no dangling bonds at the interface between SiO2 and S, resulting in a stable interface. Furthermore, the present invention provides high-electronegativity compounds such as F, Q, Cl, Br,
By including impurities such as S, I, and N,
It is characterized by suppressing the redistribution of group V elements in high melting point metal silicide. Although the mechanism is not clear, it is thought that, for example, the diffusion of As in TiSia is redistributed through the dangling bonds of silicon existing at the grain boundaries of TiSi2. On the other hand, by including F, which has a high electronegativity, in TiSi2, grain boundary silicon dangling bonds can be formed because the bond energy of Si-F is large.
It is thought that F and nodule distribution are suppressed. [Example] (Example 1) Fig. 1 is an explanatory diagram of a longitudinal section showing the principle structure of a pibolar element according to the present invention, and Figs. 2(a) to 2(i) are illustrations of a bipolar CMISIC according to the present invention. It is a process cross-sectional explanatory diagram showing an example of a manufacturing process. In the figure, 1 is an N-type semiconductor substrate that becomes a collector, 2 is a P-type diffusion region that is a base, 3 is an N0-type diffusion region that is an emitter, 4 is a thin oxide film, 5 is an A1 electrode, and 6 is a thin oxide film ( 7 is a polycrystalline semiconductor 1101 (polysilicon film), 8 is a PSG (phosphorus silicate glass) film, 9 is an A1 electrode that becomes a pace emitter electrode, 10
is a P° type silicon substrate, 11 is an N9 type buried layer, 12 is an element isolation insulating film, 12' is an isolation P layer, 13 is an N type epitaxial layer, 14 is an isolation oxide film, and 15 is a P type well. , l6 is a mask, 17 is a base region, 18a, 18b are thin oxide films, 19a, 19b are polysilicon films, 20 is a mask, 21 is an N0 emitter, 22
is a polysilicon gate, 23 is a mask, 24 is a P0 source/drain, 25 is a P'' base contact, 26 is a mask, 27 is an N0 source/drain, 28 is a PSG film, 29 is an A1 electrode (wiring), 30 is an N4 collector contact portion.As shown in FIG. 1, in the semiconductor device of the present invention, the N0 type diffusion region 3 is composed of V group impurity elements such as As and P, and F, Cl, and F, which have high electronegativity. O,
N0 consisting of impurities such as Br, S, I, N, etc.
It is formed by forming a type diffusion layer. Next, the manufacturing process of the semiconductor device of the present invention is shown in FIGS. 2(a) to 2(a).
Explain step by step according to (i). (a) First, an N″-type buried layer 11 is embedded in one main surface of a P-type silicon substrate (wafer) 10, and an N-type silicon layer is separated by an isolation P layer 12′ and an element isolation insulating film 12. The N-type epitaxial layer 13 has a specific resistance of 1Ω and a thickness of 3~
Grow epitaxially to about 10 μm. At this time, if the N-type buried layer 11 is composed of a group V element and an element with high electronegativity, such as As and F or Sb and F, or a halogen element, the epitaxially grown silicon layer 13 will be defect-free. , and a good substrate without redistribution of the N4 type buried layer 11 is obtained. Figures 8(a) and (b) are As
, 4E15cm-'', 80keV injection sample (b) and As,4E15cm-2.80keV after injection,
F, 35 ke V, 2 E 15cm-
``For the additionally injected sample (a), 900@C,
Cross-sectional TEM observation after 15 minutes of N2 annealing.
There are secondary defects in the sample in which only As is implanted, and there are no secondary defects in the sample in which F is additionally implanted according to this example. The N''' type buried layer 11 can also be formed by high-energy ion implantation, for example, MeV ion implantation of As or P. At this time, a highly electronegative element (for example, F) is added together with group V ions to M e V By implanting ions, it is possible to form a diffusion layer 11 in which defects with little redistribution are suppressed.After this, an isolation oxide layer 14 is formed on the surface of the N-type epitaxial Si layer 13 by low-temperature selective oxidation. Separate into smaller regions. [Figure 2 (a)] In Figure 2, ■ is the region where the bibolar element is formed, and II is the region where the MIS element is formed. In some areas, the PM well 15 was formed to a thickness of 4 μm by selective B (boron) impurity ion implantation.
Form to a certain depth. (b) A mask 16 is formed by photoresist processing, and a P-type region 17 serving as a base is formed to a depth of 1.5 μm by B deposit diffusion on the surface of the N layer in a part of the region.
[FIG. 2(b)] (C) The mask material and surface oxide film on the surface are once removed, and gate oxidation is performed to form thin thermal oxide films 18a and 18b on the entire surface. At this time, the MIS side (■!) which becomes the gate part has a thickness of 100A to 1
An oxide film 18a having a thickness of about 110A to 1300A is formed on the surface of the P-type region 17 serving as the base, while an oxide film 18b having a thickness of, for example, about 110A to 1300A is formed on the surface of the P-type region 17, which is thicker than the gate side due to oxidation promotion by B. [FIG. 2(C)] (d) Silicon produced in a vapor phase is deposited on the entire surface to form polysilicon films 19a and 19b. Thereafter, the polysilicon film 19b on the bipolar side (I) is removed by photoresist processing, leaving the polysilicon film 19b only in the periphery of the emitter.
[Fig. 2(d)] (e) With a mask 20 formed by photoresist processing on the surface of the P-type base region 17 except for the emitter portion, an A of about 4xlO "am-" is applied.
After ion implantation of impurities such as s (arsenic), F, CLO, Br, S, which have high electronegativity
Of I and N, for example, F is ion-implanted at 2xlO"cm-", diffused, and annealed at 900@C for 15 minutes.
An N9 type emitter region 21 is formed and an N'' collector contact region 32 is formed.If the As implantation energy is set to 80KeV and the F implantation energy is set to 40KeV, the distribution of F at the time of implantation will be the same as that at the time of implantation. The As injection layer according to this example has no secondary defects as shown in FIG. 8(a).As shown in FIG. Figure 9 shows As,' 80KeV,
Rapid Thermal Annealing at 1020"C for the sample in which only 4E15cm-2 was injected and the As and F injected sample according to this example.
After (RTA), 650@C furnace
As after Annealing (FA) treatment
Comparing profiles. The F-additionally implanted sample according to this example has small As redistribution and enables shallow junction formation. Furthermore, after heat treatment at 900°C for 15 minutes, F was distributed only inside the As profile. At this time, MIS
The resistance is lowered by diffusing a high concentration of N-type impurity into the polysilicon layer on the side (II This is effective in high-resistance wiring layers used in SRAMs, etc., but if As and F are implanted into the diffusion layer region of polycrystalline silicon, As will diffuse in the lateral direction (planar direction) of polycrystalline silicon. In addition, gate electrodes containing silicide or high-melting point metals, such as pOly cide, can be
In the case of structures 19a and 19b, in this example, the lateral redistribution of group V impurities in the polycide wiring layer is suppressed by the presence of impurities with high electronegativity. Therefore, no problems occur due to redistribution of group V elements in the silicide. '[21st! I(e)] Note that this N-type impurity deposition may be performed immediately after the polysilicon film is formed in step (d). (f) MIS
Gate photoetching is performed on the polysilicon film on the side (II) to expose the semiconductor surface of the source/drain portion and form a polysilicon gate 22. After that, with the mask material 23 formed on a part of the surface, B
(boron) impurity is deposited or ion-implanted and diffused to form a P"tl region 24 which becomes a self-lined source/drain with a gate on the surface of the N layer in region II to a depth of 0.1 to 0.8 μm. On the other hand, a high concentration P1 layer 25 for a base contact is also formed on the base surface of the bibolar side region.
[FIG. 2(f)] (g) After exposing only the top of the P-well 15 on the MIS side (region II) and covering the rest with a mask material 26, As is ion-implanted in the same manner as in the step (e) above. Then, F is implanted, diffused and annealed, and P
N" regions 24, which are self-lined with gates and serve as sources and drains, are formed on the well surface to a depth of 0.05 to 0.8 μm. Here, even if P and F are implanted, there are few secondary defects. It is possible to form shallow junctions with little redistribution.Figure 10(a)
, (b), FIG. 5E15
cm-” injection sample (b) and 11p, 40KeV,
5E15cm-' after injection, IIF, 35KeV, 2E1
5 cm-” for sample (a) injected, 700@
P profile and cross section T after 0.180 minutes N2 annealing
This is an EN image. In the 31P and laF implanted samples according to this example, secondary defect growth is suppressed and P tail redistribution is small. Therefore, a shallow bond with fewer defects is formed. [Figure 2 (g)]
(h) PSG (phosphorus silicate glass) film 28 on the entire surface
After depositing, contact photoetching is performed.
[Figure 2 (h)] (i) Evaporating (or sputtering) Al and patterning and etching it,
Form electrodes (wiring) 29 in ohmic contact with each region. [Figure 2(i)] Through the above process, a Bi-CMISIC having an NPN transistor with a microscopic emitter and a short channel MISFET is completed. Although the present invention has been described as being applied to a CMISIC having an NPN transistor and a short channel MISFET, the present invention is not limited to this embodiment. ,
The present invention can be applied to any semiconductor device made of metal or metal silicide wiring layers. Furthermore, silicon is not limited to polysilicon and single crystal silicon, and of course may be amorphous silicon.
Moreover, the characteristics shown in FIGS. 8 to 11 are the same as those of other examples 2 to
The same can be said for 5. In addition, in this example, the V group impurity was 40 k e V
, 80 keV energy was introduced with high purity. However, in the case of a low concentration, if the introduced energy is set to 100 keV or more, more interstitial Si can be produced, and the same effect as in this example can be obtained. In conventional semiconductor devices, a single group V impurity such as As is used to form an N-type diffusion layer.
By implanting ions such as , P, etc., a diffusion layer consisting of a high concentration of group V impurities was formed, but the redistribution of group V element impurities due to accelerated diffusion was large, making it difficult to form shallow junctions. ．． Also, polycrystalline silicon, poly cide
The redistribution of Group V element impurities in the wiring was also large, making it difficult to miniaturize the wiring. Furthermore, secondary defects are formed in the high droplet density region, and when an N-type diffusion layer is formed by ion implantation, secondary defects are present in the high droplet density region as well as in the amorphous and single crystal interface region at the time of implantation. However, according to the semiconductor device of the present invention, it is possible to provide a semiconductor device comprising an N-type diffusion layer with a shallow junction and a method for manufacturing the same, which does not cause secondary defects. becomes possible. In addition, in this example, the redistribution of group V impurities in polycrystalline silicon, metal, and silicide interconnections is suppressed, so that the miniaturization and high Promote integration. (Example 2) In this example, As, which is a group V element most commonly used in the N-type diffusion layer, will be explained, but the same is qualitatively true for P and Sb elements. Further, in the examples, F, which has the highest electronegativity, will be described, but the same effect can be obtained with other highly electronegative Cl, O, N, Br, I, and S, although to a lesser extent. A high concentration of As is implanted (2) into a silicon (100) substrate.
1 x 10"cm-"), F is implanted at an energy that almost overlaps with the As implantation profile. This F
may be performed before As injection. Figure 3 (a) - (c
) is a cross-sectional view of the process flow for forming source and drain regions of MISFET. On the silicon substrate 31, a gate electrode 35, a gate insulating film 33, a sidewall insulating film 34, and a source are separated by an insulating film 32 for element isolation such as Side.
MISFET consisting of drain region 38 (Fig. 3(C)
))It is shown. In the source and drain regions 38,
In FIG. 3(a), As36 is selectively treated with high dose energy and amount (for example, 80KeV 4xlO ”c
m-"). Then, in FIG. 3(b),
Selectively implant F (fluorine) 37 into the same region (for example,
35KeV 2xlO"cm-"), followed by heat treatment (
For example, at 900°C for 5 minutes in N2 atmosphere). As a result, source and drain regions 38 are formed. Therefore, FIG. 3(C) shows a MISFET in which the source and drain regions 38 have N-type diffusion layers made of two types of impurities, high concentration As and F. Here, Cl, O, Br. s
, LN, and other highly electronegative elemental impurities can also have the same effect, albeit to a lesser extent. In the manufacturing method according to the present invention, since F suppresses the high-concentration accelerated diffusion of As and the generation of secondary defects, it is possible to produce A
An N-type spreading layer 38 with small s redistribution is obtained. For this reason, MI
It becomes possible to miniaturize SFETs and provide highly reliable and highly integrated LSI semiconductor devices. (Embodiment 3) FIG. 4 shows a sectional view of another embodiment of the semiconductor device according to the present invention. An element isolation insulating film 42 is provided on the silicon substrate 41.
MISFET is formed separated by
The ET is formed from a source and drain region 43, a gate insulating film 44, and a gate electrode 45. F atoms exist near the interface 47 between the gate insulating film 44 and the silicon substrate 41. This can be obtained by annealing in an atmosphere containing F after forming the gate insulating film 44 or by implanting ions containing F. In addition, the gate electrode 45 and the gate insulating film 4
F atoms also exist near the interface with 46. This F atom is particularly effective when the gate electrode is made of polycide or polysilicon. F in this region 46 can be introduced by annealing in an atmosphere containing F or implanting ions containing F after forming the gate electrode 45. Furthermore, if F is introduced after forming the gate electrode 45 and high-temperature annealing of the source and drain regions 43, Si-
The bond of F is stable. Further, after forming the wiring layer connecting the MISFETs, for example, by implanting MeV ions of F atoms, the interface 46 is
Alternatively, it is also possible to introduce F into 47. In addition to F atoms, impurities with high electronegativity like F atoms or halogen element impurities, such as Cl,
O, Br, S, I, N, etc. are also used in the same way. According to the present invention, F atoms are present at the interface 46 between the gate electrode 45 and the gate insulating film 44 or at the interface 47 between the gate insulating film 44 and the silicon substrate 41. These interfaces are Si-
Due to the strong bond of F, there are no dangling bonds and it is stable. Therefore, the electrical characteristics of the MISFET do not change even during IC operation, making it possible to provide a highly reliable semiconductor device. (Example 4) FIG. 5 is a sectional view of the TPT according to this example. This figure shows an amorphous silicon or polycrystalline silicon thin film 52 formed on a glass or quartz substrate 51, a gate electrode 55, a gate insulating film 54, source and drain regions 5
This shows a MISFET consisting of 3. F ion implantation or F
F atoms are included due to annealing in an atmosphere containing F atoms. As mentioned above, F atoms are present in the source and drain regions 5.
In order to suppress the redistribution of impurities of No. 3, such as P and As,
No short circuit occurs even if the channel length L+ is reduced. Also,
The interface between the gate insulating film 54 and the silicon thin film 52 is also stabilized by the presence of F. FIG. 6 shows the SRA according to this embodiment.
It is a cross-sectional view of high-resistance polycrystalline silicon used for M.
An interlayer insulating film 62 is formed on the silicon substrate 61, and a polycrystalline silicon thin film 63 is formed on the interlayer insulating film 62. It is connected to the wirings A and B through the impurity doped region 64. The resistance is determined by the length of the region not doped with impurities, ie, L2. In this embodiment, the high resistance region 63 or the impurity doped region 64 contains F atoms by F ion implantation or annealing in an atmosphere containing F. Conventionally, when L2 was reduced to 2 μm or less, short circuits occurred due to redistribution of impurities during heat treatment in the post-process. In other words, impurities have diffused into the area that should be a resistor, making it no longer a resistor. However, the introduction of F suppresses the redistribution of impurities such as B, P, and As, and even when L2 is miniaturized to submicron size, short circuits do not occur and a stable high-resistance region can be obtained. In addition to the F atom, impurities with high electronegativity similar to the F atom or halogen element impurities, such as Cl, O
, Br, S, I, N, etc. are also used in the same way. As explained above, according to this embodiment, it is possible to produce a TPT element and a high-resistance element made of polycrystalline or amorphous thin film, which are miniaturized to submicron scale, and
Moreover, a highly reliable semiconductor device can be provided. (Example 5) FIG. 7 is a cross-sectional view of a CMISFET semiconductor device according to this example. On the silicon substrate 71, a P-type MISFE is separated by an element isolation insulating film 72 made of SiO2 or the like.
T (Pch) and N-type MI SFET (Nch) are formed. Each FET is made of polycrystalline silicon (74A, 74B) and TiSi2 (75A, 75B).
) The *NMMISFET is connected with a poly side gate electrode consisting of a gate insulating film 73A,
polycide electrodes (74A, 75A) and sources,
It consists of a drain region 76A. And P-type MISFE
T consists of gate insulation #73B, poly side electrodes (74B, 75B), and source and drain regions 76B. Gate electrodes 74A and 75 of N-type MISFET
A contains a high concentration of group V elements, such as P or As. On the other hand, in the P-type MISFET, the gate electrodes 74B and 75B have 11! Contains group elements such as B. Conventionally,
74A. P or As contained in 75A spread to TiSia 75B in the subsequent heat treatment process and was further expelled to polycrystalline silicon 74B, causing a shift in the threshold voltage of the P-type MISFET and unstable electrical characteristics.

On the other hand, in this example, since F is injected into TiSi275A, P or As in 74A and 75A is
Redistribution is suppressed and does not spread to 75B, 74B, 75
B has no P or As. Therefore, P-type MI
The SFET electrode is made of polycrystalline silicon 74B with a constant carrier concentration, and the P-type MISFET has stable electrical characteristics with less fluctuation. Other high melting point metal silicides such as Mo, W, T
The same can be said for silicides such as a, Pt, Pd, and Zr. Furthermore, the same can be said for the high melting point metal itself, not the high melting point metal silicide. In addition to F, CL
The same effect can be obtained by using highly electronegative elemental impurities such as O, Br, S, I, and N, although the degree of effect varies. From the above, according to this example, Vt! in the high melting point metal silicide! A semiconductor device can be obtained in which redistribution of A impurities is suppressed and CMISLSI defects caused by redistribution of group V elements are avoided. As described above, in Examples 1 to 5, among the impurities with high electronegativity or the halogen element impurities, F was particularly found in other CI. O, Br, S,
It has a greater effect than I or N. (Effects of the Invention) When forming an N-type diffusion layer in a conventional semiconductor device, a single group V impurity, for example, an ion such as As or P, is implanted to form a diffusion layer made of a high concentration group V impurity. However, the redistribution of group V element impurities due to accelerated diffusion was large, making it difficult to form shallow junctions.Furthermore, the redistribution of group V element impurities in polycrystalline silicon and polycide wiring was also large, and the wiring In addition, secondary defects were formed in the high concentration region, and when forming the N!!!!! diffusion layer by ion implantation, the amorphous and monotonous materials formed during implantation were mixed together with the high immersion region. In the crystal interface region,
Due to the presence of secondary defects, a problem occurred in which device performance deteriorated, but the semiconductor of the present invention? According to the apparatus, it is possible to provide a semiconductor device including an N-type diffusion layer with a shallow junction that does not cause secondary defects, and a method for manufacturing the same. In addition, in the present invention, the redistribution of group V impurities in polycrystalline silicon, metal, and silicide wiring is suppressed, so it is possible to suppress the redistribution of group V impurities in polycrystalline silicon, metal, and silicide wiring, so
! Promoting miniaturization and high integration of poles.

[Brief explanation of drawings]

Figure 1 is a longitudinal section showing the basic structure of the bibolar element according to the present invention. FIGS. 2(a) to 2(i) show a bibolar MO according to the present invention.
3 is a process cross-sectional view showing Example 1 of the SIC manufacturing process. FIG. 3(a) to 3(C) are manufacturing process cross-sectional views showing Example 2 of the method for manufacturing a semiconductor device according to the present invention. ￥44 The figure shows Example 3 of the structure of a semiconductor device according to the present invention.
FIG. 5 and 6 are principal cross-sectional views, respectively, showing a fourth embodiment of the structure of a semiconductor device according to the present invention. FIG. 7 is a main cross-sectional explanatory diagram showing a fifth embodiment of the structure of a semiconductor device according to the present invention. FIGS. 8(a) and 8(b) are explanatory diagrams using photographs showing the state of crystals due to the introduction of As impurities according to the embodiment of the present invention and the conventional technology. FIG. 9 is a diagram showing the relationship between As impurity concentration and depth according to the embodiment of the present invention and the conventional technique. Figure 10(a)
, (b) is an explanatory diagram using photographs showing the state of crystals due to the introduction of P impurity according to the embodiment of the present invention and the conventional technology. FIG. 11 is a diagram showing the relationship between the concentration and depth of P impurities according to the embodiment of the present invention and the conventional technique. In the figure, 1
2 is the N-type semiconductor substrate which becomes the collector, and 2 is the P which becomes the base.
3 is an N''' type diffusion region which becomes an emitter, 4
is a thin oxide film, 5 is an A1 electrode, 6 is a thin oxide III (gate oxide M), and 7 is a polycrystalline semiconductor film (polysilicon film)
, 8 is PSG (phosphorus silicate glass) nl, 9 is A1 electrode which becomes the base emitter electrode, 10 is P-type Si
11 is an N2 type buried layer, 12, 32, 42.72 are element isolation insulating films, and 12' is an isolation PW. 1
3 is an NW epitaxial layer, 14 is an isolation oxide film, 15 is a P-type well, 16 is a mask, 17 is a base region, 18a, 18b are thin oxide films, 19a. 19
b is a polysilicon film, 20 is a mask, 21 is an N4 emitter, 22 is a polysilicon gate electrode, 23 is a mask, 2
4 is the P6 source and drain region, 25 is the P0 base contact, 26 is the mask, 27 is the N source and drain region, 28 is the PSG film, 29 is the A1 electrode (wiring),
30 is the N0 collector contact portion, 31.41, 61.
71 is a silicon substrate, 33, 44, 54,
73A and 73B are gate insulating films, 34 is a sidewall insulating film, 35. 45, 55.74A, 74B, 75
A, 75B are gate electrodes, 36 is As ion, 37 is F
ions, 38, 43, 53, 76A, 76B are sources,
Drain region, 46 near the gate electrode-gate insulating film interface, 47 near the gate insulating film-silicon substrate interface, 5
1 is a glass substrate, 52, 63 is polycrystalline silicon, 62 is an interlayer insulating film, and 64 is an impurity doping region. The same reference numerals in each figure indicate the same or equivalent parts.

Claims (24)

[Claims] (1) High melting point metals such as amorphous silicon, polycrystalline silicon, single crystal silicon, Ti, Mo, W, Ta, Pt, Pd, Zr, etc. or silicides of the high melting point metals contain a group V impurity. 1. A semiconductor device comprising at least a region containing one impurity and a second impurity made of a highly electronegative impurity or a halogen element impurity. (2) The semiconductor device according to claim 1, wherein the second impurity consisting of the highly electronegative impurity or the halogen element impurity is F. (3) The first impurity consisting of group V impurities is P, A
3. The semiconductor device according to claim 1, wherein the semiconductor device is made of s or Sb alone, or a combination thereof. (4) The semiconductor device according to claim 1 or 3, wherein the second impurity is Cl, O, Br, S, I, or N. (5) The profile of the second impurity is shallower than the profile of the first impurity, and the concentration of the second impurity is lower than the concentration of the first impurity. or 4. The semiconductor device according to 4. (6) The peak concentration of the first impurity is approximately 10^2^0c
Claims 1, 2, and 3 characterized in that it exceeds m^-^3.
, 4 or 5. The semiconductor device according to . (7) In high melting point metals such as amorphous silicon, polycrystalline silicon, single crystal silicon, Ti, Mo, W, Ta, Pt, Pd, and Zr, or silicide of the high melting point metals,
Before, after, or simultaneously with the introduction of the first impurity made of group V impurities by ion implantation etc., the second impurity made of highly electronegative impurities or halogen element impurities is introduced.
A method for manufacturing a semiconductor device, comprising the steps of introducing an impurity, annealing, and thereby forming an N-type impurity region. (8) The method for manufacturing a semiconductor device according to claim 7, wherein the second impurity is F. (9) The first impurity is P, As or Sb alone;
9. The method of manufacturing a semiconductor device according to claim 7, wherein the method is a combination thereof. (10) Claim 7 or Claim 9, wherein the second impurity is Cl, O, Br, S, I, or N.
A method of manufacturing the semiconductor device described above. (11) Claims 7, 8, and 9, wherein the profile of the second impurity is shallower than the profile of the first impurity, and the concentration of the second impurity is lower than the concentration of the first impurity. Alternatively, the method for manufacturing a semiconductor device according to 10. (12) The peak concentration of the first impurity is approximately 10^2^0
Claims 7, 8, characterized in that it exceeds cm^-^3,
12. The method for manufacturing a semiconductor device according to 9, 10 or 11. (13) Claims 7, 8, 9, 10, 1, wherein the profile when introducing the second impurity is distributed deeper than the amorphous region generated when introducing the first impurity.
13. A method for manufacturing a semiconductor device according to 1 or 12. (14) In a semiconductor device in which a gate insulating film provided on a semiconductor substrate is made of a silicon nitride film or a silicon oxide film, a first region near the interface between the gate insulating film and the semiconductor substrate and the gate insulating film A semiconductor device characterized in that a first impurity made of a highly electronegative impurity or a halogen element impurity is present in a second region near an interface between the semiconductor device and a gate electrode provided thereon. (15) The semiconductor device according to claim 14, wherein the first impurity is F. (16) The semiconductor device according to claim 14, wherein the first impurity is Cl, O, Br, S, I, or N. (17) Having an element made of a silicon thin film such as a polycrystalline silicon thin film or an amorphous silicon thin film into which a first impurity consisting of a highly electronegative impurity or a halogen element impurity is introduced on an insulating substrate or an insulating film. A semiconductor device characterized by: (18) The semiconductor device according to claim 17, wherein the element is a high resistance element comprising a region of the silicon thin film into which group III or group V impurities are introduced and a high resistance region. (19) The semiconductor device according to claim 17, wherein the element is a thin film transistor having a source, a drain region, and a channel region in the silicon thin film. (20) The semiconductor device according to claim 17, 18, or 19, wherein the first impurity is F. (21) The semiconductor device according to claim 17, 18, or 19, wherein the first impurity is Cl, O, Br, S, I, or N. (22) At least a part of each of the source, drain region, or gate electrode of the N-type MISFET of the complementary MIS semiconductor device contains a first impurity consisting of a highly electronegative impurity or a halogen element impurity. ,
A semiconductor device comprising a silicide layer of a high melting point metal such as W, Ta, Pt, Pd or Zr. (23) The semiconductor device according to claim 22, wherein the first impurity is F. (24) The semiconductor device according to claim 22, wherein the first impurity is Cl, O, Br, S, I, or N.