JPS6035563A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To enable to easily form a well layer having a concentration distribution of reverse gradient to prevent latch-up by a method wherein an N type impurity is introduced to the entire surface of an Si substrate, and further a P type impurity is introduced at this region selectively into the substrate, thereafter the P type and N type impurities which have been introduced are thermally diffused into the substrate at the same time. CONSTITUTION:The region other than the region for forming a P type well layer is selectively covered with a photo resist film 23 in order to form the well layer, and, with the film as a mask, the P type impurity, e.g., boron to form the well layer is introduced via Si oxide film 21. In the region for forming the well layer, the layer 24 of the P type impurity, e.g., boron and the layer 22 of the N type impurity, e.g., arsenic are mixed. Next, the film 23 is removed, and the P type impurity, e.g., boron and the N type impurity, e.g., arsenic which have been introduced are thermally diffused. At this time, because the diffusion speeds of boron and arsenic into the substrate 1 are different, layers of different depths are formed on thermal diffusion treatment. Since boron has a higher diffusion speed than arsenic, it forms a deeper P type well layer.

Description

Detailed Description of the Invention [Technical Field] The present invention relates to a complementary insulating cathedral effect semiconductor device (Co
mplementaly MISIC, hereinafter,
Regarding the manufacturing method of CM
The present invention relates to latch-up countermeasure technology for O8IC.

[Background technology]

In 0M6S technology C, in order to prevent latch-up caused by the semiconductor substrate constituting the semiconductor substrate and the well layer of opposite conductivity type formed in the semiconductor substrate, a technology for forming the well layer as a highly doped impurity layer is used. For example, I BDM
, 82. Technical Digest No. 447
It is entrusted to the page.

This technology aims to reduce the resistance of the well layer by forming a low impurity concentration only on the surface of the substrate where the source/drain layer in well 1 exists, and increasing the impurity concentration in the well layer other than the surface. (A well layer with such a structure is hereinafter referred to as a "well layer with an inverse concentration distribution.")
).

If the resistance of the well layer is reduced, the substrate, well layer, and
The current flowing through the parasitic bipolar transistor created by the source/drain layer is reduced, reducing current breakdown due to latch-up. Furthermore, by lowering the concentration near the source/drain layer, the junction capacitance between the source/drain layer and the substrate can be reduced.

The method for manufacturing CMI SIC having such a structure is to first form a highly doped well layer of conductivity type opposite to that of the substrate, and then to reduce the concentration of the substrate surface of the well layer to a low concentration. In this method, impurities of the opposite conductivity type are introduced using a field insulating film or the like as a mask, and are thermally diffused.

However, in the method for manufacturing a CM6SIC having the above structure, the well layer is formed only on the surface of the substrate at a low concentration, and then impurities are introduced into regions other than the well layer formation region to prevent the short channel effect. However, the entire process for forming the device (IC) has the disadvantage of being extremely complicated.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a method for easily manufacturing a well layer having a reverse gradient concentration distribution to prevent latch-up.

The above and other objects and novel features of the present invention will become apparent from the description herein and the accompanying drawings.

[Summary of the invention]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a thin oxide film is formed on an N-conductivity type silicon substrate, N-type impurities are introduced into the entire surface of the silicon substrate through the thin oxide film, and P-type impurities are selectively introduced into this region into the silicon substrate. Introduce. P introduced later
Through this process of simultaneously thermally diffusing type impurities and N-type impurities into the substrate, a P-type low-concentration impurity layer is formed near the surface of the P-type impurity introduced region, and a P-type high-concentration impurity layer is formed in the deep part. Ru. In other words, a well layer having a concentration distribution with an opposite gradient is formed.

At the same time, in the N-type/recon substrate other than the P-type well layer, an N-type high concentration impurity layer can be formed using arsenic in the vicinity of the surface where the source/drain layer is present.

〔Example〕

FIG. 1 is a cross-sectional view of a CMISIC having an insulated gate field effect transistor (hereinafter referred to as MISFET) Qt formed by the manufacturing method of the present invention;
FIG. 2 is a plan view of the CMISIC having the cross-sectional view shown in FIG. 1 along line AA'.

In FIG. 1 and FIG. 2, P-channel type MI
SFETQ+ and N-channel type MISFFJTQ2 exist via a field insulating film 5 made of silicon oxide (Sin). 3 and 4 are MI 5FETs
Qt, Q2 are present in the active region 4 through a gate 8 extending across the plane of FIG. In the active region 3, N
A type source/drain layer 7 is present. An input signal enters the gate 8 made of polycrystalline silicon, and an output signal passes through the source/drain N6, 7 and is sent to the wiring 13.
is output to. Wires 14 and 15 are aluminum wires for supplying power supply voltage, and are in ohmic contact with the active region 4.3.

The characteristics of the device (IC) formed by the manufacturing method of the present invention are that a high concentration P conductivity type layer 2 and a low concentration P conductivity type N3 exist in the P conductivity type well layer; At the same time as layer 3 is formed, an N conductivity type layer having a higher concentration than the N conductivity type semiconductor substrate is formed in the P channel type MISFETQ+. As mentioned above, by forming the highly-concentrated P conductivity type well layer 2, the well layer becomes low in resistance.
Latch amplifier can be prevented. Also, low concentration of P
The presence of the conductive well layer 3 makes it possible to reduce the parasitic capacitance between the source and the substrate. Furthermore, the presence of the N conductivity type impurity layer 4 formed at the same time can suppress the short channel effect of the P channel type MISFETQ+. A high concentration P conductivity type well layer 2, a low concentration P4 conductivity type well layer 3, and a high concentration N conductivity type well layer 2,
The method for forming the type impurity N4 will become clear later.

The structure of the CMISFET shown in FIGS. 1 and 2 will be explained in more detail as follows. 1 is an N conductive type semiconductor substrate, in which the P+ type source/drain layer 6. P-type TwelfWI2,3. N+
A type source/drain layer 7 is present. Lanochiup, which is a problem in the present invention, is a P-type source/drain layer 6. N
Mold substrate 1. A bipolar transistor parasitically formed from a P-type well layer and an N-type substrate1. P-type Twel #2.
It arises from a bipolar transistor formed parasitically from the N1 type source drain N7.

A field insulating film 5 made of silicon oxide for isolating the individual MISFETs is present on the substrate, and a gate electrode 8 made of polycrystalline silicon is present in the active region. A gate insulating film 9 made of silicon oxide is present between the gate 8 and the substrate 1, and a silicon oxide film 11 is formed around the gate 8 in order to prevent electric field concentration. A first passivation film 12 made of phosphosilicate glass is formed to protect the source/drain layer or gate formed in the active region. In addition, aluminum wiring 1 contributing to the input and output
3 to 15 are formed on the first passivation film. Furthermore, a final page transport film 16 made of phosphosilicate glass is formed to protect the entire structure.

The method for manufacturing a CMISIC according to the present invention will be described below with reference to FIGS.
This will be explained using FIG.

First, an N-type single crystal silicon substrate l having a (100) crystal plane is prepared. The N-type silicon substrate 1 is thermally oxidized to form a thin silicon oxide film 21 as shown in FIG. An N-type impurity, for example, arsenic, is introduced into the silicon substrate through the silicon oxide film 21. In this case, the silicon oxide film 21 serves to protect the silicon substrate. The arsenic introduced into the substrate is concentrated on the surface of the substrate as shown in FIG. 322. In order to form the P-type well layer, areas other than the area where the P-type well layer is to be formed are selectively covered with a photoresist film, and using this as a mask, the P-type well layer 3 is coated with a photoresist film.
A P-type impurity, for example, boron, is introduced through the silicon oxide film 21.

This state is shown in FIG.

In the region where the P-type well layer is formed, P-type impurities,
For example, a layer 24 of boron and a layer 22 of N-type impurity, for example arsenic, coexist.

Next, the photoresist film 23 is removed, and the introduced P-type impurities, such as boron, and N-type impurities, arsenic, are thermally diffused. At this time, since the diffusion rates of boron and arsenic into the substrate 1 are different, when thermal diffusion treatment is performed, layers with different depths are formed as shown in FIG. 5. Compared to arsenic, boron is
Since the diffusion rate is fast, a deep P-type well layer 2 is formed.

Since arsenic has a slower diffusion rate than boron, it spreads over a shallower region than boron, and in the N-type silicon substrate, the N-type impurity w has a higher impurity concentration than the silicon substrate 1.
Form I4. This N-type impurity layer 4 suppresses the short channel effect of the P-channel MISFET. Further, in the P-type well layer, arsenic mixes with boron to form a region 3 in the P-type well layer that has a lower P-type trench electric property than the P-type well region 2. N
Since the channel type MISFgT is formed within this P-type well layer 3, the parasitic capacitance between the source and the P-type well layer 3 can be made small, and high speed operation can be achieved. In addition, the P-type well layer 2 formed at a high concentration has a P-type well/i
It serves to lower the resistance of 12, and can prevent latte-up in CMISIC. In the present invention,
N-type impurity layer 4. pH Liugol/j'J2. The formation of the P-type well layer 3 is much easier than the previous formation method described in the Background Art section, and has many advantages.

Hereinafter, a well-known manufacturing method will be used to form an element (IC) on the substrate. In order to form a field insulating film without cutting, a thin silicon oxide film (not shown) is formed on the entire surface of the silicon substrate, and then a silicon nitride film is deposited on top of it by, for example, a vapor phase chemical reaction method (hereinafter referred to as CVD method). A membrane (not shown) is selectively formed. By thermally oxidizing the silicon substrate surface using this silicon nitride film (not shown) as a mask, a thick field insulating film 5 made of silicon oxide is formed.
This is an insulating film for insulating the FET. Furthermore, the thin silicon oxide film (not shown) and silicon nitride film (not shown) formed on the silicon substrate for forming the field insulating film 5 are removed, and a thin gate insulating film 9 made of silicon oxide is formed as shown in FIG. Form as shown.

When forming this thin gate insulating film 9, in order to obtain cleanliness, the silicon substrate is once thermally oxidized to remove the thin oxide film formed on the surface, and then the gate insulating film 9 is formed.

Next, this gate insulating film 9 and field insulating film 5
A polycrystalline silicon film for forming a gate is formed on the entire surface using, for example, a CVD method.

Furthermore, in order to obtain conductivity of the polycrystalline silicon film, impurities such as phosphorus (pi?) are added to the polycrystalline silicon layer.
Introduced by ion implantation method. Furthermore, in order to remove the polycrystalline silicon IJ layer in areas other than the area where the gate is to be formed, a photoresist film (not shown) is selectively formed, and using this photoresist film as a mask, the A crystalline silicon layer 8 is formed. Furthermore, in order to form source/drain layers, M I S F E is applied using the polycrystalline silicon layer 8 that forms the gate as a mask.
Impurities suitable for each are implanted into the T Q+ and Q2 regions. This is done in the following way.

First, let's take the example of silicon oxide (8) in a high temperature, low pressure atmosphere.
102) A film (not shown) is selectively formed in areas other than the P-type well layer, and using this as a mask, KN-type impurities in the P-type well skin, such as phosphorus, are implanted and thermally diffused.
Form an N-type source/drain hermitage. Furthermore, in contrast to this, a silicon oxide film is selectively formed on the P-type well layer,
Using this as a mask, a P-type impurity such as boron is implanted and thermally diffused to form the source/drain layer of the P-channel MISFETQ.
form 6. After this treatment, a thin silicon oxide film 8 is formed on the surface of the polycrystalline silicon layer 8 in order to clean the device surface and prevent electric field concentration at the edge of the gate. A structure formed in this manner is shown in FIG.

After forming the device as described above, a first passivation film, a desired pattern of aluminum wiring, and a final passivation film are formed by a well-known method.

That is, a first passivation film 12 having contact holes 17 to 20 is formed by disposing a phosphosilicate glass film over the entire surface by, for example, the CVD method. As shown in FIGS. 8 and 2, aluminum wirings 14 to 15 for input/output signals, power supply voltage, etc. are formed. Finally, as shown in FIG. 1, a final passivation film is formed into a shape 5y using, for example, phosphosilicate glass.

〔effect〕

By implanting arsenic (As) and boron (B) into the silicon substrate almost simultaneously, a P-type well structure for improving the Lanthia knob breakdown voltage can be easily formed, and a high concentration can be used to suppress the short channel effect of P-channel MISFETs. It is possible to form an N-type impurity 1 near the P-type source/drain. Therefore, compared to the conventional manufacturing method of a P-type well structure for improving latch-up breakdown voltage, a large number of steps can be reduced.

Although the invention made by the present inventor has been specifically explained based on Examples above, the present invention is not limited to the above Examples, and it should be noted that various changes can be made without departing from the gist of the invention. Not even. For example, even if the arsenic introduced into the substrate is antimony, the effects of the present invention will not be impaired. Further, the first passivation film may be formed of silicon oxide, and the PJ4 MIC7 insulating film may also be formed of silicon oxide or the like.

[Brief explanation of drawings]

Figure 1 shows mutually complementary MISFETQ+. A cross-sectional view of the CMISIC with Q2, FIG.
CMIS with cross-sectional view 1 shown in the figure along line AA'
The plan view of the IC and FIGS. 3 to 8 are cross-sectional views taken along line AA' in FIG. 2, showing the manufacturing process of the CMI SIC according to the present invention. DESCRIPTION OF SYMBOLS 1...N-conductivity type silicon semiconductor substrate, 2...P-conductivity type well layer, 3...P-conductivity type well layer introduced according to the present invention, 4...N4 introduced according to the present invention Tortoise-shaped diffusion region, 5... Field insulating film made of oxidized silicon, 6... P+ type drain layer, 7... N
+ type drain 1.8...Gate electrode made of polycrystalline silicon, 9...Gate insulating film made of silicon oxide, 10...Silicon oxide film, 11...Silicon oxide that protects the gate electrode Film, 12... First passivation film made of phosphosilicate glass, 13-1
5... Aluminum wiring, 16... Final passivation film made of phosphosilicate glass, 17-
20... Contact hole, 21... Silicon oxide film, 22... Arsenic doped region, 23... Photoresist film, 24... Boron doped region. Agent Patent Attorney Akio Takahashi

Claims (1)

[Claims] 1. A step of forming a thin oxide film on an N-conductivity type silicon substrate and introducing arsenic into the substrate through the thin oxide film;
A method for manufacturing a semiconductor device, which includes a step of selectively introducing boron into a region where a P-conductivity type well layer is to be formed, and a step of thermally dissipating the introduced arsenic and boron into a substrate. 2. The method for manufacturing a semiconductor device according to claim 1, wherein the arsenic is antimony (r-).