JP2508218B2 - Complementary MIS integrated circuit - Google Patents

Description

The present invention relates to complementary MIS integrated circuits, and more particularly to CMOS integrated circuits.

[Conventional technology]

Fourth conventional example in which N well is formed in P type semiconductor
Shown in the figure. In the figure, 4 is a P ⁻ type semiconductor substrate, 5 is an N well provided in the substrate, P ⁺ diffusion layers 1-1 and 1-2 in this region and a gate electrode 3 made of polysilicon provided above
A pMOS transistor is provided at -2. Reference numeral 2-3 is an N ⁺ diffusion layer for applying a well potential to the N well 5. 2-
1, 2-2 are N ⁺ diffusion layers directly provided on the semiconductor substrate 5 and nMO
These are the source / drain regions of the S transistor. 1-3
Is a P ⁺ diffusion layer for applying a substrate potential to the P ⁻ type semiconductor substrate 4.

[Problems to be solved by the invention]

In the conventional CMOS integrated circuit shown in FIG. 4, the P ⁺ diffusion layers 1-1 and 1-2, the parasitic vertical transistor Q2 formed by the N well 5, and the P ⁻ type semiconductor substrate 4 and the N ⁺ diffusion layer are formed. Two
-2, P ^- type semiconductor substrate 4, and N well 5 form a parasitic lateral transistor Q1. When a certain amount of trigger current flows into the above-mentioned parasitic bipolar transistor, positive feedback occurs between Q2 and Q1, and the N ⁺ diffusion layer 2-3 and the P ⁺ diffusion layer 1 pass through the side surface or the bottom surface of the N well 5. Current flows between -3 and causes latch-up.

As one of the causes of latch-up, if there is a parasitic resistance R between the P ⁺ diffusion layer 1-3 that gives a substrate potential and the P ⁻ type semiconductor substrate 4, the substrate potential cannot be suppressed sufficiently and the N ⁺ diffusion layer is not suppressed. Electrons can easily flow into the P ⁻ type semiconductor substrate from 2-2 by the trigger, and the lateral transistor Q1 can be operated. Then, due to the operation of Q1, electrons are injected into the N well and the well potential is lowered, thereby operating the vertical transistor Q2 and causing positive feedback between Q1 and Q2.

As described above, the conventional CMOS integrated circuit has a drawback of low latch-up resistance.

[Means for solving problems]

A complementary MIS integrated circuit according to the present invention is a complementary MI that comprises a second conductivity type well provided in a first conductivity type semiconductor substrate.
In the S integrated circuit, the side surface and the bottom surface of the second conductivity type well are insulated by an insulating layer and a high-concentration first conductivity type semiconductor layer, respectively.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip showing a main part of a first embodiment of the present invention.

In this embodiment, in a CMOS integrated circuit including an N well 5 provided on a P ⁻ type semiconductor substrate 4, a separation groove 6 (insulating layer) in which the side surface and the bottom surface of the N well 5 are filled with silicon oxide, respectively. And is insulated by the P ⁺ type semiconductor layer 7.

 Next, the manufacturing method of this embodiment will be described.

2A to 2C are cross-sectional views of semiconductor chips arranged in the order of steps for explaining the manufacturing method of the first embodiment.

First, as shown in FIG. 2 (a), it is made of silicon.
The P ⁻ type semiconductor substrate 4 is selectively etched to a depth of about 5 μm from the surface to form a well region. Then, P-type ions such as boron are implanted in this region to form an ion implantation layer 7 °. The injection volume is about 10 ¹³ cm ^-2 . Next, as shown in FIG. 2B, an N ⁻ type semiconductor layer is selectively epitaxially grown on the above-mentioned etched portion to form an N well 5, and a field insulating layer 8 for element isolation is formed. Then, a groove is formed at the boundary between the N well 5 and the P ⁻ type semiconductor substrate 4, and the surface of the substrate is thermally oxidized to form the gate oxide film 9. At this time, the side surface of the groove is also covered with the thermal oxide film, but if the groove cannot be completely filled with the thermal oxide film, the silicon oxide film is selectively grown by the CVD method to form the separation groove 6
To form. Next, as shown in FIG. 1, a polycrystalline silicon film is formed on the entire surface and then patterned to form a gate electrode 3
-1,3-2 is formed. Further, the gate oxide film immediately below the gate oxide film is also etched to expose the substrate surface, and As ions and boron ions are selectively implanted using the field insulating film 8 and the gate electrodes 3-1 and 3-2 as masks. As a result, the N ⁺ diffusion layers 2-1 to 2-3 and the P ⁺ diffusion layers 1-1 to
Form 1-3.

The side surface of the N well 5 is sufficiently insulated by the isolation trench 6 filled with silicon oxide, and the P ⁺ type semiconductor layer 7 is present at the bottom, so that the amplification factor α of the parasitic NPN transistor (Q1) becomes small, so that latch up The tolerance is improved.

FIG. 3 is a cross-sectional view of a semiconductor chip mainly including a main part of the second embodiment of the present invention.

An N well 5 and a P-type semiconductor layer are formed on the P ⁺ -type semiconductor layer 7.
10 are formed, and a pMOS transistor is formed in the N well 5 and an nMOS transistor is formed in the P type semiconductor layer 10. In this embodiment, not only the N well 5 but also the P type semiconductor layer 10 is formed on the P ⁻ type semiconductor substrate 4 by epitaxial growth after forming the P ⁺ type semiconductor layer 7. In this embodiment, since the P ⁺ type semiconductor layer is formed on the entire surface of the substrate, there is an advantage that the resistance of the substrate is further lowered and the resistance is increased by the latch-up.

In the above description, the same holds true even if the conductivity type is reversed. Needless to say, the MIS transistor such as MNOS may be used instead of the MOS transistor.

〔The invention's effect〕

As described above, according to the present invention, since the insulating layer is provided on the side surface of the well and the high-concentration low-resistance layer of the same electric type as the substrate is provided on the bottom surface of the well, positive feedback occurs in the parasitic thyristor circuit. This has the effect of improving the latch-up resistance of the complementary MIS integrated circuit.

[Brief description of drawings]

FIG. 1 is a sectional view of a semiconductor chip showing a main part of a first embodiment of the present invention, and FIGS. 2A to 2C are arranged in the order of steps for explaining a manufacturing method of the first embodiment. FIGS. 3 and 4 are sectional views of the semiconductor chip showing the main parts of the second embodiment and the conventional example, respectively. 1-1 to 1-3 ... P ⁺ diffusion layer, 2-1 to 2-3 ... N ⁺ diffusion layer, 3-1, 3-2 ... Gate electrode, 4 ... P ⁻ type semiconductor substrate,
5 ... N well, 6 ... Isolation trench, 7 ... P ⁺ type semiconductor layer, 8 ... Field insulating film, 9 ... Gate oxide film, 10 ... P type semiconductor layer.

Claims (1)

(57) [Claims] 1. A complementary type comprising a second conductivity type well provided in a first conductivity type semiconductor substrate and a field insulating film having a predetermined thickness selectively provided on a surface portion of the semiconductor substrate.
In the MIS integrated circuit, the second-conductivity-type well is insulated by a high-concentration first-conductivity-type semiconductor layer and an insulating isolation groove that is in contact with the entire side surface and bottom surface of the well and extends deeper than the bottom surface of the field insulating film. , A high-concentration second-conductivity-type diffusion layer for supplying a well potential, which is provided in a region defined by the field insulating film on the surface of the second-conductivity-type well, The complementary MIS, which is a second-conductivity-type epitaxial layer in contact with the first-concentration-concentration semiconductor layer and in which the isolation trench is filled only with a silicon oxide film in contact with the side and bottom surfaces thereof.
Integrated circuit.