JPS6388856A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the saturating resistance of a bipolar transistor due to the defect of a buried diffused layer thereby to suppress the deterioration of its characteristics and to simplify the number of steps of manufacturing a semiconductor device by providing a low resistance layer at the center of a base and forming a structure that the opposing length of an emitter and a collector is increased while the resistance component is being reduced. CONSTITUTION:An NPN transistor Q1 has a structure formed of a collector region 2 made of an N-type diffused layer formed on a p<-> type substrate 1, high concentration p<+> type regions 51 contained in the region 2 and formed at relative position, a base 12 interposed between the two regions 51, a p<+> type layer 8 formed substantially at the center of the region 12 and of deeper diffused length than the base 12, and an emitter 17 contained in the region 12 and formed in a self-aligned manner with the base, thereby providing a transistor structure equivalent to the double emitters and double collectors to prevent the saturating resistance of the transistor Q1 from increasing due to the defect of the n<+> type buried diffused layer and to also produce a large output current.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to semiconductor devices, particularly bipolar transistors and CM
So-called Bi-CMO that incorporates an OS transistor
The present invention relates to a method for manufacturing an SIC.

[Conventional technology]

In recent years, various Bi-CMOS ICs have been proposed in which bipolar transistors and CMOS transistors are formed on the same substrate and take advantage of the features of each device. An example of the element structure of the Bi-CMOSIC is shown in FIG. 2 and will be explained. In FIG. 2, 21 is a p-type substrate;
2 is an n-type buried layer, 23 is an n-epitaxial layer (hereinafter referred to as
24 is a p+ isolation layer, 25 is an n+ collector extraction layer, 26 is a field oxide film, 27 Fip-
It is a type island. Also, 28.29 are each NP
N base and emitter of transistor Q1, 30 are p(
Channel) Polysilicon as the gate of MOS transistor Q2, 301 is the same <, (channel) Polysilicon of MOS transistor Q3, 31 is the source and drain of 9MO8 transistor Q2, 32 is the source and drain of nMOS transistor Q3, 33 is At (aluminum) wiring, 34 is a p+ channel cut layer, 35 is a gate oxide film, and 36 is a PSG film as an insulating protection layer.

Next, a method for manufacturing the above B i -0MO3 structure will be outlined with reference to FIG. First, Figure 3 (&)
In this step, an n-type buried layer 22 is formed on a p-type substrate 21 by high-concentration buried diffusion, and an n-type layer 23 is formed by epitaxial growth.

Next, after oxidizing this surface, B+ (boron) is ion-implanted to form a p- island 27 (FIG. 2(b)).
reference). Next, as shown in FIG. 3(b), after forming a p-sufficient separation layer 24 and further forming an n+ collector extraction layer 25, a field oxide film 26 is formed by selective oxidation, and at the same time, a p+ channel is cut. Form layer 34.

Next, as shown in FIG. 3(C), after peeling off the oxide film on the surface of the n-type layer 23, a gate oxide film 36 is formed, and B+ ions are implanted into the gate part of the nMOS transistor Q3 to form a channel. Do dope. Thereafter, polysilicon is deposited by CVD and patterned to form polysilicon gates 30, 3 (h) of 9MO8 and nMO8 transistors Q2 and Q3.
By implanting + ions, the base 28 of the NPN transistor Q1 and the source and drain 31 of the PMOS transistor Q2 are simultaneously formed.

Next, as shown in FIG. 3(d), the emitter part of the NPN transistor Q1 and the nMO8 transistor Q3
Openings are provided on the source and drain regions of A++”
(Arsenic) is ion-implanted to form the emitter 29 of the NPN transistor Q1 and the source and drain 32 of the nMO8 transistor Q3. Thereafter, a PSG film 36 is deposited, contact holes are formed at predetermined locations, and At wiring 33 is provided, thereby completing the old CMOSIC having the structure shown in FIG.

[Problem that the invention seeks to solve]

However, the conventional Bi-CMO produced in this way
Since SIC simply combines a bipolar device structure and a CMOS device structure, desired transistor characteristics can be obtained for each transistor, but the number of steps is large,
There was a problem that it was too redundant and productivity was low.

The present invention was made in order to solve the above problems, and provides a Bi-CMO that can simplify the number of steps and can be manufactured without deteriorating the characteristics of each transistor.
The purpose of the present invention is to provide a method for manufacturing an SIC.

[Failure to solve the problem]

That is, the present invention provides a bipolar transistor and a first transistor having a different conductivity type on a substrate of one conductivity type. Bi- which incorporates CMOS transistor consisting of second MOS transistor
A method for manufacturing a semiconductor device having a CMOS structure, which includes the steps of: performing diffusion of another conductivity type on the substrate of one conductivity type to form a collector layer of a bipolar transistor and an island region of a first MOS transistor; and selective oxidation of the substrate. After that, a step of selectively forming a diffusion layer of one conductivity type at a predetermined location below the layer, and a step of performing diffusion of another conductivity type in a part of the collector layer to form a high concentration collector region. , forming a diffusion region with a high concentration of one conductivity type and a diffusion depth deeper than the base near the center where the base is to be formed in the collector layer; 1st each.
forming a gate of a second MOS transistor;
forming a base of a bipolar transistor in the diffusion region of one conductivity type formed near the center of the island region, and simultaneously forming a source and a drain using the gate of the first MOS transistor as a mask;
The method is characterized by comprising the step of forming an emitter in the base region and simultaneously forming a source and a drain using the gate of the second MOS transistor as a mask.

[Effect]

Therefore, in the present invention, the shrimp layer and the buried diffusion layer can be omitted, and a low resistance layer is provided in the center of the base constituting the bipolar transistor in the Bi-CMOS structure to reduce the base resistance component. However, by creating a structure with a long emitter-collector facing length, it is possible to prevent the saturation resistance of the bipolar transistor from increasing due to missing buried diffusion layers, increase the output current, and suppress the deterioration of the characteristics of the bipolar transistor. .

〔Example〕

Hereinafter, the present invention will be described in detail based on embodiments shown in the drawings.

FIG. 1(a) or 1) shows the 81-CMO according to the present invention.
FIG. 8 is a process cross-sectional view showing an example of a method for manufacturing 8IC.

First, in FIG. 1(,), a p-type substrate 1 is oxidized, and phosphorus (phosphorus) is implanted onto the substrate 1 to form an n-type transistor at the same time as the collector region 2 of the NPN transistor Q1. An island 21 is formed. Next, as shown in FIG. 1(b), a field oxide film 4 is formed on this substrate 1, a nitride film 3 is deposited and patterned, and boron (B+) is ion-implanted to form a p+ isotope. Create ration area 5. Then, at the same time, phosphorus (P+) is implanted using the lurgist as a mask to form the n+ isolation region 6. At this time, NP
N) At the same time, a p10 region 51 is formed around the base of the rungis 291 portion. Note that the n+ isolation region 6 does not need to be formed. In that case, the p+ isolation/region 5 is not formed in the n+ isolation region 6 portion. Then, selective oxidation is performed simultaneously with isolation annealing.

Next, as shown in FIG. 1(c), the nitride film 3 on the collector portion of the NPN transistor Q1 is removed, and a heavily doped n0 region T is formed by implantation or diffusion.

Next, as shown in FIG. 1(d), the nitride film 3 is completely removed and a p-type layer 8 is formed as a low resistance base layer at the center of the base of the NPN transistor Q1 by ion implantation. At this time, although the order may be reversed, only the thin oxide film on the substrate 1 is removed and oxidized again to form the gate oxide film 10, and then channel doping is performed by implanting boron ions. Region 9 is formed.

Next, as shown in Figure 1(,), polysilicon is
After depositing using the D method and diffusing phosphorus to lower the resistance, patterning is performed to form 2MO8 and n
MO8 transistors Q2 and gates 11 of A3 are formed. Next, as shown in FIG. 1(f), boron ions are implanted and annealed to form the base 12 of the NPN transistor Q1 and the p+ source and drain 13 of the pMOS transistor Q2. At this time,
The base 12 and the p+ layer 1 are in contact or N
PN transistor Q.

In order to improve the withstand voltage of the NPN transistor Q1, it is desirable that the distance be smaller than the depletion layer extending toward the collector side due to the operating voltage.

Next, as shown in FIG. 10), an NPN transistor Q
After opening holes in the oxide film 4 on the emitter and collector parts of 1 and the source and drain of the nMO8 transistor Q3,
Ions are implanted in As and annealed to form the emitter 17. of the NPN transistor Q1. At the same time as the collector section 18, n
The n+ source and drain 16 of the MO8 transistor Q3 are formed. At this time, it is desirable that the size of the opening 14 of the emitter is determined by the field oxidation M4.

At that time, the relationship between the base 12 and the p-physiology 51 is essential as described above. The part where the field oxide film 4 and the base 12 are in contact is the weakest in terms of withstand voltage, and it is
This is because it is necessary to reinforce it with I.

After that, as shown in Fig. 1 (color), a PSG film 9 is deposited, contact holes are made in each predetermined part, and A4 wiring 20 is applied, as shown in Fig. 1 (i).
As shown in the figure, a B-type transistor with CMO8 transistors consisting of an NPN transistor Q1, a 9MO8 transistor Q2, and an nMO8 transistor Q3 is assembled on the same substrate.
i-CMOSIC can be produced.

Bi-CMOSI of the present invention manufactured in this way
According to C, since the shrimp layer and the buried diffusion layer can be omitted, the process can be simplified.

In addition, the structure of the bipolar transistor in the conventional Bi-CMOS structure has been changed, and a low resistance layer made of a highly doped diffusion layer is provided in the center of the base to lower the base resistance component and increase the emitter-collector facing length. By doing so, it is possible to eliminate the characteristic deterioration of the bipolar transistor that often occurs due to the omission of the shrimp layer and the buried diffusion layer. That is, the NPN transistor Q1 has a collector region 2 made of an n-type diffusion layer formed on a p-type substrate 1.
A high-concentration P10 region 51 included in this collector region 2 and formed at an opposing position, and a base 12 formed at a position sandwiched between the two P10 regions 51.
A p layer 8 having a high concentration and having a deeper diffusion depth than the base 12 is formed substantially in the center of the base region 12, and an emitter 1T included in the base region 12 and formed in self-alignment with the base. By creating a structure consisting of
This has the advantage of preventing an increase in the saturation resistance of the transistor Q1 and allowing a large output current to be extracted.

In the above embodiment, in the step of FIG. 1(f), N
Although annealing was performed after implanting boron to form the base of the PN transistor Q1 and the source and drain of the 9MO8 transistor Q2, the annealing after implanting boron may be omitted. In this case, there is an advantage of shortening the channel length of the PMOS transistor Q2, but the xj of the base 12 of the NPN transistor Q must be shallow, the field oxide film thickness, the boron dose amount of the 24th layer 51, and the xB base 12 ( It is necessary to take into consideration parameters such as the boron dose amount of the source and drain of the 9MO8 transistor Q2, and the annealing conditions after AlI implantation.

〔Effect of the invention〕

As described above, according to the present invention, by omitting embedded diffusion and shrimp growth, the l-CM can be produced at low cost with high productivity.
By incorporating bipolar transistors that can be manufactured into OSICs and have a high output current, an i-CMOSIC with good characteristics can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a process sectional view showing an example of the Bi-CMOSIC manufacturing method according to the present invention, and FIGS. 2 and 3 are a sectional view showing a conventional Bi-CMO8 structure and a schematic process sectional view thereof, respectively. . 1...p-type substrate, 2...collector region, 21
・Fist φ・n-type island, 4...field oxide film, 5...p+ isolation region, 51 a
Fist/fist p ten region, 6... n+ isolation region, T... n ten region, 8... p soil layer (low resistance base layer), 10... gate oxide film, 11...gate, 12...base, 13...-p+ffi source, drain, 16...men+ type source, drain, 17...emitter, 1B...collector section,
19...PSG film, 20...At wiring, Ql...
...NPN transistor, Q2 ...9MO
s transistor, Q3...nMO8 transistor.

Claims (1)

[Claims] A CMO consisting of a bipolar transistor and first and second MOS transistors of different conductivity types on a substrate of one conductivity type.
In the method of manufacturing a semiconductor device having a Bi-CMOS structure incorporating an S transistor, the step of performing diffusion of another conductivity type on the substrate of one conductivity type to form a collector layer of a bipolar transistor and an island region of the first MOS transistor; , after performing selective oxidation of the substrate, selectively forming a diffusion layer of one conductivity type at a predetermined location under the substrate; and diffusing another conductivity type into a part of the collector layer to form a highly concentrated collector layer. a step of forming a diffusion region of one conductivity type at a high concentration near the center where a base is to be formed in the collector layer and having a diffusion depth deeper than the base; and an island region on the substrate. and forming gates of first and second MOS transistors on the surface of the region adjacent thereto, respectively, and forming a base of a bipolar transistor in the diffusion region of one conductivity type formed near the center of the island region. At the same time, forming a source and a drain using the gate of the first MOS transistor as a mask, forming an emitter in the base region, and simultaneously forming a source and a drain using the gate of the second MOS transistor as a mask. A method for manufacturing a semiconductor device, comprising the steps of: