JPS62219554A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the area of an isolation region and to contrive to enhance the integration of the titled device by providing processes for forming respectively a buried semiconductor region and a semiconductor region for isolation; which have the same conductivity type as those of the respective substrates between semiconductor element forming regions or the other conductivity type and also, have an impurity concentration higher than those of the substrates; on the major surface parts of the substrates. CONSTITUTION:The bottom part of the n-type well region of a p-channel MISFET Qp is constituted of a high-concentration buried semiconductor region 3B, the bottom part of the n-type well region of an n-channel MISFET Qn is constituted of a high-concentration buried semiconductor region 5A like the p-type well region and an isolation region is provided between the regions in which are formed the MISFET Qp and the MISFET Qn respectively that prevent latch-up respectively. Following the process for forming this insulating film 4 for interelement isolation, a p-type impurity is introduced in the major surface parts of the respective epitaxial layers 2 of the MISFET Qn forming region and the isolation region forming region and the buried semiconductor region 5A and a semiconductor region 5B for isolation are each formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to a complementary M circuit device.
Semiconductor integrated circuit device (hereinafter referred to as
6MO8).

[Conventional technology]

CMO3, which aims to achieve high integration and low power consumption, is required to have high operating speed and large drive capacity. As a technology for realizing this requirement, there is a so-called mixed type semiconductor integrated circuit device (hereinafter referred to as B1-CMOS) in which a bipolar transistor is mounted on a 6MO8.

Japanese Patent Application No. Sho 58-143859, previously filed by the applicant of the present application, describes a technique for preventing latch-up in Bi-CMOS. This technology creates a highly doped p-type buried semiconductor region between the lightly doped p-type semiconductor substrate and the P-type well region (n-type epitaxial layer) in the CMOS formation region. It was formed. This P
The +-type buried semiconductor region is configured to form a p-type well region having a higher impurity concentration at the bottom than at the surface. In other words, the P+ type buried semiconductor region is p
Parasitic bipolar 1~ that makes the well region of the mold the base region
The current amplification factor of the transistor is reduced to prevent its operation from occurring.

The P-type buried semiconductor region is formed in an intervening portion between a p-type semiconductor substrate and an n-type epitaxial layer so as to surround the n4-type buried collector region of the bipolar transistor. In other words, between the P+ type buried semiconductor region and the n''' type buried collector region or between the buried collector regions, there is a high concentration p type isolation layer between the P+ type buried semiconductor region and the buried collector region to electrically isolate the semiconductor elements. This P-type isolation semiconductor region forms an isolation region together with a field insulating film formed on the surface of the epitaxial layer.

This type of Bi-CMOS can be formed by performing the following manufacturing process. First, an n-type impurity for forming a buried collector region and a p-type impurity for forming a buried semiconductor region and an isolation semiconductor region are sequentially introduced into different main surface portions of a p-type semiconductor substrate.

Thereafter, an n-type epitaxial layer is laminated on the main surface of the semiconductor substrate, and n-type and p-type well regions constituting the CMOS are formed in this epitaxial layer. and,
A field insulating film (device isolation insulating film) is formed on the main surface of the epitaxial layer between the semiconductor element forming regions.

Thereafter, a collector region, a base region, and an emitter region are sequentially formed on the main surface of the epitaxial layer to form a bipolar transistor. Along with the formation of this bipolar transistor, p-channel and n-channel MISFETs are formed on the main surfaces of the π-type and p''-type well regions, respectively.By performing these series of manufacturing steps, Bi-CMOS
is completed.

[Problem that the invention seeks to solve]

As a result of studying the above-mentioned Bi-CMOS, the inventor found that the following problems occur.

The epitaxial layer cannot be made thin.

That is, this is because the emitter-collector junction breakdown voltage of the bipolar transistor is reduced.

Moreover, the source region and drain region of MISFET,
The purpose of the n-type buried semiconductor region (or buried collector region) is to prevent the pn junction capacitance with the P-type buried semiconductor region from increasing.

Therefore, a low concentration p-type isolation semiconductor region is formed between the P4-type isolation semiconductor region and the element isolation insulating film in accordance with the thickness of the epitaxial layer. This p-type isolation semiconductor region is formed by introducing an impurity (boron) into the P-wall region, which is formed in the same manufacturing process as the p-type well region, to further increase the concentration.

However, when forming an isolation insulating film on the surface of a p-type semiconductor region for isolation between elements (oxidation process), impurities are significantly eaten away, making control of the impurity concentration unstable and concentration becomes lower. For this reason, the withstand voltage due to punch-through between semiconductor elements decreases.
The area of the isolation region increases, and the degree of integration of Bi-CMOS decreases.

An object of the present invention is to provide a technique that can reduce the area of one isolation region and increase the degree of integration of a semiconductor integrated circuit device.

Another object of the present invention is to provide a technique that can reduce the area of the isolation region and reduce the number of manufacturing steps required to form one isolation region.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

An overview of one typical invention disclosed in this application is as follows.

An insulating film for element isolation is formed on the main surface of the substrate between the semiconductor element formation regions, and impurities are introduced into the semiconductor element formation region and the main surface of the substrate between the semiconductor element formation regions through the element isolation insulating film. Then, a buried semiconductor region and an isolation semiconductor region having an impurity concentration of the same conductivity type or opposite conductivity type and higher impurity concentration than the base body are formed in the semiconductor element formation region and the main surface portion of the base body between the semiconductor element formation regions, respectively. do.

[For production]

According to the above-mentioned means, since the semiconductor region for isolation is formed through the insulating film for isolation after forming the insulating film for isolation, it is possible to form the isolation semiconductor region in contact with the insulating film for isolation at a high concentration. . Therefore, the area of the isolation region can be reduced and higher integration of the semiconductor integrated circuit device can be achieved.

Further, since the isolation semiconductor region can be formed in the same manufacturing process as the buried semiconductor region, the number of manufacturing steps for forming one isolation region can be reduced.

Hereinafter, regarding the structure of the present invention, the present invention will be described as Bi-CuO2
This will be explained along with an example in which the present invention is applied to.

In addition, in all the episodes, parts having the same functions are given the same reference numerals, and repeated explanations thereof will be omitted.

[Example I] This example
This is an example in which the present invention is applied to an ISFET formation region.

The schematic structure of B i-CuO2, which is Example I of the present invention, is shown in FIG. 1 (a sectional view of the main part).

In FIG. 1, 1 is a P-type semiconductor substrate made of single-crystal silicon, 2 is an n-type semiconductor substrate laminated on the main surface of the semiconductor substrate
- type epitaxial layer. The semiconductor substrate 1 and the epitaxial layer 2 constitute the base body referred to in Example I.

A heavily doped n'' type buried collector region 3A is provided in the bipolar transistor forming region between the semiconductor substrate 1 and the epitaxial layer 2.

A heavily doped t-type buried semiconductor region 3B is provided between the semiconductor substrate 1 and the epitaxial layer 2 in the p-channel MIS'FET formation region.

The Bi-CuO3 bipolar transistor Tr has a first
As shown on the left side of the figure, n+ type buried collector region 3A
, highly doped collector region 7° epitaxial layer 2
．． P-type base region 8, high concentration p-type emitter region 1
It consists of 1B.

The collector region of the bipolar transistor Tr is composed of a buried collector region 3A, a collector region 7, and an epitaxial layer 2. Collector region 7 includes interlayer insulating film 1
The collector region electrode 15 is connected to the collector region electrode 15 through a connection hole 14 provided at 3.

The base region 8 is electrically connected to the base region electrode 15 through the connection hole 14 . The emitter region IIB is a connection hole (not numbered) provided in the insulating film 9.
It is electrically connected to the emitter region electrode 10B through which the emitter region electrode 10B is passed.

The Bi-CuO2 p-channel MISFET QP is
As shown in the center of the figure, a high concentration buried semiconductor region 3B
an n-type well region consisting of a low concentration epitaxial layer 2, a gate insulating film 9, a gate electrode 10A, a high concentration p+
It consists of a source region and a drain region 12 of the type. The n-type well region is composed of a buried semiconductor region 3B with a high concentration at the bottom, and reduces the current amplification factor of the parasitic bipolar transistor whose base region is this n-type well region, thereby preventing its operation. (to prevent latch-up). The source region and drain region 12 are electrically connected to a source region electrode 15 or a drain region electrode 15 through a contact hole 14 .

Bi-CuO2 n-channel M I S F'ETQn
As shown on the right side of FIG. 1, a p-type well region consisting of a heavily doped p'' type buried semiconductor region 5A and a lightly doped p-type semiconductor region 6, a goo 1-insulating film 9. Gate electrode 1
0A, high concentration n+ type source and drain regions l
It is composed of IA. Similar to the p-type well region, the n-type well region has a bottom portion that is a highly doped buried semiconductor region 5A.
It is configured to prevent latch-up.

The source region and drain region 11A are electrically connected to the source region or train region electrode 15 through the connection hole 14.

The embedded semiconductor region I! ! 125A is constructed as shown with reference numeral 5A in FIG. 2 (the impurity concentration distribution diagram along the T-I line in FIG. 1). In other words, the buried semiconductor region 5A
is, the depth d+ from the surface of the epitaxial layer 2 is 1.2
−1.6 E p m ], lXl0”
The buried semiconductor region 5A is configured to have a peak value at an impurity concentration of about [a oms/cm'']. For example, boron is introduced by high-energy ion implantation of about 500 [K e V ]. It can be formed by

In FIG. 2, reference numeral 6 denotes a low concentration semiconductor region 6 in a p-type well region, which has a structure of I x 10" [atoms
It can be formed by introducing boron of about /cm21 by ion implantation with an energy of about 150 [KeV].

This semiconductor region 6 is formed so as to have a peak value of impurity concentration at a depth of about 0.4 [μm].

Reference numeral 11A indicates a source region or drain region 11A.

Bipolar 1, transistor], “r, MI 5FETQP, MI 5FETQn that constitutes this Bi-CuO2
A separation region is provided between each formation region.

This isolation region is in contact with the lower surface of the inter-element division insulating film (field insulation v) 4 provided on the main surface 2 of the epitaxial layer 2 and the isolation M film 4 for element amount m, and is in contact with the buried semiconductor region. It is composed of a highly doped p'' type isolation semiconductor region 5B provided on the main surface of the epitaxial layer 2 at a shallower position than 5A.

This isolation semiconductor region 5B is shown in FIG.
The impurity concentration distribution diagram on the line (2) is shown with reference numeral 5B attached thereto. Isolation l': The boron forming the conductor region 5B is formed into an insulating film for element isolation (for example, Si02 with a film thickness of 0.7 [μm]) in the same manufacturing process as the buried semiconductor region 5A. +) introduced through 4.

In other words, in the isolation semiconductor region 5B, the range of boron in the element isolation insulating film 4 is approximately 0.9 μm (500 μm).
KeV), so the depth d2 of the surface of the epitaxial layer 2 is 0.2 to 0.3 [μm].
The structure is such that the peak value of the impurity concentration is close to the lower surface of the insulating film 4 for isolation between elements. Boron forming the semiconductor region 6 is absorbed into the element isolation insulating film 4.

Next, the method for manufacturing Bi-CuO2 of this example will be briefly described using FIGS. 4 to 6 (cross-sectional views of main parts shown for each of the three manufacturing steps).

First, a P-type semiconductor substrate l is prepared. Then, bipolar transistor Tr formation region, p channel MISF
n on the main surface of each semiconductor substrate 1 in the ETQP formation region.
A 4-type buried collector region 3A and an n'' type buried semiconductor region 3B are formed, respectively.

Thereafter, as shown in FIG. 4, an n-type epitaxial layer 2 is laminated on the main surface of the semiconductor substrate l.

After the step of forming the epitaxial layer 2 shown in FIG. 4, as shown in FIG. 5, an insulating film 4 for isolation between elements is formed on the main surface of the epitaxial layer 2 between the semiconductor element forming regions. The element isolation insulating film 4 is formed of a silicon oxide film in which the main surface of the epitaxial layer 2 is oxidized using, for example, a silicon nitride film as a thermal oxidation mask. As mentioned above, this insulating film 4 for element isolation is, for example, 0.7 Eμ.
The thickness of the film is approximately 100 m.

After the step of forming the element isolation insulating film 4 shown in FIG. 5, a P1 type buried semiconductor region 5Δ, a P4 type Separation semiconductor regions 5B are formed respectively. Furthermore, as shown in FIG. 6, a p-type semiconductor region 6 is formed mainly on the main surface of the epitaxial layer 2 in the n-channel MISFETQn formation region.

The buried semiconductor region 5A, the isolation semiconductor region 5B, and the p-type semiconductor region 6 are formed under the above-mentioned ion implantation conditions using an impurity introduction mask shown by a dashed line with the reference numeral 16 in FIG. . The impurity introduction mask 16 is, for example,
The photoresist 1 is formed of a resin film, an insulating film such as a silicon oxide film or a silicon nitride film, or a metal film such as Afl or Mo.

In the step of forming the buried semiconductor region 5A, a p-type well region consisting of the buried semiconductor region 5A and the semiconductor region 6 is formed. In addition, in the step of forming the isolation semiconductor region 5B, the collector region (buried collector region 3A, epitaxial layer 2) of the bipolar transistor Tr electrically isolated from other regions is substantially formed, and the buried semiconductor region 3B
An n-type well region consisting of the epitaxial layer 2 and the epitaxial layer 2 is formed. Further, an isolation region is formed by the element isolation insulating film 4 and the isolation semiconductor region 5B (and the semiconductor substrate 1).

In this way, after the step of forming the element isolation insulating film 4, p-type impurities are introduced into the main surface of the epitaxial layer 2 in the 1Ml5FETQn formation region and the isolation region formation region, and the buried semiconductor region 5A, isolation By forming the semiconductor regions 5B for isolation, the semiconductor regions 5B for isolation are formed through the insulating film 4 for element isolation after forming the semiconductor regions 5B for isolation, so that impurities in the semiconductor regions 5B for isolation are removed from the insulating film 4 for isolation between elements. The isolation semiconductor region 5B can be formed at a high concentration and in contact with the element isolation insulating film 4. Therefore, since the area of the element isolation region 4 can be reduced, the semiconductor integrated circuit device can be highly integrated.

Moreover, since the isolation semiconductor region 5B can be formed in the same manufacturing process as the buried semiconductor region 5A, the manufacturing process for forming it can be reduced.

Further, the semiconductor region for isolation 5B is formed by the insulating film 4 for isolation between elements.
Since it is formed after forming the impurities, the time for stretching and diffusing the introduced impurities (heat treatment) can be shortened.

Therefore, the buried collector region 3A, the buried semiconductor region 3
Diffusion of impurities forming each of B and the buried semiconductor region 5A into the epitaxial layer 2 can be reduced, and the thickness of the epitaxial layer 2 can be reduced. The thinning of the epitaxial layer 2 shortens the range of α rays and reduces the amount of minority carriers generated.
Rough 1-error can be prevented in CuO2.

After the step of forming the buried semiconductor region 5A and isolation semiconductor region 5B shown in FIG. 6, as shown in FIG.
Bipolar transistor Tr, MI 5FETQn and Q
p is formed sequentially. Namely.

In the bipolar transistor Tr formation region, a collector region 7, a base region 8, and an emitter region 11B are formed in this order. Emitter region 11B is formed after forming electrode 10B. In the MISFETQn formation region, a gate insulating film 9, a gate electrode 10A, a source region and a drain region 11A are formed in this order. MISFET
In the Qp formation region, a gate insulating film 9, a gate electrode IOA, a source region, and a drain region 12 are sequentially formed. After forming the one-layer insulating film 13 and the connection hole 14, the respective electrodes 15 are formed.

By performing these series of manufacturing steps, B of this example
i-CuO2 is completed.

[Example ■]

Embodiment 2 is an example in which the present invention is applied to a Bi-CuO2 bipolar transistor formation region, an n-channel MISFET formation region, and a P-channel MIsFET formation region.

A schematic structure of Bi-CuO2, which is Example 2 of the present invention, is shown in FIG. 7 (a sectional view of the main part).

As shown in FIG. 7, the Bi-CuO2 of this example
The heavily doped n4 type buried collector region 5C of the bipolar transistor Tr and the heavily doped n' type buried semiconductor region 5D of the n type well region are similar to the heavily doped p4 type buried semiconductor region 5A. It is configured. That is, the buried collector region 5c and the buried semiconductor region 5D are, for example, lX
It can be formed by introducing approximately 10'' [atoms/cm2] of phosphorus (or arsenic) into the main surface of the semiconductor substrate 1 by ion implantation with an energy of 2 [MeV] and 8 degrees.

The introduced phosphorus is formed so that the impurity concentration has a peak value at a depth of approximately 2 [μm] from the surface of the semiconductor substrate l.

In this way, after forming the inter-element isolation insulating film 4,
By forming the buried collector region 5C1 of i-CuO3, the buried semiconductor region 5D, the buried semiconductor region 5A, and the semiconductor region 5B, substantially the same effect as in Example I can be obtained.

Further, a buried collector region 5C1 a buried semiconductor region 5D,
By forming the buried semiconductor region 5A and the isolation semiconductor region 5B by ion implantation after forming the element isolation insulating film 4, the buried collector region 3A and the buried semiconductor region 3B are formed as in Example I. There is no need to form. Therefore, Bi-CuO2 can be formed without forming the epitaxial layer 2 on the semiconductor substrate 1.

Note that the base body of Example H is composed of a semiconductor substrate l.

As above, the invention made by the present inventor has been specifically explained based on the above embodiments, but the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof. Of course.

For example, in Examples 1 and 2 above, the present invention was applied to Bi-CuO2, but the present invention may also be applied to 0MO8 which does not have a bipolar transistor.

〔Effect of the invention〕

Among the inventions disclosed in this application, effects obtained by typical inventions will be briefly described as follows.

An insulating film for element isolation is formed on the main surface of the substrate between the semiconductor element formation regions, and impurities are introduced into the semiconductor element formation region and the main surface of the substrate between the semiconductor element formation regions through the element isolation insulating film. Then, a buried semiconductor region and an isolation semiconductor region having an impurity concentration of the same conductivity type or opposite conductivity type and higher impurity concentration than the base body are formed in the semiconductor element formation region and the main surface portion of the base body between the semiconductor element formation regions, respectively. By doing so, the semiconductor region for isolation is formed through the insulating film for element isolation after the formation of the insulating film for element isolation, so that it can be formed at a high concentration and in contact with the insulating film for element isolation. Therefore, the area of the isolation region can be reduced and higher integration of the semiconductor integrated circuit device can be achieved.

Further, since the isolation semiconductor region can be formed in the same manufacturing process as the buried semiconductor region, the number of manufacturing steps for forming the isolation region can be reduced.

[Brief explanation of drawings]

FIG. 1 is a sectional view of a main part showing a schematic structure of Bi-0MO8 which is Example I of the present invention, and FIG. 2 is an impurity concentration distribution diagram along the line II in FIG. 1. Figure 3 is an impurity concentration distribution diagram along the line ■-■ in Figure 1, and Figures 4 to 6 are Bi-0MO8 shown in Figure 1 above.
FIG. 7 is a cross-sectional view of a main part showing the schematic structure of Bi-0MO8, which is Example 2 of the present invention. In the figure, 1... Semiconductor substrate, 2... Epitaxial layer, 3A... Buried collector region, 3B, 5A, 5C, 5
D... Buried semiconductor region, 5B... Semiconductor region for isolation, 6... Semiconductor region, 7... Collector region, 8...
・Base region, 11B... Emitter region, 9... Gate insulating film, 10A... Gate electrode, IIA, 12.
...Source region or drain region, Q...MISFE
T, Tr... Bipolar transistor.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor integrated circuit device, which includes the steps of: forming an insulating film for isolation between elements on the main surface of a substrate between semiconductor element forming regions; Impurities are introduced into the main surface of the substrate between the semiconductor element formation regions through an isolation insulating film, and the impurities are introduced into the semiconductor element formation region and the main surface of the substrate between the semiconductor element formation regions to have the same or opposite conductivity as the substrate. 1. A method for manufacturing a semiconductor integrated circuit device, comprising the steps of: forming a buried semiconductor region having a higher impurity concentration than the buried semiconductor region; and a step of forming an isolation semiconductor region at the same time. 2. The semiconductor integrated device according to claim 1, wherein the buried semiconductor region forms a well region or a buried collector region of a bipolar transistor having a higher impurity concentration at the bottom than at the surface. A method of manufacturing a circuit device. 3. The method of manufacturing a semiconductor integrated circuit device according to claim 1, wherein the insulating film for isolation between elements is formed of a silicon oxide film obtained by selectively oxidizing a base. 4. A patent characterized in that the isolation semiconductor region is formed at a shallower depth from the base body than the buried semiconductor region, and is formed so as to be in contact with the lower surface of the element isolation insulating film. A method for manufacturing a semiconductor integrated circuit device according to claim 1.