JP2611450B2 - Semiconductor integrated circuit and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit and a method for manufacturing the same, and more particularly, to a structure of a buried layer of a Bi-CMOS transistor in which a bipolar transistor and a CMOS transistor are formed on the same substrate. And a forming method.

[Conventional technology]

FIG. 5 is a longitudinal sectional view of a Bi-CMOS transistor in which a conventional P ⁺ type buried layer and an N ⁺ type buried layer are formed in a self-aligned manner.

Between the P-type silicon substrate 1 and the N-type epitaxial layer 5
The N ⁺ type buried layer 3 and the P ⁺ type buried layer 4 are formed in a self-aligned manner and have a structure in contact with each other. P ⁺ type buried layer 3
N-well region 7 in which a P-channel MOS transistor is formed is provided in a part of the epitaxial layer where P ⁺ type buried layer 4 exists. Isolation region and N
P well region 6 where channel MOS transistor is formed
Is provided. An NPN bipolar transistor is formed in another part of the epitaxial layer where the P ⁺ type buried layer 3 exists. The field insulating layer 8, the gate oxide film 9, the gate electrode 10 of the N-channel MOS transistor, the gate electrode 11 of the P-channel MOS transistor, and N
Channel source / drain region 13, P-channel source
A drain region 14 is provided, and an N-channel MOS transistor and a P-channel MOS transistor are formed respectively. Further, an N ⁺ collector electrode lead-out region 12, an external base region 15, a base region 16, and an emitter region 17 are formed.
An NPN transistor is formed together with the N-type epitaxial region 5. The P ⁺ -type buried layer 4 and the P-well region 6 around the NPN transistor serve to provide isolation between the bipolar transistors.

[Problems to be solved by the invention]

In Bi-CMOS transistor having a buried layer of a conventional P ⁺ -type and N ⁺ -type described above is in contact structures, the P ⁺ type buried layer and the N ⁺ -type buried layer one photolithography process (hereinafter PR Process)
There is an advantage that it can be formed with. This will be described below with reference to FIG.

First, as shown in FIG. 6 (A), a thermal oxide film 101 is formed on a P-type silicon substrate 1 in a thickness of 300 to 1000 °, and a silicon nitride film 102 is grown thereon in a thickness of 1000 to 3000 °.

Next, as shown in FIG. 6B, a part of the silicon nitride film 102 is anisotropically etched through a PR process. At this time, the thermal oxide film 101 serves as an etching stopper. Next, using the remaining silicon nitride film 102 as a mask,
For example, arsenic energy 40~80KeV dose 10 ¹³ to 5 × 1
Ion implantation is performed under the condition of 0 ⁴ cm ^-2 .

Next, as shown in FIG. 6 (C), thermal oxidation is performed to form an oxide film.
105 is formed in a thickness of 4000 to 10000Å, and then a silicon nitride film 102 is formed.
Then, the thermal oxide film 101 is removed by etching. Thereafter, using the oxide film 105 as a mask, a P-type impurity, for example, boron is supplied with an energy of 30 to 80 keV and a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ c.
Ion implantation is performed under the condition of m- ² .

Next, as shown in FIG. 6D, the oxide film 105 is removed by etching.

Next, as shown in FIG. 6E, an N ⁺ type buried layer 3 and a P ⁺ type buried layer 4 are formed by epitaxial growth to form an epitaxial layer 5.

However, Bi-CM having the above-described conventional buried layer
In the OS transistor, since the N ⁺ -type buried layer 3 and the P ⁺ -type buried layer 4 are in contact with each other, there is a disadvantage that the breakdown voltage therebetween is reduced. In addition, the lateral capacitance between the collector and the substrate of the bipolar transistor has a disadvantage that the depletion layer of the N ⁺ -type buried layer 3 and the P ⁺ -type buried layer 4 does not easily spread, and thus increases. On the other hand, it is necessary to increase the concentration of the N ⁺ type buried layer in order to reduce the collector resistance for speeding up. In addition, it is necessary to increase the concentration of the N ⁺ -type buried layer and the P ⁺ -type buried layer in order to enhance the latch-up. Then P ⁺ -type buried layer and the N ⁺ -type if buried layer is in contact as in the conventional structure directly, for example, the concentration of the P ⁺ -type buried layer about ^{1 × 10 18 cm -3, N} + -type When the concentration of the buried layer becomes about 5 × 10 ¹⁹ cm ⁻³ , the breakdown voltage between the buried layers becomes 4 to
The voltage becomes extremely small at 5 V, which prevents the miniaturization, and also increases the lateral capacitance between the collector and the substrate of the bipolar transistor, thereby preventing a high speed operation.

As shown in FIGS. 6B and 6C, when a region in which a high concentration impurity such as arsenic is ion-implanted under the conditions of 70 keV and 1 × 10 ¹⁶ cm ² is thermally oxidized, the oxide film 105 and the silicon Stress is applied to the boundary A of the nitride film and defects are likely to occur, causing a problem of leakage between the P ⁺ type buried layer and the N ⁺ type buried layer. Defects also adversely affect the growth of the epitaxial layer.

[Means for solving the problem]

A semiconductor integrated circuit according to a first aspect of the present invention provides a semiconductor layer formed on a semiconductor substrate of a first conductivity type and having a substantially uniform impurity distribution of a predetermined conductivity type, a bipolar transistor region provided in the semiconductor layer, and a first transistor. A first buried layer of a second conductivity type having a high concentration formed on the semiconductor substrate below the conductive channel type MOS transistor region; and an insulating isolation region of the bipolar transistor and a lower portion of the second conductive channel type MOS transistor region. In a semiconductor integrated circuit having a high-concentration first conductivity-type second buried layer formed in the semiconductor substrate, a low-concentration second conductive layer is provided in the semiconductor substrate between the first and second buried layers. A third buried layer of a mold is provided.

According to a second aspect of the invention, there is provided a method of manufacturing a semiconductor integrated circuit, comprising the steps of: forming an oxidation-resistant insulating film on a semiconductor substrate of a first conductivity type; Forming a low-concentration second conductivity type buried layer on the semiconductor substrate from which the insulating film has been removed, and forming a sidewall made of a polycrystalline silicon film on a side surface of the insulating film, and then forming a second conductive buried layer. Forming a first buried layer of the second conductivity type having a high concentration in the buried layer of the second conductivity type excluding the lower portion of the sidewall by introducing a type impurity, and removing the sidewall and removing the insulating layer after removing the sidewall. Forming an oxide film on the buried layer of the second conductivity type and the first buried layer using a film as a mask, removing the insulating film used as a mask, and removing the first conductivity type using the oxide film as a mask; Of high concentration in the semiconductor substrate by introducing impurities of Forming a second buried layer of one conductivity type; and forming a semiconductor layer of a predetermined conductivity type over the entire surface after removing the oxide film used as a mask. .

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a sectional view of a first embodiment of the present invention.

In FIG. 1, an N ⁺ -type buried layer 3 and a P ⁺ -type buried layer 4 are formed on a silicon substrate 1 between a P-type silicon substrate 1 and an N-type epitaxial region 5 formed thereon. Yes,
Further, an N ⁻ -type buried layer 2 having a lower impurity concentration than that of the N ⁺ -type buried layer 3 is formed in the silicon substrate 1 in the boundary region.
N ⁺ type in the partial region of the buried layer 3 existing epitaxial layer is provided with the N-well region 7 where the P-channel MOS transistor is formed, also exists the epitaxial layer of N ⁺ -type buried layer 3 A bipolar transistor is formed in another part of the region. In a part of the epitaxial layer where the P ⁺ -type buried layer 4 exists, an insulating isolation region of a bipolar transistor and a P well region 6 in which an N-channel MOS transistor is formed are provided. A field insulating layer 8, a gate oxide film 9, a gate electrode 10 of an N-channel MOS transistor,
Gate electrode 11, N-channel source / drain region 13, P-channel source / drain region of channel MOS transistor
14, an N-channel MOS transistor and a P-channel MOS transistor are formed. Further, an N ⁺ collector electrode lead-out region 12, a P ⁺ -type external base region 15, a P-type base region 16, and an N ⁺ emitter region 17 are formed, and an NPN transistor is formed together with the N-type epitaxial region 5. The P ⁺ -type buried layer 4 and the P-well region 6 around the NPN transistor serve to provide isolation between the bipolar transistors.

In the first embodiment thus configured, since the N ⁻ -type buried layer 2 exists between the N ⁺ -type buried layer 3 and the P ⁺ -type buried layer 4, the N ⁺ -type buried layer The electric field applied to the silicon substrate 1 between the buried layer 3 and the P ⁺ type buried layer 4 is reduced, and the breakdown voltage between the buried layers is increased. Further, since the depletion layer easily spreads in N ⁻ type buried layer 2, the lateral capacitance between the collector and the substrate of the bipolar transistor can be reduced.

Next, a method of forming a buried layer, which is a feature of the first embodiment, will be described as a second embodiment with reference to FIG.

First, as shown in FIG. 2 (A), a P-type silicon substrate 1
A thermal oxide film 101 is formed thereon in a thickness of 300 to 1500 .ANG., And a silicon nitride film 102 is grown thereon in a thickness of 1000 to 4000.

Next, as shown in FIG. 2B, patterning is performed through a PR process, and a part of the silicon nitride film 102 is anisotropically etched. At this time, the thermal oxide film 101 serves as an etching stopper. Next, using the remaining silicon nitride film 102 and the underlying thermal oxide film 101 as a mask, an N-type impurity such as phosphorus is used at an energy of 30 to 50 keV and a dose of 1 × 10 ¹³ to 1 × 10 ¹⁴ c.
Ions are implanted under the condition of m ⁻² to form an N ⁻ type buried layer 2.

Next, as shown in FIG.
3 grows to a thickness of 2000-4000 mm.

Next, as shown in FIG. 2D, the polycrystalline silicon film is etched to form a sidewall 104 on the side wall of the silicon nitride film 102. At this time, the thermal oxide film 101 serves as an etch-back stopper and does not damage the P-type silicon substrate 1. Next, using the silicon nitride film 102 and the sidewalls 104 as a mask, an N-type impurity such as arsenic is used at an energy of 40 to 80 keV and a dose of 1 × 10 ¹⁵ to 1 × 1.
Ion implantation is performed under the condition of 0 ¹⁶ cm ⁻² to form an N ⁺ type buried layer 3.

Next, as shown in FIG. 2E, the side wall 104 formed of polycrystalline silicon is removed by etching.

Next, as shown in FIG. 2 (F), thermal oxidation is performed to form an oxide film.
105 is formed in a thickness of 4000 to 10000Å, and then a silicon nitride film 102 is formed.
Then, the thermal oxide film 101 is removed by etching. Thereafter, using the oxide film 105 as a mask, a P-type impurity, for example, boron is supplied with an energy of 30 to 80 keV and a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ c.
Ion implantation is performed under the condition of m ⁻² to form a P ⁺ type buried layer 4.

Next, as shown in FIG. 2 (G), the oxide film 105 is removed by etching, and then, as shown in FIG. 2 (H), the N type epitaxial layer 5 is formed by epitaxial growth.

By the above method, the N ⁺ -type buried layer 3 and the P ⁺ -type buried layer 4 and the N ⁻ -type buried layer 2 having a low impurity concentration sandwiched therebetween can be formed in the self-alignment.

According to the second embodiment thus manufactured, P ⁺
The withstand voltage between the buried layer and the N ⁺ -type buried layer can be increased to 10 to 15 V, which is two to three times higher than that of the conventional one.

As shown in FIGS. 2B to 2F, the oxide film 10
Because it is a low concentration of ion implantation at lower energy than the conventional example is the boundary between the silicon nitride film when forming a 5, defects due to stress hardly occurs as compared with the conventional example, P ⁺ -type buried Leakage between the embedded layer and the N ⁺ type buried layer can be suppressed. Therefore, the transistor yield can be improved.

 FIG. 3 is a sectional view of a third embodiment of the present invention.

In FIG. 3, below the P-channel MOS transistor region and the bipolar transistor region between the P-type silicon substrate 1 and the N-type epitaxial region 5 formed thereon, an N ⁺ type buried layer 3 is formed. A P ⁺ -type buried layer 4 and an N ^-- type buried layer 2A exist below the channel MOS transistor region and the bipolar transistor insulating region. N ^- type buried layer 2A is formed to extend in the lower portion of the P ⁺ -type buried layer 4 and the N ⁺ -type between the buried layer 3 and the P ⁺ -type buried layer 4, the P ⁺ -type buried Layer 4 is electrically separated from P-type silicon substrate 1. Also, a P ⁺ type buried layer 4, an N ⁻ type buried layer 2 A, an N ⁺ type buried layer 3
Have a structure formed by self-alignment.

In the third embodiment, the N ⁺ type buried layer 3 and the P ⁺
In addition to increasing the breakdown voltage between them, the structure is resistant to α-ray soft errors. For example, when forming an SRAM using Bi-CMOS, α rays enter the P-type silicon substrate 1 and generated electrons cause a soft error collected in the N ⁺ drain region 13 of the N-channel MOS transistor constituting the memory cell. In the case of the third embodiment, a depletion layer spreads between the N ⁻ -type buried layer 2A and the P ⁺ -type buried layer 4 to generate a potential.
Therefore, in order for electrons generated by α rays to reach the N ⁺ drain region 13 of the N-channel MOS transistor, energy for exceeding this potential is required, and the electrons and holes recombine in the depletion layer. As a result, the number of electrons collected in the N ⁺ drain region 13 is greatly reduced, and a soft error hardly occurs. The structure in which the N ^-- type buried layer 2A is present is 1.5 to 3 times as strong as a soft error due to α-rays compared to the conventional structure without the N ^-- type buried layer.

Next, a manufacturing method of the third embodiment will be described with reference to FIG. 4 as a fourth embodiment.

First, as shown in FIG. 4 (A), a P-type silicon substrate 1
A thermal oxide film 101 is formed thereon in a thickness of 300 to 1500 、, and a silicon nitride film 102 is grown thereon in a thickness of 1000 to 4000 Å.

Next, as shown in FIG. 4B, patterning is performed through a PR process, and a part of the silicon nitride film 102 is anisotropically etched. At this time, the thermal oxide film 101 serves as an etching stopper. Next, using the remaining silicon nitride film 102 and the underlying thermal oxide film 101 as a mask, an N-type impurity such as phosphorus is used at an energy of 50 to 150 keV and a dose of 1 × 10 ^{12 to} 5 × 10 ^13.
Ion implantation is performed under the condition of cm- ² .

Next, as shown in FIG. 4 (C), a high-temperature heat treatment at 1000 ° C. to 1100 ° C. is performed to deeply implant the implanted N-type impurities to form an N ⁻ -type buried layer 2A. Next, the polycrystalline silicon film 10
3 is grown to a thickness of 2000-4000 mm.

Next, as shown in FIG. 4D, the polycrystalline silicon film is etched to form side walls 104 on the side walls of the silicon nitride film 102. At this time, the thermal oxide film 101 serves as an etching stopper, and does not damage the silicon substrate 1. Next, using the silicon nitride film 102 and the side wall 104 as a mask, a P-type impurity, for example, boron is supplied with an energy of 30 to 80 keV and a dose of 1 × 10 ^{13 to} 5 × 10 ¹⁴ c.
Ion implantation is performed under the condition of m ⁻² to form a P ⁺ type buried layer 4.

Next, as shown in FIG. 4E, the sidewalls 104 formed of polycrystalline silicon are removed by etching.

Next, as shown in FIG. 4 (F), thermal oxidation is performed to form an oxide film.
105 is formed to a thickness of 4000 to 10000. Then, the silicon nitride film 102 and the thermal oxide film 101 are removed by etching. After that, using the oxide film 105 as a mask, an N-type impurity, for example, arsenic is supplied with an energy of 40 to 80 keV and a dose of 1 × 10 ¹⁵ to 1 × 1.
Ion implantation is performed under the condition of 0 ¹⁶ cm ⁻² to form an N ⁺ type buried layer 3.

Next, as shown in FIG. 4 (G), the oxide film 105 is removed by etching, and then, as shown in FIG. 4 (H), the N-type epitaxial layer 5 is formed by epitaxial growth.

By the above method, the N ⁺ type buried layer 3, the P ⁺ type buried layer 4,
N ^- type buried layer 2 can be formed in a cell-aligned manner with one mask.

〔The invention's effect〕

As described above, the present invention provides a highly buried second conductivity type first buried layer formed on a semiconductor substrate below a bipolar transistor region and a first conductivity channel type MOS transistor region, and a bipolar transistor insulating layer. A high concentration second conductive type second transistor formed on the semiconductor substrate below the isolation region and the second conductive channel type MOS transistor region.
By providing a low-concentration third buried layer of the second conductivity type in the semiconductor substrate between the first buried layer and the second buried layer,
This has the effect of reducing the electric field applied between the buried layers and increasing the breakdown voltage. Further, since the depletion layer easily spreads in the third buried layer, there is also an effect that the lateral capacitance between the collector and the substrate can be reduced. Furthermore, the occurrence of defects due to stress during thermal oxidation is reduced, and the first buried layer and the second
Since the leakage between the buried layers hardly occurs, the yield of the semiconductor integrated circuit can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view of a first embodiment of the present invention, and FIG.
Sectional view of the semiconductor chip for explaining the manufacturing method of the third embodiment, FIG. 3 is a sectional view of the third embodiment, and FIG. 4 is a cross section of the semiconductor chip for explaining the manufacturing method of the fourth embodiment. FIG. 5 is a cross-sectional view of a conventional example, and FIG. 6 is a cross-sectional view of a semiconductor chip for explaining a manufacturing method of the conventional example. 1 ... P-type silicon substrate, 2,2A ... N ⁺ type buried layer, 3 ...
N ⁺ type buried layer, 4 ... P ⁺ type buried layer, 5 ... N type epitaxial layer, 6 ... P well region, 7 ... N well region, 8
... Field insulating layer, 9 gate oxide film, 10 gate electrode, 11 gate electrode, 12 N ⁺ collector electrode lead-out region, 13 N-channel MOS source / drain region, 14 P Channel MOS source / drain regions, 15 ...
… P ^{+ type} external base region, 16 …… P type base region, 17 ……
N ⁺ type emitter region.

Claims (3)

(57) [Claims] 1. A semiconductor layer formed on a semiconductor substrate of a first conductivity type and having a substantially uniform impurity distribution of a predetermined conductivity type, a bipolar transistor region provided in the semiconductor layer, and a first conductive channel type MOS transistor. A first buried layer of the second conductivity type having a high concentration formed on the semiconductor substrate below the region, and a first buried layer formed on the semiconductor substrate below the isolation region of the bipolar transistor and the second conductive channel type MOS transistor region; And a second buried layer of a first conductivity type having a high concentration and a third concentration of a second conductivity type having a low concentration in the semiconductor substrate between the first and second buried layers. A semiconductor integrated circuit having a buried layer. 2. The semiconductor integrated circuit according to claim 1, wherein said third buried layer extends below said second buried layer. 3. A step of forming an oxidation-resistant insulating film on a semiconductor substrate of a first conductivity type, and selectively removing the insulating film and introducing an impurity of a second conductivity type to remove the insulating film. Forming a low concentration second conductivity type buried layer in the semiconductor substrate, forming a sidewall made of a polycrystalline silicon film on a side surface of the insulating film, and then introducing a second conductivity type impurity into the sidewall. Forming a first buried layer of the second conductivity type having a high concentration in the buried layer of the second conductivity type excluding a lower portion of the first conductive type, and removing the sidewalls and then using the insulating film as a mask to form the second conductive type buried layer. Forming an oxide film on the mold buried layer and the first buried layer, removing the insulating film used as a mask, and introducing a first conductivity type impurity using the oxide film as a mask to form the semiconductor; A second buried layer of the first conductivity type having a high concentration is formed in the substrate. Process and method of manufacturing a semiconductor integrated circuit which comprises a step of forming a semiconductor layer of a predetermined conductivity type on the entire surface after removing the oxide film as a mask to.