JP2924038B2 - Semiconductor device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which a CMOS transistor and a bipolar transistor are formed on the same semiconductor substrate, and more particularly to a semiconductor device having a high breakdown voltage MOS transistor.

[Conventional technology]

Conventionally, a semiconductor device (BiCMOS) in which a CMOS transistor and a bipolar transistor are formed on the same semiconductor substrate,
In recent years, various attempts have been made because low power consumption operation of a CMOS transistor and high speed operation and high drive capability of a bipolar transistor can be realized simultaneously.

In some cases, it is necessary to configure such a BiCMOS together with a high breakdown voltage MOS transistor, a rewritable read only memory (EPROM) element including a double gate structure and a MOS transistor, and the like.

FIG. 4 shows a cross-sectional view of an example of the above-described semiconductor integrated circuit. This semiconductor integrated circuit includes a low breakdown voltage bipolar transistor 18, a low breakdown voltage N-type MOS transistor 19, and a low breakdown voltage P-type MOS transistor.
It comprises a transistor 22, an EPROM element 20, a high voltage N-type transistor MOS21, and a high voltage P-type MOS transistor 23.

The bipolar transistor 18 is formed in the N-type epitaxial layer 5 based on the P-type semiconductor substrate 1 via the N ⁺ -type buried layer 3. N ⁺ type polysilicon 9a, N ⁺ type diffusion layer 1
A collector portion is formed by 3a, a base portion is formed by a P-type active base diffusion layer 12 and a P ⁺ type diffusion layer 13, and an emitter portion is formed by an N ⁺ type diffusion layer 13a and an emitter electrode 11 made of N ⁺ type polysilicon. Are formed. 8 is a field oxide film, 16 is an interlayer insulating film, and 17 is an aluminum electrode.

Low breakdown voltage N-type MOS transistor 19, EPROM element 20, high breakdown voltage N
Type MOS transistor 21, the P-type well 6 arranged in connection with the P ⁺ -type buried layer 4 in the N-type epitaxial layer 5 provided on the P-type semiconductor substrate 1 through the P ⁺ -type buried layer 4 Is formed. The sources and drains of the transistors 19 and 20 and the source of the transistor 21 are N ⁺ type diffusion layers 13a.
The drain of the high-breakdown-voltage N-type MOS transistor 21 is formed from the N ⁺ -type diffusion layer 13a and the P-type low-concentration drain 15. The gate electrodes of transistors 19 and 21 are N
⁺ Formed from polysilicon 9, a gate electrode of the EPROM element 20 is formed of the control gate and the floating gate 10 for consisting N ⁺ -type polysilicon 9. 8 is a field oxide film, 16 is an interlayer insulating film, and 17 is an aluminum electrode.

High breakdown voltage P-type MOS transistor 23 and low breakdown voltage P-type MOS
The transistor 22 includes an N-type epitaxial layer 5 provided on the P-type semiconductor substrate 1 via the N ⁺ type buried layer 3 and an N-type well 7 provided in the N-type epitaxial layer 5.
Is formed. The source of the source-drain and the transistor 23 of the transistor 22 is formed from a P ⁺ -type diffusion layer 13, the drain of the transistor 23 is formed from a P ⁺ -type diffusion layer 13 and the N-type lightly doped drain 14. 8 is a field oxide film, 16 is an interlayer insulating film, and 17 is an aluminum electrode.

The high-voltage MOS transistors 21 and 23 are used for a program-related circuit including an internal booster circuit for the EPROM element 20,
A voltage of 10 to 25 V is applied. In order to secure this withstand voltage, the N-type epitaxial layer 5 is made thick (for example, 3 to 5 μm).
m), but the thickness of the N-type epitaxial layer 5 in the high breakdown voltage portion where the high breakdown voltage MOS transistors 21 and 23 are formed and the low breakdown voltage portion where the CMOS logic circuit and the small signal circuit are formed are the same. Since the high breakdown voltage MOS transistor coexists up to the N-type epitaxial layer of the low breakdown voltage portion which does not require a thick N-type layer, the thickness becomes large.

[Problems to be solved by the invention]

Since the high breakdown voltage MOS transistor coexists up to the N-type epitaxial layer of the low breakdown voltage portion, the thickness of the transistor increases, so that the characteristics of the low breakdown voltage transistor are significantly reduced. In particular, the high frequency characteristics of the bipolar transistor are significantly reduced. For example,
Cutoff frequency f _T is greatly reduced, the operating speed of such ECL circuit constituted by bipolar transistors is delayed.

Also, since the N-type epitaxial layer is thick, a deep P ⁺ -type element isolation diffusion layer is required, and the diffusion in the lateral direction of the diffusion layer is also large. Becomes difficult.

[Means for solving the problem]

The semiconductor device of the present invention comprises a high breakdown voltage first conductivity type MOS transistor, a high breakdown voltage second conductivity type MOS transistor, a low breakdown voltage first conductivity type MOS transistor, and a low breakdown voltage second conductivity type MOS transistor on the same semiconductor substrate. In a semiconductor device including a transistor and a low breakdown voltage bipolar transistor, the first
A first second conductivity type well is provided on a surface of the conductivity type semiconductor substrate, and a second conductivity type buried layer is provided on a part of the surface of the first second conductivity type well. A first conductivity type buried layer is provided on a part of the surface of the first semiconductor substrate at a position away from the second conductivity type well, and the first conductivity type semiconductor including the first second conductivity type well is provided. A second conductivity type epitaxial layer is provided on the substrate; a second second conductivity type well is provided on a surface of the second conductivity type epitaxial layer immediately above the second conductivity type buried layer; Except immediately above the two-conductivity-type well, the surface of the second-conductivity-type epitaxial layer including at least the portion immediately above the first-conductivity-type buried layer has a first-conductivity-type directly connected to the first-conductivity-type semiconductor substrate. A well is provided, and a portion immediately above the second conductivity type buried layer is provided. A high breakdown voltage first conductivity type MOS transistor formed on the second conductivity type epitaxial layer immediately above the first second conductivity type well, and a low breakdown voltage MOS transistor provided on the second second conductivity type well. A first conductivity type MOS transistor, a low breakdown voltage second conductivity type MOS transistor provided in the first conductivity type well immediately above the first conductivity type buried layer, and a position other than immediately above the first conductivity type buried layer. First
A high withstand voltage second conductivity type MOS transistor provided in the conductivity type well.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

 FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention.

An N-type well 2, an N ⁺ -type buried layer 3, and a P ⁺ -type buried layer 4 are provided on a P-type semiconductor substrate 1, and a bipolar transistor is provided above the N ⁺ -type buried layer 3 provided on the P-type semiconductor substrate 1. 18
There are formed, N-type in the upper part of the N ⁺ -type buried layer 3 formed on the well 2 low breakdown voltage P-type MOS transistor 22 is formed, P-type P ⁺ -type buried layer 4 formed on the semiconductor substrate 1 A low withstand voltage N-type MOS transistor 19 is formed on the upper part of FIG. An N-type epitaxial layer 5 having a thickness of 1 to 2 μm is provided on a P-type semiconductor substrate 1 including an N-type well 2, an N ⁺ -type buried layer 3 and a P ⁺ -type buried layer 4, and the P ⁺ -type buried layer 4 is A P-type well 6 connected to the P-type semiconductor substrate 1 is provided in a part of the N-type epitaxial layer 5 including the N-type epitaxial layer 5.
A MOS transistor 19, an EPROM element 20, and a high breakdown voltage N-type MOS transistor 21 are formed, and a bipolar transistor 18 is formed in the N-type epitaxial layer 5 on the N ⁺ type buried layer 3.
The N-type epitaxial layer 5 on the N-type well 2 including the N ⁺ -type buried layer 3 has a low-breakdown-voltage P-type MOS transistor 22 and a high-breakdown-voltage P-type.
A MOS transistor 23 is formed.

N ⁺ is formed on the -type buried layer 3 N ⁺ -type polysilicon 9a, N
^The collector portion is formed by the ⁺ type diffusion layer 13a, the base portion is formed by the P type active base diffusion layer 12, and the P ⁺ type diffusion layer 13, and the N ⁺ type diffusion layer 13a, the emitter electrode made of N ⁺ type polysilicon. An emitter portion is formed by 11, a field oxide film 8, an interlayer insulating film 16, and an aluminum electrode 17 constitute a bipolar transistor 18.

The source of the low-voltage N-type MOS transistor 19, the source-drain and a high-voltage N-type MOS transistor 21 of the EPROM element 20 is formed of N ⁺ -type diffusion layer 13a, a drain of the high voltage N-type MOS transistor 21 is the N ⁺ diffusion It is formed from the layer 13a and the P-type low-concentration drain 15. Transistor 19,2
One gate electrode is formed from N ⁺ type polysilicon 9 and has an EPR
The gate electrode of the OM element 20 is formed by a control gate made of N ⁺ polysilicon 9 and a floating gate 10. 8 is a field oxide film, 16 is an interlayer insulating film,
17 is an aluminum electrode.

N-type well 7 provided in N-type epitaxial layer 5
The source / drain of the low breakdown voltage P-type MOS transistor 22 and the source of the high breakdown voltage P-type MOS transistor 23 are P
⁺ Formed from type diffusion layer 13, the drain of the transistor 23 is formed from a P ⁺ -type diffusion layer 13 and the N-type lightly doped drain 14. 8 is a field oxide film, 16 is an interlayer insulating film,
17 is an aluminum electrode.

In the structure of this embodiment, the high breakdown voltage N-type MOS transistor 21
There is no P ⁺ -type buried layer 4 between the lower P-type well 6 and the P-type semiconductor substrate 1. Therefore, even if the N-type epitaxial layer 5 becomes thin, the depletion layer extending from the drain of the high breakdown voltage N-type MOS transistor 21 collides with the P ⁺ type buried layer 4,
The phenomenon that avalanche breakdown occurs to lower the breakdown voltage does not occur.

Further, since the N ⁺ -type buried layer 3 under the high-breakdown-voltage P-type MOS transistor 23 is eliminated and the N-type well 2 is provided in the P-type semiconductor substrate 1, even if the thickness of the N-type epitaxial layer 5 is reduced, The depletion layer extending from the drain of the high-breakdown-voltage P-type MOS transistor 23 is composed of the N-type epitaxial layer 5 and the P-type semiconductor substrate 1.
Even if it extends beyond the interface with the interface, the breakdown voltage does not decrease.

Next, with reference to the vertical cross-sectional views of FIGS. 2A to 2D, a description will be given of a process of forming main components of the present embodiment.

First, as shown in FIG.
After an oxide film 24 having a thickness of 200 to 700 ° is formed thereon, the photoresist film 25 is used as a mask to implant an N-type impurity, for example, phosphorus 26 by ion implantation at a dose of 1 × 10 ¹² to 1 × 10 ¹³ cm ^−2. After the introduction into the P-type semiconductor substrate 1, the pressing is performed at a high temperature of 1100 to 1200 ° C. for 5 to 8 hours. The N-type well 2 having a depth of 4 to 7 μm can be formed by the indentation heat treatment.

Next, as shown in FIG.
The N ⁺ type buried layer 3 is formed by implanting arsenic 27 by ion implantation at a dose of 1 × 10 ¹⁵ to 1 × 10 ¹⁶ cm ⁻² using the mask 25a as a mask.

Next, as shown in FIG.
The P ⁺ -type buried layer 4 is formed by implanting, for example, boron 28 by ion implantation at a dose of 1 × 10 ¹³ to 10 ¹⁵ cm ^{−2 using} 25b as a mask.

Next, as shown in FIG. 2D, an N-type epitaxial layer 5 having a thickness of 1 to 2 μm is grown.

Thereafter, the structure shown in FIG. 1 is manufactured by a normal BiCMOS manufacturing technique.

FIG. 3 is a longitudinal sectional view of a second embodiment of the present invention. This embodiment is an example in which the present invention is applied to an EPROM in a BiCMOS integrated circuit including a ROM / RAM type CPU and a built-in EPROM. The configuration of the other transistors is the first.
This is the same as the embodiment.

An N-type well 2, which is an important component for forming a high-breakdown-voltage P-type MOS transistor shown in the first embodiment, is provided on a P-type semiconductor substrate 1 below an EPROM element. EPROM
Around the N-type well 2 under the element, a P ⁺ type buried layer 4 is formed.
Is provided. N provided on P-type semiconductor substrate 1
In the epitaxial layer 5, the area immediately below the EPROM element and the P
The portion immediately above the ⁺ -type buried layer 4 is converted to a P-type well 6. P ⁺ type buried layer 4 and P type well 6 directly above and EPRO
An N-type epitaxial layer 5 exists between the P-type well 6 immediately below the M element. That is, the entire periphery of the P-type well 6 immediately below the EPROM element is an N-type semiconductor layer.

The gate electrode of the EPROM element 20 is formed of a control gate made of N ⁺ type polysilicon 9 and a floating gate 10, and the source and drain are formed of an N ⁺ diffusion layer 13a. N ⁺ -type polysilicon 9a is connected to the N-type epitaxial layer 5 through the N ⁺ diffusion layer 13a, N ⁺ -type polysilicon
The power supply voltage Vcc is applied to the aluminum electrode 17 on 9a. 8 is a field oxide film, and 16 is an interlayer insulating film.

The EPROM element applies a high voltage of 10 V or more to the control gate during programming, and at this time, a substrate current on the order of mA flows through the substrate of the EPROM element (P-type well 6 in this embodiment). If the P-type well 6 immediately below the EPROM element is not covered with the N-type semiconductor layer, this substrate current becomes a noise source that causes latch-up, data destruction of the built-in RAM in the same substrate, and the like. In this embodiment, the P-type well 6 immediately below the EPROM element is covered with an N-type semiconductor layer (N-type well 2, N-type epitaxial layer 5), and this N-type semiconductor layer is an N ⁺ diffusion layer 13a.
Since you are connected to N ⁺ -type polysilicon 9a applied to Vcc through a semiconductor substrate current generated in the P-type well 6 immediately below EPROM element of N-type which covers the P-type well 6 immediately below EPROM element Absorbed by the layer. That is, an N-type semiconductor layer (N-type well 2, N-type epitaxial layer 5), an N ⁺ type polysilicon 9a applied to Vcc, and an N ⁺ diffusion layer 13a intermediate these.
Form a kind of leak path for the substrate current of the EPROM element. Therefore, the substrate current of the EPROM element does not flow into other transistors and elements, and the influence of noise on other transistors and elements can be prevented.

The P ⁺ -type buried layer 4 around the N-type well 2 below the EPROM element and the P-type well 6 immediately above the P ⁺ -type buried layer 4 are used for junction separation for the above-described leak path, and for the element between the EPROM element and another transistor. Has the role of separation.

〔The invention's effect〕

As described above, the present invention relates to a semiconductor device having a high breakdown voltage MOS transistor and a BiCMOS on the same semiconductor substrate, wherein a second conductivity type well is provided on a first conductivity type semiconductor substrate and a second conductivity type well is provided. A second conductivity type epitaxial layer is provided on a one conductivity type semiconductor substrate to form a first conductivity type MOS transistor capable of high voltage operation, and is connected to the first conductivity type semiconductor substrate in the second conductivity type epitaxial layer. 2nd conductivity type MO that can be operated with high withstand voltage by providing 1st conductivity type well
By forming the S transistor, a high-concentration second conductivity type buried layer under the first conductivity type MOS transistor capable of high withstand voltage operation and a second conductivity type MOS capable of high withstand voltage operation
It is not necessary to provide a high-concentration first-conductivity-type indentation layer under the transistor, and the thickness of the second-conductivity-type epitaxial layer can be reduced.

As a result, the high-frequency characteristics of the bipolar transistor can be maintained well without lowering the withstand voltage of the high-voltage MOS transistor.

Further, since the N-type epitaxial layer is thin, a deep element isolation diffusion layer is not required, and diffusion in the lateral direction of the diffusion layer is small. Therefore, a large isolation region is not required, and the size of transistors, elements, and the like can be reduced. It becomes easier.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view of a first embodiment of the present invention, FIGS. 2 (a) to 2 (d) are longitudinal sectional views showing a manufacturing method of the first embodiment in the order of steps, and FIG. And FIG. 4 is a longitudinal sectional view of the prior art. DESCRIPTION OF SYMBOLS 1 ... P type semiconductor substrate, 2,7 ... N type well, 3 ... N ⁺ type buried layer, 4 ... P ⁺ type buried layer, 5 ... N type epitaxial layer,
6 ... P-type well, 8 ... Field oxide film, 9,9a ... N ⁺ type polysilicon, 10 ... Floating gate, 11 ... Emitter electrode, 12 ... Active base diffusion layer, 13 ... P ⁺ type diffusion layer, 13a ... N
⁺ -Type diffusion layer, 14: N-type low-concentration drain, 15: P-type low-concentration drain, 16: interlayer insulating film, 17: aluminum electrode, 18: bipolar transistor, 19: low-breakdown-voltage N-type MOS transistor, 20: EPROM element , 21 ... High voltage N-type MOS transistor,
22: low breakdown voltage P-type MOS transistor, 23: high breakdown voltage P-type MOS transistor, 24: oxide film, 25, 25a, 25b: photoresist film, 26: phosphorus, 27: arsenic, 28: boron.

Claims (1)

(57) [Claims] 1. A high withstand voltage first conductivity type MO on the same semiconductor substrate.
In a semiconductor device including an S transistor, a high breakdown voltage second conductivity type MOS transistor, a low breakdown voltage first conductivity type MOS transistor, a low breakdown voltage second conductivity type MOS transistor, and a low breakdown voltage bipolar transistor, A first conductivity type well is provided on a surface of the semiconductor substrate; a second conductivity type buried layer is provided on a part of a surface of the first second conductivity type well; The first type at a position away from the conductive well;
A first conductivity type buried layer is provided on a part of the surface of the semiconductor substrate, and a second conductivity type epitaxial layer is provided on the first conductivity type semiconductor substrate including the first second conductivity type well; A second second conductivity type well is provided on the surface of the second conductivity type epitaxial layer immediately above the second conductivity type buried layer, and at least the first conductivity type except immediately above the first second conductivity type well. A first conductivity type well directly connected to the first conductivity type semiconductor substrate is provided on a surface of the second conductivity type epitaxial layer including a portion immediately above the mold buried layer, and just above the second conductivity type buried layer And a high-breakdown-voltage first-conductivity-type MOS transistor formed in the second-conductivity-type epitaxial layer immediately above the first second-conductivity-type well, and a low-voltage transistor provided in the second second-conductivity-type well. Withstand voltage first conductivity type MOS transistor A low-breakdown-voltage second conductivity type provided in a well of the first conductivity type well immediately above the buried layer of the first conductivity type;
A semiconductor device comprising: a MOS transistor; and a high-breakdown-voltage second conductivity-type MOS transistor provided in the first conductivity-type well at a position other than immediately above the first conductivity-type buried layer.