JPH08316335A - Semiconductor device and fabrication thereof - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device in which excellent soft error resistance, high speed and low power consumption similar to those of MOSFET having SOI structure are realized without having any adverse effect on the current drive characteristics. CONSTITUTION: In a semiconductor device having a MOSFET, the lower part between the drain region 12 and the source region 13 of the MOSFET is insulated electrically from a semiconductor substrate 11 through insulation layers 19, 19' and 20 except at least a part thereof.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a manufacturing method thereof, and more particularly to a semiconductor device having a MOS field effect transistor (hereinafter referred to as MOSFET) and a manufacturing method thereof.

[0002]

2. Description of the Related Art FIG. 6 shows a sectional structure of a so-called bulk MOSFET which is a MOSFET having a normal structure. Figure 6
For example, taking an n-channel MOSFET as an example, a drain region 102 and a source region 103 made of an n-type diffusion layer are formed on the surface side of a p-type semiconductor substrate 101, and a channel region 104 between both regions 102 and 103 is formed. A gate electrode 106 is provided above through a gate insulating film 105.
Are arranged, for example, LOCOS (Local Oxidation of Sili
The structure is such that element isolation is achieved by the element isolation regions 107 and 108 of the con) structure. Bulk M of such structure
In the OSFET, the drain region 102 and the source region 10
3 and the channel region 104 are all the semiconductor substrate 101.
Since it is connected to, there are the following problems.

That is, when charged particles such as α rays enter the drain region 102, excess minority carriers generated inside the semiconductor substrate 101 are collected in the drain region 102, so that the node voltage of the drain region 102 is increased. Changes, the soft error is likely to occur. Here, the soft error refers to a malfunction of the temporary storage circuit or its peripheral circuits caused by a small amount of α-rays emitted from the package material or Al wiring on the chip. In addition, the drain region 102 or the source region 10
3 forms a junction capacitance between the semiconductor substrate 101 and the semiconductor substrate 101, so that in the circuit operation, a component of delay time and current consumption occurs due to the charging and discharging of the junction capacitance, resulting in higher speed and lower power consumption. It was one of the obstacles.

In order to solve such a problem, as shown in FIG. 7, a drain region 112 and a source region 113 of a silicon thin film are formed on an insulating substrate 111, and a channel between the regions 112 and 113 is formed. Area 114
An SOI (Silicon on) structure in which a gate electrode 116 is provided on the gate insulating film 115 to realize a complete element isolation structure
There is a MOSFET of Insulator structure.

[0005]

However, the SOI
In the MOSFET having the structure, the insulating substrate (oxide film) 11
Since the heat conduction of No. 1 is not good, the temperature rise is large due to self-heating, the current driving capability is deteriorated, negative resistance appears in the saturation region of the drain current, or majority carriers generated in the channel region 114 easily accumulate. for,
There is a problem that the substrate potential changes and a kink occurs in the current characteristic.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a soft error resistance and a high speed which are as good as those of an SOI structure MOSFET without adversely affecting the current driving characteristics. It is to provide a semiconductor device and a method of manufacturing the same, which can realize high power consumption and low power consumption.

[0007]

In order to achieve the above object, in the semiconductor device according to the present invention, the lower part of the region is insulated except at least a part of the region extending from the drain region to the source region of the MOSFET. A layer is used to electrically insulate the semiconductor substrate.

In the first manufacturing method according to the present invention, a step of forming a groove having a first depth in a semiconductor substrate, filling an insulating material in the groove, and insulating the semiconductor region adjacent to the semiconductor region exposed at the top of the substrate. A step of removing a part of the object to a second depth which is equal to or less than the junction depth of the diffusion layer formed on the semiconductor surface and is shallower than the first depth;
A step of epitaxially growing a semiconductor with a thickness equal to or more than the depth of, a step of selectively polishing only the semiconductor using an insulator as a stopper to form a thin film semiconductor region connected to a semiconductor substrate, and exposing the substrate surface. M on the existing semiconductor region
And a step of forming an OSFET.

In the second manufacturing method according to the present invention, a step of ion-implanting a gas in which a compound with a semiconductor serves as an insulator into the inside of the substrate from above a shielding mask provided on the surface of the semiconductor substrate, and after removing the shielding mask A step of performing high temperature heat treatment, a step of forming an element isolation region, and a step of forming a MOSFET on the semiconductor region exposed on the substrate surface are used.

In the third manufacturing method according to the present invention, a step of forming an element isolation region on a semiconductor substrate and a gate electrode of a MOSFET, and a gas in which a compound of a semiconductor serves as an insulator is used for the element isolation region and the gate. A step of implanting ions into the substrate using the electrodes as a shield mask, a step of performing a high temperature heat treatment, and a step of forming M on the semiconductor region exposed on the substrate surface.
And a step of forming an OSFET.

[0011]

In the semiconductor device having the above structure, the MOSFET
In the region extending from the drain region to the source region, for example, a lower portion of the drain region is electrically insulated from the inside of the substrate by an insulating layer, so that no junction capacitance is formed between the drain region and the substrate and Even when charged particles such as α-rays are incident on, the excess minority carriers generated inside the substrate are not collected in the drain region. Further, since the lower part of at least a part of the region from the drain region to the source region of the MOSFET is connected to the inside of the substrate, thermal efficiency is not impaired.

In the first manufacturing method, a groove having a first depth is formed in a semiconductor substrate, an insulator is embedded in the groove, and a part of the insulator adjacent to the semiconductor region exposed at the top of the substrate is partially removed. Remove to the second depth. Next, a semiconductor is epitaxially grown on the surface of the substrate and only the semiconductor is selectively polished by using an insulator as a stopper to form a thin film semiconductor region connected to the semiconductor substrate. Then, a MOSFET is formed on the semiconductor region exposed on the surface of the substrate.

In the second manufacturing method, a gas (for example, oxygen) in which a compound with a semiconductor serves as an insulator is ion-implanted into the substrate from above a shielding mask provided on the surface of a semiconductor substrate, and after removing the shielding mask. Perform high temperature heat treatment. Next, if necessary, the surface of the substrate is thinned and, for example, LOCO
The element isolation region is formed by the S method. Then, a MOSFET is formed on the semiconductor region exposed on the surface of the substrate.

In the third manufacturing method, an element isolation region is formed on the semiconductor substrate by, for example, the LOCOS method, and a gate electrode of the MOSFET is formed. Next, a gas (for example, oxygen) in which a compound with a semiconductor serves as an insulator is ion-implanted into the inside of the substrate using the element isolation region and the gate electrode as a shielding mask, and then a high temperature heat treatment is performed. Then, a MOSFET is formed on the semiconductor region exposed on the surface of the substrate.

[0015]

Embodiments of the present invention will now be described in detail with reference to the drawings. FIG. 1 is a sectional view showing an embodiment of the present invention. Note that the semiconductor device using the n-channel MOSFET and the semiconductor device using the p-channel MOSFET have the same structure, operation, action, and the like, and therefore a semiconductor device having a CMOS structure can be easily analogized. Unless otherwise noted, a semiconductor device using an n-channel MOSFET will be described as an example. Further, in FIG. 1, three types of structures (A), (B),
(C) is shown.

First, in FIG. 1A, a drain region 12 formed of an n-type diffusion layer is formed on the surface side of a p-type semiconductor substrate 11.
And the source region 13 are formed, and the gate electrode 16 is disposed above the channel region 14 between the regions 12 and 13 with the gate insulating film 15 interposed therebetween. For example, by the element isolation regions 17 and 18 having a trench structure. Element isolation is achieved. Of the drain, source, and channel regions, the lower portions of the drain region 12 and the source region 13 are electrically insulated from the inside of the substrate by the insulating layers 19 and 20, and the lower portion of the channel region 14 is connected to the inside of the substrate. It has a structured structure. The insulating layers 19 and 20 are integrally formed with the element isolation regions 17 and 18 by an insulator such as SiO ₂ .

In FIG. 1B, of the drain, source, and channel regions, only the lower portion of the drain region 12 is electrically insulated from the inside of the substrate by the insulating layer 19, and the source region 13 and the channel region 14 are electrically insulated. The lower part has a structure connected to the inside of the substrate. Also, FIG.
In (C), of the drain, source, and channel regions, the drain region 12 and the channel region 1 are shown.
The lower part of 4 is electrically insulated from the inside of the substrate by the insulating layer 19 ', and only the lower part of the source region 13 is connected to the inside of the substrate.

As described above, the lower part of each of the source, drain and channel regions except for one region is electrically insulated from the semiconductor substrate 11 by the insulating layers 19 (19 ') and 20. N channel M
In the OSFETs (A), (B), and (C), no junction capacitance is formed between the insulated diffusion layer (drain region 12, source region 13) and the semiconductor substrate 11. Therefore, for example, as shown in FIG.
p-channel MOSF connected in series between d and ground
C composed of ETQ1 and n-channel MOSFET Q2
In a MOS inverter circuit, an n-channel MOSF
The n-channel MOSF of FIG. 1 (B) or (C) as ET
We will use ET.

As a result, the n-channel MOSFET Q2
Since there is no junction capacitance Cjd between the drain (D) and the ground of the device, higher speed and lower power consumption of the circuit can be realized as compared with the circuit using only the n-channel MOSFET of the conventional structure. Structure n-channel MOSF
Comparable with ET. On the other hand, since a junction capacitance is formed between the semiconductor substrate 11 and the source region 13 connected thereto, in the CMOS inverter circuit, the junction capacitance Cjs is provided between the source (S) of the n-channel MOSFET Q2 and the ground. However, since the junction capacitance Cjs has the function of absorbing noise in the power supply line, malfunction of the circuit due to noise can be prevented.

In a circuit having a structure in which n-channel MOSFETs Q3 and Q4 are connected in series, such as the NAND circuit shown in FIG. 2B, one n-channel MO is provided.
Since the source (S) of the SFET Q3 corresponds to the connection midpoint X, it is preferable that the junction capacitance Cjs is not interposed between the source (S) of the n-channel MOSFET Q3 and the ground (substrate). Therefore, as the n-channel MOSFET Q3 whose source (S) corresponds to the connection middle point X,
By using the n-channel MOSFET of (A) and further using the n-channel MOSFET of FIG. 1 (B) or (C) as the ground-side n-channel MOSFET,
Since it is possible to prevent the parasitic capacitances Cjs and Cjd from intervening between the connection midpoint X and the ground, it is possible to realize high-speed circuit operation and low power consumption.

Further, of the source, drain, and channel regions, at least the lower part of the drain region 12 is electrically insulated from the inside of the substrate by the insulating layer 19, and the n-channel MOSFETs (A), (B), (C) are provided. ), Excessive minority carriers (electrons in the n-channel MOSFET) generated inside the semiconductor substrate 11 are collected in the drain region 12 even when charged particles such as α-rays are incident on the drain region 12. There is no. Therefore, the same excellent soft error resistance as that of the n-channel MOSFET having the SOI structure can be obtained.

The n-channel MOSF according to this embodiment is also provided.
According to ET (A), (B), and (C), since at least one region is always connected to the semiconductor substrate 11, the problem about the current drive characteristic in the SOI structure can be solved. Become. Here, as described above, the problem with respect to the current driving characteristic is that in the n-channel MOSFET having the SOI structure, the drain, source and channel regions are electrically insulated from the semiconductor substrate by the insulating layer and are thermally Since the conductivity of the insulating layer is inferior to that of the semiconductor, the heat dissipation efficiency is poor, and the majority carriers (holes in the n-channel MOSFET) generated in the channel region are not discharged as a substrate current through the semiconductor substrate. Carriers accumulate in the channel region and MOSF
The ET current driving characteristic has a kink characteristic, and the Joule heat generated by the drain current flowing is difficult to be radiated, and the current driving ability is lowered, that is, the circuit performance is lowered due to the temperature increase.

Next, the first manufacturing method according to the present invention for manufacturing the semiconductor device having the MOSFET having the structure shown in FIGS. 1A, 1B and 1C will be described with reference to the process chart of FIG. explain. Also in this example, as in the case of FIG. 1, the case of an n-channel MOSFET will be described as an example, but a p-channel MOSFET can be similarly formed by reversing the n-type and p-type ion species. Moreover, an n-channel MOSFET and a p-channel MOSFET using a resist can be separately formed to easily form a CMOS structure.

First, in step (a), a groove 32 having a first depth d1 is formed in a semiconductor substrate (p-type silicon substrate or p-well) 31, and an insulator 33 such as SiO ₂ is formed in this groove 32.
Embed Next, in the step (b), a part of the insulator 33 adjacent to the semiconductor region 34 exposed at the uppermost part of the substrate is etched by using a resist as a mask, thereby forming a junction depth of the diffusion layer formed on the semiconductor surface. A second that is equal to or less than the first depth and is shallower than the first depth d1.
To form a region 35 by removing it to a depth d2.

Then, in the step (c), a second film is formed on the surface of the substrate.
The semiconductor 36 is epitaxially grown with a thickness equal to or greater than the depth d2. Next, in step (d), only the semiconductor 36 is selectively polished by using the insulator 33 as a stopper to form the thin film semiconductor region 37 connected to the semiconductor substrate 31. Next, in step (e), a gate oxide film 38 is formed on the semiconductor region 37 exposed on the substrate surface, a gate electrode 39 is further formed, and then an n ⁺ -type impurity is ion-implanted to form a drain. Region 40 and Source Region 41
To form. Through the above steps, as shown in FIG.
A semiconductor device in which the respective n-channel MOSFETs (A), (B) and (C) are selectively formed can be obtained.

The n-channel MOSFETs having the structures shown in FIGS. 1A, 1B, and 1C do not have to be manufactured by separate steps, and the groove 32 and the region 35 (thin film semiconductor region 37) are not required. ) And n-channel MOSF
By appropriately changing the relative positional relationship among the ET gate electrode 39 (channel region), the drain region 40, and the source region 41, they can be formed simultaneously in the same step.

Next, the second and third manufacturing methods according to the present invention will be described. In the following example, a case of manufacturing a MOSFET having a structure of FIG. 1A, that is, a structure in which the lower portions of the drain and source regions are electrically insulated from the inside of the semiconductor substrate will be described. Further, as the element isolation structure, the trench structure is adopted in the case of FIG. 1, but in the case of this example, the LOCOS structure will be described as an example.
Furthermore, in the following example, an n-channel MOSFET will be described as an example, but a p-channel MOSFET can be similarly formed by reversing the n-type and p-type ion species, and an n-channel using a resist is used. MOSFET
And p-channel MOSFET are made separately to facilitate CMO
It can be an S configuration.

First, the second manufacturing method will be described with reference to the process chart of FIG. 4. In step (a), only the region 43 which is not electrically insulated from the inside of the MOSFET substrate is formed on the surface of the silicon substrate 42. Resist 44 to remain
Pattern formation is performed, and the oxygen ions O ⁺ are used as a mask, for example, an acceleration voltage of 180 keV and a dose of 2E18
/ Cm ² (substrate temperature 650 ° C). continue,
In the step (b), after removing the resist, for example, 1300
By performing high temperature annealing at 6 ° C. for 6 hours, the SiO ₂ film (insulating layer) 45 is formed only in the region where oxygen is implanted.

Next, in step (c), the silicon substrate 4
The surface of 2 is oxidized and the resulting oxide film is etched to thin the silicon film 46 (for example, 80 nm), and the element isolation region 47 is formed by the LOCOS method.
Further, boron B ⁺ is ion-implanted to form the p-well 48. Subsequently, in step (d), after forming the gate oxide film 49, patterning of the gate electrode 50 is performed, and arsenic As ⁺ is ion-implanted into the MOSFET region using the gate electrode 50 as a shielding mask to drain the drain. A (diffusion layer) region 51 and a source (diffusion layer) region 52 are formed. At this time, a resist 53 is separately formed and masked above the region where the diffusion layer 54 for electrode extraction of the p well (see step (e)) is formed.

Next, in step (e), a diffusion layer 54 for taking out the electrode of the p well 48 is formed by ion implantation of boron B ⁺ . At this time, a resist 55 is separately formed and masked above the gate electrode 50, the drain region 51, and the source region 52. After that, as usual,
After steps such as formation of an interlayer insulating film, contacts and Al wiring, and activation annealing of impurities in wells and diffusion layers,
The element isolation structure corresponding to the structure of FIG. 1A is LOCOS.
A semiconductor device using an n-channel MOSFET having a structure can be obtained.

According to the second manufacturing method described above, the SiO ₂ film (insulating layer) 45 is formed by implanting oxygen ions using the resist 44 as a mask and performing high temperature annealing. A region that is electrically insulated from the inside of the substrate and a region that is not insulated can be easily determined by arbitrarily changing the pattern of the resist 44.

Next, a third manufacturing method according to the present invention will be described with reference to the process chart of FIG. First, in the step (a), the element isolation region 5 is formed on the silicon substrate 56.
7, a p-well 58, a gate oxide film 59 and a polysilicon gate electrode 61 with an offset oxide film 60 are formed. Next, in the step (b), oxygen ion O ⁺ implantation is performed, for example, with an acceleration voltage of 25 keV and a dose amount of 2E17 / cm ² using the gate electrode 61 with the element isolation region 57 and the offset oxide film 60 as a shielding mask. The temperature is 650 ° C). At this time, a resist 62 is separately formed and masked above the region where the diffusion layer 66 for electrode extraction of the p well (see step (e)) is formed.

Next, in the step (c), after removing the resist 62, high temperature annealing is performed, for example, at 1300 ° C. for 6 hours, so that only the oxygen-implanted region is exposed to SiO 2.
_Two films (insulating layer) 63 are formed. As a result, a partial SOI having a thin thickness of, for example, about 40 nm is formed.
Next, in step (d), arsenic As ⁺ is ion-implanted into the region of the n-channel MOSFET using the gate electrode 61 with the offset oxide film 60 as a shielding mask to form a drain (diffusion layer) region 64 and a source ( A diffusion layer area 65 is formed. At this time, a resist 66 is separately formed and masked above the region of the p well where the diffusion layer 67 for electrode extraction is formed.

Next, in step (e), a diffusion layer 67 for taking out the electrode of the p well 48 is formed by ion implantation of boron B ⁺ . At this time, a resist 68 is separately formed and masked above the gate electrode 60, the drain region 64, and the source region 65. After that, as usual,
After steps such as formation of an interlayer insulating film, contacts and Al wiring, and activation annealing of impurities in wells and diffusion layers,
The element isolation structure corresponding to the structure of FIG. 1A is LOCOS.
A semiconductor device using an n-channel MOSFET having a structure can be obtained.

According to the third manufacturing method described above, the SiO ₂ film (insulating layer) 63 is formed by implanting oxygen ions O ⁺ using the gate electrode 60 as a mask and performing high temperature annealing.
Since the region which is electrically insulated from the inside of the substrate of the MOSFET and the region which is not insulated are determined by the gate electrode 60 in a self-aligned manner by forming
It is possible to suppress variations in characteristics.

In the second and third manufacturing methods, the case where oxygen O is used as the gas for injecting into the semiconductor to form the insulating layer has been described, but the present invention is not limited to this, and nitrogen N or the like is used. Any gas can be used as long as the compound with the semiconductor serves as an insulator.

Further, in each of the above-described embodiments, the case where the drain region, the source region and the channel region of the MOSFET are electrically insulated from the inside of the substrate by the insulating layer or connected to the inside of the substrate has been described. However, the present invention is not limited to this, and the lower part of at least a part of the region from the drain region to the source region of the MOSFET is connected to the inside of the substrate, and the lower part of the other region is separated from the inside of the substrate by the insulating layer. If the structure is electrically insulated, the intended purpose can be achieved.

[0038]

As described above, according to the present invention,
Between the diffusion region and the substrate, the lower part of the region excluding at least part of the region extending from the drain region to the source region of the MOSFET is electrically insulated from the semiconductor substrate by the insulating layer. No junction capacitance is formed, and even when charged particles such as α-rays are incident on the diffusion region, excess minority carriers generated inside the substrate are not collected in the diffusion region. It is possible to achieve excellent soft error resistance, high speed, and low power consumption.

Further, since the lower part of at least a part of the region extending from the drain region to the source region of the MOSFET is connected to the inside of the substrate, thermal efficiency is not impaired, so that the MOSFET having the SOI structure can be obtained. Regarding the problem of the kink characteristics of the existing current characteristics and the deterioration of the current driving ability due to the temperature rise, that is, the deterioration of the circuit performance, the bulk MO
It can be reduced to the same extent as the SFET.

[Brief description of drawings]

FIG. 1 is a sectional view showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit example to which the present invention is applied.

FIG. 3 is a process drawing of the first manufacturing method according to the present invention.

FIG. 4 is a process drawing of a second manufacturing method according to the present invention.

FIG. 5 is a process drawing of the third manufacturing method according to the present invention.

FIG. 6 is a sectional view showing a sectional structure of a bulk MOSFET.

FIG. 7 is a sectional view showing a sectional structure of a MOSFET having an SOI structure.

[Explanation of symbols]

 11 semiconductor substrate 12 drain region 13 source region 14 channel region 16 gate electrode 17, 18 element isolation region 19, 19 ', 20 insulating layer

Claims (4)

[Claims] 1. A semiconductor device having a MOS field effect transistor, wherein a lower part of the region except for at least a part of a region extending from a drain region to a source region of the MOS field effect transistor is a semiconductor substrate. A semiconductor device comprising an insulating layer that electrically insulates. 2. Forming a groove having a first depth in a semiconductor substrate,
The step of embedding an insulator therein, and the part of the insulator adjacent to the semiconductor region exposed at the top of the substrate are equal to or less than the junction depth of the diffusion layer formed on the semiconductor surface. Second shallower than depth
To a semiconductor substrate, a step of epitaxially growing a semiconductor on the surface of the substrate to a thickness not less than the second depth, and a step of selectively polishing only the semiconductor using the insulator as a stopper to form a semiconductor substrate. A method of manufacturing a semiconductor device, comprising: a step of forming a connected thin film semiconductor region; and a step of forming a MOS field effect transistor on a semiconductor region exposed on a surface of a substrate. 3. A step of ion-implanting a gas, in which a compound with a semiconductor serves as an insulator, into a substrate from above a shielding mask provided on the surface of a semiconductor substrate, and a step of performing a high temperature heat treatment after removing the shielding mask. A method of manufacturing a semiconductor device, comprising: a step of forming an element isolation region; and a step of forming a MOS field effect transistor on a semiconductor region exposed on a surface of a substrate. 4. A step of forming an element isolation region on a semiconductor substrate and forming a gate electrode of a MOS field effect transistor, and a gas in which a compound with a semiconductor serves as an insulator is formed in the element isolation region and the gate electrode. A semiconductor device characterized by using a step of implanting ions into the substrate as a shielding mask, a step of performing high temperature heat treatment, and a step of forming a MOS field effect transistor on a semiconductor region exposed on the surface of the substrate. Production method.