JPH07283302A - Manufacture of semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of manufacturing processes by the process performed for forming a second groove which separates elements from each other by forming the second groove together with a first groove for alignment target in the same process by utilizing the process for forming the first groove. CONSTITUTION:A first groove 2S for alignment target is formed in a first area on the main surface of the substrate l and a second groove 2W for separating elements from each other having a narrower width is formed between a second area 11 and third area 12 adjacent to the area 11 on the main surface of the substrate 1. Then an oxide film 3 is formed on the entire main surface of the substrate 1 by thermal oxidation so that at least the groove 2W can be filled with the film 3. In addition, a well area 4 having a conductivity opposite to that of the substrate 1 is formed in the second area 11 and another well area 5 having the same conductivity as that of the substrate 1 is formed in the third area 12 on the main surface of the substrate l. Therefore, the number of manufacturing processes can be reduced by the process for forming the groove 2W between the well area.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a technique effective when applied to an element isolation technique of the semiconductor integrated circuit device.

[0002]

2. Description of the Related Art A semiconductor element or a circuit in which the semiconductor element is integrated is miniaturized and highly integrated for the purpose of improving element characteristics and circuit characteristics. On a semiconductor substrate (semiconductor wafer during manufacturing, semiconductor chip after scribing), a plurality of elements (active elements) are electrically isolated from each other by an element isolation technique. An important requirement of the element isolation technique is to minimize the area required for the isolation and effectively secure the arrangement area of the elements on the main surface of the semiconductor substrate.

By the way, a semiconductor integrated circuit device equipped with a CMOS (complementary MOSFET), which is optimal for low power consumption and high operating speed, has an n-type well region as shown in FIG. 4 and the p-type well region 5 are separated from each other by interposing a boundary between them. Specifically, the n ⁺ type semiconductor region (n
Source region or drain region of channel MOSFET)
11 and a p ⁺ type semiconductor region (source region or drain region of p-channel MOSFET) 12 formed on the main surface of the n-type well region 4 have a field insulating film (thermal oxide film) interposed therebetween, and are electrically isolated. To be done. In FIG. 8, reference numeral 1
Is a p-type semiconductor substrate (single crystal silicon substrate), and reference numeral 8 is a p-type channel stopper region formed in a region that is easily inverted.

However, in this type of element isolation structure, carrier densities of different conductivity types cancel each other out in the vicinity of the boundaries between the p-type well region 5 and the n-type well region 4, and the carrier density becomes low (well The impurity concentration of the region becomes low). That is, the dielectric isolation breakdown voltage between the n ⁺ type semiconductor region 11 of the p type well region 5 and the p ⁺ type semiconductor region 12 of the n type well region 4 cannot be sufficiently secured. In order to ensure a sufficient dielectric isolation breakdown voltage, a plurality of adjacent n ⁺ -type semiconductor regions 11 in the p-type well region 5 or a plurality of adjacent p ⁺ -type semiconductor regions 12 in the n-type well region 4 are separated by a reference distance. In terms of dimensions, a distance that is several times the standard separation dimension is required.

Further, when the distance between the n ⁺ type semiconductor region 11 of the p type well region 5 and the p ⁺ type semiconductor region 12 of the n type well region 4 is not sufficiently secured, a lateral parasitic bipolar transistor is formed. , The ground width of the emitter becomes small and the grounded emitter current amplification factor h _PE increases, so that the latch-up resistance deteriorates.

[0006]

As a technique capable of solving the above problems, an element isolation groove is formed at the boundary between the p-type well region 5 and the n-type well region 4 on the main surface of the semiconductor substrate 1. , Element isolation technology is known. The element isolation groove is formed by etching in the depth direction from the main surface of the semiconductor substrate 1, and the element isolation groove is filled with an insulator. The element isolation technique for forming the element isolation trench is a conventional selective oxidation technique for the main surface of the semiconductor substrate 1, so-called L.
Compared with the OCOS technique, the distance required for insulation separation can be secured in the depth direction of the semiconductor substrate 1, so that the insulation separation breakdown voltage can be improved without impairing the degree of integration.

However, in the element isolation technique for forming the element isolation groove described above, the steps of forming the element isolation groove and the step of burying an insulator in the element isolation groove are simply increased, and the manufacturing of the semiconductor integrated circuit device is increased. The number of steps increases.

Further, the element isolation technique for forming the above-mentioned element isolation groove is technically difficult. For example, a technique of forming an element isolation groove on the main surface of the semiconductor substrate 1 and then introducing an impurity (channel stopper region) into the sidewall of the element isolation groove, or an element isolation groove having a different width is uniformly filled with an insulator. Each technique involves difficulties. Further, the chamfering technique (rounding technique) performed on the opening corners or bottom corners of the element isolation trench for the purpose of alleviating stress concentration or electrolytic concentration is similarly difficult.

The present invention has been made to solve the above problems, and an element isolation groove is provided between each of the semiconductor substrate and the well regions or between each of the plurality of well regions. It is an object of the present invention to provide a technique capable of reducing the number of manufacturing steps in a method of manufacturing a semiconductor integrated circuit device to be formed.

[0010]

In order to solve the above problems, the present invention is characterized in that a method for manufacturing a semiconductor integrated circuit device includes the following steps (1) to (3).

(1) The first main surface of the first conductivity type semiconductor substrate
In the region, a first groove for an alignment target is formed in a depth direction from the main surface of the semiconductor substrate, and a second region different from the first region in the main surface of the semiconductor substrate is formed. Forming a second trench for element isolation having a groove width smaller than that of the first groove at a boundary portion between the respective third regions adjacent to the region; and (2) applying heat to the entire main surface of the semiconductor substrate. A step of forming a thermal oxide film by an oxidization process and burying the thermal oxide film in at least the inside of the second groove, (3) in the second region of the main surface of the semiconductor substrate, which has a conductivity type opposite to that of the semiconductor substrate. Forming a second conductivity type first semiconductor region, or forming this first semiconductor region, and
Forming a first conductivity type second semiconductor region of the same conductivity type as the semiconductor substrate in the third region of the main surface of the semiconductor substrate.

Further, in the present invention, the step of forming the first groove for the alignment target is a step of forming the first groove in the scribe region of the semiconductor substrate, wherein the second semiconductor region or the second semiconductor region is formed. And the step of forming the third semiconductor region is a step of forming a well region in the integrated circuit formation region of the semiconductor substrate, and the step of forming the second trench for element isolation is performed on each of the semiconductor substrate and the well region. The step of forming a groove for electrically isolating each element formed in the above step or each element formed in each of the plurality of well regions.

Further, according to the present invention, the thermal oxidation treatment includes a treatment for removing a damaged layer on the main surface of the semiconductor substrate, which accompanies the formation of the first groove for alignment target and the second groove for element isolation. Is characterized by.

[0014]

According to the present invention, in the method of manufacturing a semiconductor integrated circuit device, the step of forming the first groove for the alignment target, which is used in the mask alignment in the photolithography technique, is used. Since the second isolation trench is formed, the number of manufacturing steps can be reduced by the amount corresponding to the step of forming the element isolation second groove. In the method for manufacturing a semiconductor integrated circuit device according to the present invention, a thermal oxidation treatment for removing a damaged layer on a main surface of a semiconductor substrate, which accompanies the formation of the alignment target first groove and the element isolation second groove, is performed. Since the thermal oxide film was buried inside the second trench for element isolation in the same process as this process,
The number of manufacturing steps can be reduced by the amount corresponding to the step of burying the thermal oxide film inside the second trench for element isolation.

[0015]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will be described below with reference to the drawings.

A method of manufacturing a semiconductor integrated circuit device according to an embodiment of the present invention is shown in FIGS. 1 to 7 (cross-sectional views of the essential part shown in each manufacturing step).

First, a p-type (or n-type) made of single crystal silicon is used.
A type) semiconductor substrate (semiconductor wafer) 1 is prepared.

Next, as shown in FIG. 1, an alignment target groove 2S is formed in the scribe region (left side in FIG. 1) on the main surface of the semiconductor substrate 1. Then, in the same step as the step of forming the alignment target groove 2S, the element isolation groove 2W is formed in a region (center on the right side in FIG. 1) corresponding to the boundary between the well regions of the integrated circuit formation region.

The alignment target groove 2S is
In the photolithography technology, it is used as a mark for aligning a manufacturing mask. The alignment target groove 2S is formed in the scribe region that does not affect the formation of elements in the integrated circuit formation region. Therefore, since the scribe region is excluded after the scribe (dicing) step, the alignment target groove 2S does not exist in principle.

The element isolation trench 2W insulates and isolates an element formed in a p-type well region and an element formed in an n-type well region, which will be formed in a later step, from the insulating isolation capability. Used to enhance. Element isolation groove 2W
Is basically formed in the same step as the step of forming the alignment target groove 2S, so that it can be formed without increasing the number of manufacturing steps.

The alignment target groove 2S and the element isolation groove 2W are formed by anisotropic etching using an etching mask formed by a photolithography technique. The alignment target groove 2S is formed with a groove width of 2.0 μm and formed with a depth of 0.5 μm from the main surface of the semiconductor substrate 1 to facilitate alignment, for example. The element isolation trench 2W is formed with a groove width of 0.5 μm, for example, in order to reduce the element isolation area.
It is formed to a depth of 0.5 μm from the main surface of.

Next, in order to remove the damage layer of the surface layer generated by the anisotropic etching, a thermal oxidation treatment process is applied to the entire main surface of the semiconductor substrate 1 to oxidize it as shown in FIG. A silicon film 3 is formed. This silicon oxide film 3 is
For example, it is formed with a film thickness of 500 nm. The silicon oxide film 3 having this thickness almost fills the inside of the element isolation trench 2W, and the surface on the element isolation trench 2W is formed flat. In addition, the silicon oxide film 3 has a flat surface on the alignment target groove 2S without being filled in the alignment target groove 2S.

Next, isotropic etching is performed on the entire surface of the silicon oxide film 3 to perform a so-called etch back process,
The over-etching amount is added, and etching is performed by the film thickness of the silicon oxide film 3 to form a layer (see FIG. 3).
By this etch back process, the element isolation trench 2W is formed.
The silicon oxide film 3 can be selectively left inside. On the other main surface of the semiconductor substrate 1, each silicon oxide film 3 inside the alignment target groove 2S is removed. The etching is performed using HF, for example. Further, in order to make the surface of the silicon oxide film 3 buried inside the element isolation trench 2W flat, the amount of overetching is reduced.

Since the silicon oxide film 3 buried in the element isolation trench 2W is formed in the same step as the step of forming the silicon oxide film 3 for removing the damaged layer, the number of manufacturing steps should be increased. Instead, the silicon oxide film 3 is embedded in the element isolation trench 2W.

Next, the entire main surface of the semiconductor substrate 1 is subjected to a thermal oxidation treatment, and as shown in FIG. 3, a silicon oxide film is formed on the main surface of the semiconductor substrate 1 although no reference numeral is given. This silicon oxide film is formed with a film thickness of, for example, 50 nm for the purpose of mitigating damage at the time of ion implantation and preventing heavy metal contamination.

Next, as shown in FIG. 4, in the main surface of the semiconductor substrate 1, an n-type impurity (for example, P +) 4N is selectively introduced into the formation region of the n-type well region, and the p-type well region is formed. P-type impurity (eg B +) 5P in the formation region of
To introduce. When introducing each of the n-type impurity 4N and the p-type impurity 5P, an introduction mask formed by a photolithography technique is used. The n-type impurity 4N is, for example, 1 at a dose amount of 1.5 × 10 ¹³ atoms / cm ^2.
It is introduced with an energy of 30 KeV. p-type impurity 5P
Is introduced with an energy of 40 KeV at a dose of 1.2 × 10 ¹³ atoms / cm ² , for example. In this embodiment, the scribe region is basically not doped with impurities for forming the well region.

Next, the semiconductor substrate 1 is subjected to thermal diffusion treatment,
The n-type impurity 4N is stretched and diffused to form the n-type well region 4, and the p-type impurity 5P is stretched and diffused to form the p-type well region 5. The thermal diffusion process is
For example, it is performed at 1100 ° C. for about 20 hours. When each of the n-type well region 4 and the p-type well region 5 is formed, a so-called twin well structure is formed (see FIG. 5).

Next, the silicon oxide film remaining on the main surface of the semiconductor substrate 1 is removed, and a silicon oxide film 19 is newly formed by thermal oxidation treatment. The silicon oxide film 19 is, for example, 20
It is formed with a film thickness of nm.

Next, a silicon nitride film 20 is formed on the entire surface of the silicon oxide film 19, and the silicon nitride film 20 is removed except for the silicon nitride film 20 in the element formation region and the silicon nitride film 20 in the scribe region. To remove. The silicon nitride film 20 is deposited by, for example, a CVD method and is formed to have a film thickness of 15 nm. This silicon nitride film 20 is patterned by anisotropic etching using an etching mask formed by a photolithography technique. The remaining silicon nitride film 20 is used as an oxidation resistant mask (see FIG. 5).

Since the surface of the semiconductor substrate 1 is oxidized and eroded when the silicon oxide film 3 is embedded therein, the element isolation trench 2W is formed to have a trench width of about 1 μm. Also,
Particularly in the p-type well region, an inversion layer (leakage path) is likely to occur along the field insulating film to be formed later,
The formation of the channel stopper region is essential. Therefore, the silicon nitride film 20 as an oxidation-resistant mask has a size of, for example, 0.5 μm (the size on one side from the end of the silicon nitride film 20 to the opening end of the isolation trench 2W is 0 for forming the channel stopper region). 0.5 .mu.m), the silicon nitride film 20 is set to about 2.0 .mu.m at the boundary of the well region.

Next, as shown in FIG. 5, a p-type impurity (for example, B +) 8P is introduced into the formation region of the channel stopper region in the main surface of the p-type well region 5. The p-type impurity 8P is introduced using the silicon nitride film 20 and the introduction mask 21 formed by the photolithography technique shown by the broken line in FIG. The p-type impurity 8P is, for example, 3.0 × 1
It is introduced with an energy of 30 KeV at a dose of 0 ¹³ atoms / cm ² .

Next, after removing the introduction mask 21,
Using the silicon nitride film 20 as an oxidation resistant mask, a thermal oxidation process is performed to form a field insulating film (silicon oxide film) 6. This field insulating film 6 is, for example, 500 nm
It is formed with a film thickness of. Further, since this thermal oxidation treatment is accompanied by heat at the same time, the p-type impurity 8P is stretched and diffused to form the p-type channel stopper region 8 (see FIG. 6).

The element isolation structure is completed by forming the p-type channel stopper region 8. At the boundary between the n-type well region 4 and the p-type well region 5, the isolation trench 2W, the silicon oxide film 3 embedded therein, the field insulating film 6, and the p-type channel stopper region are formed. The element isolation structure formed by 8 is constituted. The silicon oxide film 3 and the field insulating film 6 form a well isolation insulating film 7. An element isolation structure formed of a field insulating film 6 is formed between the plurality of elements formed in the n-type well region 4. An element isolation structure formed by the field insulating film 6 and the p-type channel stopper region 8 is formed between the plurality of elements formed in the p-type well region 5.

Then, as shown in FIG. 6, the silicon nitride film 20 used as the oxidation resistant mask is removed.

Next, in accordance with normal CMOS programming, as shown in FIG. 7, n-channel MOSFETs Qn, p
Channel MOSFET Qp, interlayer insulating film 13, connection hole 1
4. Each of the wirings (for example, Al—Cu alloy) 15 is sequentially formed.

The n-channel MOSFET Qn is formed by sequentially forming a gate insulating film 9, a gate electrode 10, a low-concentration n-type semiconductor region, a sidewall spacer, and a high-concentration n-type semiconductor region 11. The p-channel MOSFET Qp is formed by sequentially forming the gate insulating film 9, the gate electrode 10, the low-concentration p-type semiconductor region, the sidewall spacers, and the high-concentration p-type semiconductor region 12. In this embodiment, n-channel MOSFET Qn, constituted either husband p-channel MOSFETQp people in LDD (L ightly D oped D rain ) structure.

When the wiring 15 is formed (actually, the final protective film is formed), the semiconductor substrate 1 is scribed in the scribe area to be formed as a semiconductor chip.

The present invention is not limited to the above-mentioned embodiment, but various modifications can be made without departing from the scope of the invention.

For example, the present invention can be applied to a semiconductor integrated circuit device having a single well structure. That is, according to the present invention, the element isolation groove is formed at the boundary between the well region in which the element is formed and the semiconductor substrate in which the element is formed.

The present invention is not limited to CMOS,
n-channel or p-channel MOSFET or C
It can be applied to a semiconductor integrated circuit device having a MOS and a bipolar transistor.

[0041]

As described above, the present invention utilizes the step of forming the first groove for the alignment target, which is used in the mask alignment in the photolithography technique, in the method of manufacturing a semiconductor integrated circuit device, Since the element isolation second groove is formed in the same step as this step, the number of manufacturing steps can be reduced by an amount corresponding to the step of forming the element isolation second groove.

Further, according to the present invention, in the method of manufacturing a semiconductor integrated circuit device, a thermal oxidation treatment for removing a damaged layer on the main surface of the semiconductor substrate accompanying the formation of the first groove for alignment target and the second groove for element isolation. Since the thermal oxide film is embedded inside the element isolation second groove in the same step as this step, the amount corresponding to the step of filling the thermal oxide film inside the element isolation second groove, The number of manufacturing steps can be reduced.

[Brief description of drawings]

FIG. 1 is a fragmentary cross-sectional view in a first step showing a method for manufacturing a semiconductor integrated circuit device which is an embodiment of the present invention.

FIG. 2 is a cross-sectional view of a main part in a second step.

FIG. 3 is a cross-sectional view of main parts in a third step.

FIG. 4 is a cross-sectional view of main parts in a fourth step.

FIG. 5 is a main-portion cross-sectional view in a fifth step.

FIG. 6 is a sectional view of a key part in a sixth step.

FIG. 7 is a sectional view of a key part in a seventh step.

FIG. 8 is a cross-sectional view of essential parts of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

 1 Semiconductor Substrate 2S, 2W Groove 3,19 Silicon Oxide Film 4,5 Well Region 6 Field Insulating Film 7 Interwell Isolation Film 8 Channel Stopper Region 9 Gate Insulating Film 10 Gate Electrode 11, 12 Semiconductor Region 20 Silicon Nitride Film Q MOSFET

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 27/08 331 BA

Claims (3)

[Claims] 1. A method of manufacturing a semiconductor integrated circuit device, comprising the following steps (1) to (3). (1) In the first region of the main surface of the first conductivity type semiconductor substrate, a first groove for an alignment target formed in the depth direction from the main surface of the semiconductor substrate is formed, and the main surface of the semiconductor substrate is formed. At the boundary between the second region different from the first region and the third region adjacent to the second region, an element isolation second groove having a groove width smaller than that of the first groove is formed. The process of doing. (2) A step of forming a thermal oxide film on the entire main surface of the semiconductor substrate by a thermal oxidation process and burying the thermal oxide film at least inside the second groove. (3) A second conductivity type first semiconductor region having a conductivity type opposite to that of the semiconductor substrate is formed in the second region of the main surface of the semiconductor substrate, or the first semiconductor region is formed and the semiconductor substrate of the semiconductor substrate is formed. A step of forming a first conductivity type second semiconductor region having the same conductivity type as the semiconductor substrate in the third region of the main surface. 2. The step of forming a first groove for an alignment target according to claim 1 is a step of forming a first groove in a scribe region of the semiconductor substrate, wherein the second semiconductor region, or The step of forming the second semiconductor region and the third semiconductor region is a step of forming a well region in the integrated circuit formation region of the semiconductor substrate, and the step of forming the second trench for element isolation is the semiconductor substrate, A semiconductor integrated circuit device, which is a step of forming a groove for electrically separating each element formed in each well region or each element formed in each of the plurality of well regions. Manufacturing method. 3. The thermal oxidation treatment according to claim 1 or 2 is the first for the alignment target.
A method of manufacturing a semiconductor integrated circuit device, comprising: a process of removing a damaged layer on a main surface of a semiconductor substrate, which is accompanied by formation of a groove and a second groove for element isolation.