JPH06151740A - Power semiconductor device - Google Patents

Abstract

PURPOSE:To provide a power semiconductor device wherein transistors are surely restrained front interfering mutually with each other when V-DMOS power transistors are formed on the same semiconductor chip. CONSTITUTION:A semiconductor substrate 11 is composed of a first N<+> substrate 12 and a second N<-> substrate 13, first and second V-DMOS transistors, 100 and 200, are formed on the primary surface of the second substrate 13, two trench isolating oxide films 151 and 152 are provided along a boundary line between the transistors 100 and 200, and a P diffusion layer 16 is provided between the oxide films 151 and 152. At this point, the trench oxide films 151 and 152 are formed so deep as to reach the first substrate 12, the P diffusion layer 16 is connected to a grounding potential, and currents flowing out of the sources of the V-DMOS transistors when a parasitic PNP transistor is kept in an ON-state are absorbed in the P diffusion layer 16.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power semiconductor device having an intelligent power device or a multi-channel power device, etc., in which a plurality of power transistors are formed on the same semiconductor chip.

[0002]

2. Description of the Related Art A semiconductor in which a plurality of power transistors are arranged and formed on the same semiconductor chip and a control circuit is formed on the same semiconductor chip, and the control circuit controls each of the plurality of power transistors. The construction of devices tends to be widespread.
The power transistor configured by such a semiconductor device is used for power control such as motor control and relays or inverters.

In order to protect the control region formed in an SOI (Silicon On Insulator) substrate from the potential fluctuation of the power transistor, for example, Japanese Unexamined Patent Publication No. 2-25226.
As disclosed in Japanese Patent Laid-Open No. 2-129765 and Japanese Patent Laid-Open No. 3-129765, a structure for forming a shield layer has been proposed.

However, a plurality of V-Ds have come to use the substrate as a drain as a power transistor.
When the MOS or the IGBT is formed on the same semiconductor chip, it is not possible to form a structure in which each power transistor is surrounded by the shield layer to suppress electrical interference.

On the same semiconductor chip, for example, V-DM
If there is more than one power transistor with OS and the substrate is configured to be used as a common drain, the source of the first V-DMOS, the drain of the substrate and the source of the second V-DMOS are There will be parasitic PNP transistors serving as terminals. Therefore, for example, when the potential of the source of the first V-DMOS rises above the potential of the common drain, this parasitic transistor is easily turned on and a current flows into the source of the second V-DMOS. As a result, the operation of the second V-DMOS is inevitably affected.

[0006]

SUMMARY OF THE INVENTION The present invention has been made in view of the above points, and is provided on the same semiconductor chip.
For example, even when a plurality of power transistors are formed by V-DMOS, it is possible to ensure stable and reliable operation of each power transistor without being influenced by the parasitic transistors. The present invention aims to provide such a power semiconductor device.

[0007]

A power semiconductor device according to the present invention comprises a high-concentration first substrate used as a common drain, and a low-concentration second substrate bonded to the first substrate. A plurality of power transistors are formed by dividing a region on the main surface of the second substrate by using the configured semiconductor substrate, and the plurality of power transistors are divided into regions to correspond to their boundaries. A diffusion layer is formed on the diffusion layer, and a trench isolation oxide film is formed corresponding to the diffusion layer to a depth reaching the first substrate. Set to the lowest potential for the transistor.

[0008]

In the power semiconductor device having the above structure, the first V-D forming one power transistor is formed.
When the source potential of the MOS rises above the potential of the common drain, a parasitic transistor is turned on between the source and the second V-DMOS, and a current tries to flow into the source of the second V-DMOS. The electric current is preceded by the first and second
Is absorbed in the diffusion layer set between the V-DMOS of the.
Therefore, in the second V-DMOS, the first V-D
Mutual electrical mutual interference can be suppressed without being affected by MOS switching and noise. That is, in the state where a plurality of power transistors are formed on the same semiconductor chip, each power transistor is controlled without mutual interference.
The power semiconductor device can have high reliability.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 shows two power transistors, the first
And second V-DMOS transistors 100 and 200
Shows an example in which the semiconductor substrate 11 is formed on the same substrate.
Is formed by bonding a second substrate 13 having a low concentration of N ⁻ onto a first substrate 12 having a high concentration of N ⁺ , and corresponding to the main surface of the second substrate 13, Two V-DMOS transistors 100 and 200 are formed with their respective regions set.

Here, the first and second V-DMOS transistors 100 and 200 are arranged in rows and columns in divided regions corresponding to the surface portion of the second substrate 13, respectively. .. and 201, 202, .. The P wells 101, 102, .. And 201, 202 ..

In each of the first and second V-DMOS transistors 100 and 200, a P well 10 is provided.
The gate electrodes 110 and 210 having a lattice shape are set so as to extend over 1, 102, ... And 201, 202, ..., respectively, and the first substrate 11 is provided with these first and second V- It will act as a common drain for DMOS transistors 100 and 200.

The first and second V-DMOS transistors 10 and 10 are formed on the second substrate 13 on which the first and second V-DMOS transistors 100 and 200 are formed.
Corresponding to the boundaries that divide the 0 and 200 regions, the first
2 parallel grooves are formed up to the substrate 11 of
An oxide film is buried corresponding to each of the trenches to form first and second trench isolation oxide films 151 and 152.
Then, the first and second trench isolation oxide films 151
And 152, a P type diffusion region 16 is formed. Then, the P-type diffusion layer 16 is connected to the lowest potential (ground).

The diffusion layer 16 has P-type wells 101, 102 ... Further 201, 202, ... with respect to the main surface of the second substrate 13.
Although they can be formed at the same time in the step of forming, it is of course possible to form them in separate steps. Further, the trench isolation oxide films 151 and 152 reduce the gain of the parasitic PNP transistor generated when the first V-DMOS 100 is turned on, for example.
^{The +} is formed to a depth reaching the first substrate 12.

In this embodiment, first and second power transistors V-DMOS transistors 100 and 200 are formed on a semiconductor substrate 11 which is the same chip, and two columns are formed between the transistors 100 and 200. Trench isolation oxide films 151 and 152 were formed, and a P diffusion layer 16 was formed in a line between them. However, the isolation structure of the first and second V-DMOS transistors 100 and 200 is such that between the two parallel P diffusion layers 161 and 162 and the P diffusion layers 161 and 162 as shown in FIG. It may be constituted by one trench isolation oxide film 15 formed in the above.

FIG. 3 shows a manufacturing process for realizing such a structure of a semiconductor device. First, as shown in FIG. 3A, a first silicon substrate 31 having one surface mirror-polished is prepared. Recesses 321 to 32 are formed on the polished main surface side of the silicon substrate 31 by chemical etching or reactive etching.
Form 3 Then, grooves 331 and 332 are formed corresponding to the recesses 321 and 322, respectively, and further the recesses are formed.
Grooves 333 and 334 are formed corresponding to both ends of 323.

Next, as shown in FIG. 2B, a second silicon substrate 34 having one surface mirror-polished is prepared. The mirror-polished surface of the second silicon substrate 34 is provided with concave portions 321 to 323 and grooves.
The main surface side of the first silicon substrate 31 on which 331 to 334 are formed,
That is, the surfaces in which the concave portions 321 to 323 are opened are bonded together and integrated. Then, in a state in which the first and second silicon substrates 31 and 34 are integrally bonded together in this manner, a closed chamber formed by the recesses 321 to 323 and the grooves 331 to 334 corresponding to the bonding surfaces. Is thermally oxidized so that it is filled with the oxide film 35.

If an oxide film 35 formed by thermal oxidation is formed between the first and second silicon substrates 31 and 34 thus bonded together, as shown in FIG. The back surface side of the silicon substrate 31, that is, the surface opposite to the opened surface of the recesses 321 to 323 is ground and polished to form the grooves 321 to 323.
The first silicon substrate 31 is thinned until the exposed portion of the.

In this way, the trench isolation oxide films 151 and 152 shown in FIG. 1 are formed by the oxide film 35 formed corresponding to the trenches 331 and 332. In this case, the recess
Oxide film 35 formed corresponding to 323 and grooves 333 and 334.
Will set the element region specified on the polished surface of the first silicon substrate 31.

Then, an oxide film is appropriately formed on the polished surface of the first silicon substrate 31, a mask is formed by a lithography process, and then a groove is formed by the ion implantation process.
A P-type diffusion layer 16 is formed between the first and second layers as shown in FIG. At the same time, ions are implanted into a region surrounded by the trenches 333 and 334 and the recess 32 to form the P-type well 17, so that a transistor for forming a control circuit or the like is formed. Here, in the lithography process for ion implantation, the grooves 331 to 334 are used for mask alignment.

Thereafter, the first and second V-DMOSs are
Predetermined gates 110, 210, 410, 510 are formed of polysilicon to form transistors 100 and 200, and wells 101, 102, ... And 201, 202 are formed by diffusion of P ions in a self-aligned manner with respect to the polysilicon gates.
, N-type diffusion layer 18 and P-type diffusion layer 19 are formed.
Is formed in a desired region to obtain a semiconductor device as shown in FIG. In this case, although not shown in the figure, V-DMO can be obtained by appropriately providing wiring and a protective film.
A semiconductor device including two power transistors including S transistors 100 and 200 is completed.

Note that such a manufacturing method is not limited to the case where a plurality of power transistors are formed on the same chip, but the control circuit and the plurality of power transistors are formed on the same chip, and the control circuit and the power are formed by using the SOI structure. It can be applied effectively without increasing the number of steps when separating transistors.

In the semiconductor device having such a structure,
The operation of the parasitic PNP transistor when one of the plurality of V-DMOS transistors is turned on is relaxed, and the current flowing through the other transistor is absorbed in the P diffusion layer. Mutual interference between the formed power transistors is effectively reduced.

For example, when the first and second V-DMOS transistors are arranged side by side on the same chip without forming the P diffusion layer and the trench isolation oxide film as shown in the embodiment, the parasitic The transistor gain (H _FE ) easily exceeds "1". However, when the P diffusion layer and the trench isolation oxide film are formed as shown in the embodiment, the gain of the parasitic PNP transistor can be easily set to "1" or less, and the parasitic current is absorbed by the P diffusion layer. Therefore, it is possible to suppress a malfunction when the source potential of the V-DMOS transistor rises above the drain potential due to ON / OFF of the V-DMOS transistor or noise.

Specifically, the first and the second on the high side
Second V-DM of the parasitic PNP transistor which operates when the first V-DMOS transistor 100 is turned off during the operation of the V-DMOS transistors 100 and 200 of FIG.
The influence on the OS transistor is reduced.

[0025]

As described above, according to the power semiconductor device of the present invention, when a plurality of power transistors, which use the substrate as a common drain, are formed on the same semiconductor chip, the power semiconductor device has a common substrate. A parasitic bipolar transistor based on the drain is formed, the gain of this parasitic transistor is reliably reduced, and the current that flows from one power transistor to another is absorbed by the diffusion layer. . Therefore, the plurality of power transistors on the same chip do not interfere with each other, and the reliability of the operation can be effectively ensured.

[Brief description of drawings]

FIG. 1A is a view showing a cross-sectional structure of a power semiconductor device according to an embodiment of the present invention, and FIG. 1B is a plan view structure of the same semiconductor device, showing a cross-section corresponding to line aa. Is shown in FIG.

FIG. 2 is a diagram showing a cross-sectional structure of a semiconductor device according to a second embodiment of the present invention.

3A to 3C are views for sequentially explaining steps for manufacturing the semiconductor device.

4A and 4B are views for explaining the manufacturing process following FIG.

[Explanation of symbols]

11 ... Semiconductor substrate, 12 ... First substrate, 13 ... Second substrate, 10
0, 200 ... First and second V-DMOS transistors, 101, 102, ... 201, 202, ... P-well, 110, 21
0 ... Gate, 15, 151, 152 ... Trench isolation oxide film, 1
6, 161, 162 ... P diffusion layer.

Claims (2)

[Claims] 1. A semiconductor substrate composed of a high-concentration first substrate to be used as a common drain, and a low-concentration second substrate bonded to the first substrate, and the semiconductor substrate. A plurality of power transistors formed by dividing a region on the main surface of the second substrate, and a plurality of power transistors on the second substrate corresponding to the boundary lines so as to divide the regions of the plurality of power transistors. At least one diffusion layer formed by embedding, and a trench isolation oxide film embedded in a groove formed in the second substrate at a depth up to the first substrate corresponding to the diffusion layer The power semiconductor device according to claim 1, wherein the diffusion layer is set to a lowest potential with respect to the plurality of power transistors. 2. The semiconductor substrate is N-type, and each of the plurality of power transistors is a plurality of P.
The power semiconductor device according to claim 1, wherein the power semiconductor device is constituted by a V-DMOS including a well.