JPH01223769A - Semiconductor device and manufacture of the same - Google Patents

Abstract

PURPOSE:To remove the danger of latch up derived from a trigger pulse and variation in temperature from the outer environment by forming a transistor for large current or high dielectric strength on a substrate area where a buried insulation layer is removed and by forming a transistor for small current or low dielectric strength on the other areas. CONSTITUTION:To leave a semiconductor layer 54 on a first main surface of an n-type single semiconductor substrate 52, oxygen ion implantation is made to form an insulation layer 53. Then, an insulation 74 is formed on a semiconductor layer 54 on the main surface of the semiconductor substrate 52. Some portion of the insulation layer 74 is etched to expose the semiconductor layer 54, and etched to the depth reaching the semiconductor substrate 52 to form a groove 75. Then, for example, a p-type semiconductor film is accumulated so that at least the semiconductor substrate 52 is epitaxially grown on the bottom surface of the groove on the main surface of the semiconductor substrate 52. This results in the single crystal layer 55 being formed in the portion whose basement is the semiconductor substrate 52, and a polycrystalline layer 55' being formed in the portion whose basement is the insulation layer 74. Then, only the polycrystalline layer 55 accumulated is selectively removed by chemical etching, and further the insulation layer 74 is removed.

Description

[Detailed description of the invention] [Industrial application field] The present invention has high reliability under large current and high voltage environments.

The present invention relates to a semiconductor device that operates at high speed and a method of manufacturing the same.

[Conventional technology]

An example of a conventional semiconductor device of this type is shown in FIG. Third
In the figure, 1 is an n-type semiconductor substrate, 2 is an insulating film for electrically isolating individual transistors, 3a is a gate oxide film of a large current transistor, 3b, 3ef'i controls a large current transistor 4 is the gate electrode of the transistor for large current; 4b, 4e is the gate electrode of the transistor for controlling the large current transistor;
is the p-cedar oil region of a large current n-channel transistor,
6 is the p-cedar oil region of the n-channel transistor, Ryo, 8
is an n-type source region of a large current n-channel transistor, 9 is a source region of a p-channel transistor, 10 is a drain region of a p-channel transistor, 11 is a source region of an n-channel transistor, and 12 is an n-channel transistor 13 is the drain region of the transistor diverted from dog 1, 14a is the gate electrode barrier of the p-channel transistor, 14b is the gate electrode barrier film of the n-channel transistor, 15 is the insulating film, and 16 is the gate electrode diverted. The source electrode of the transistor, 11 is the source electrode of the p-channel transistor, and 18 is the drain of the p-channel transistor! ffl, I9 The source 44.20 of the n-channel transistor is the drain-1 pole of the n-channel transistor.

Until now, in semiconductor devices configured in this way,
The dog transistor was manufactured without being mixed on the same chip as other transistors.

This is because the back-door method for manufacturing large-current transistors is far from the manufacturing method for general transistors, and the main use was for applications where a single large-current transistor was sufficient. In recent years, applications have begun to be considered for various consumer electronic products, etc., and by mixing high-current transistors with other general transistors, they can be incorporated into high-performance integrated circuits, expanding the range of applications. There is a movement to do so. To meet such demands, it is increasingly possible to combine relatively small size transistors as shown in area Bl on the same chip in addition to large current transistors as shown in area A in Figure 3. . However, with this configuration, the source region 9→semiconductor substrate 1
→ p-type active region 5 → n-type source region 8 or drain region 10 → semiconductor substrate 1 → p-type active region 6 → source region 11. By parasitically incorporating a semiconductor device with a pnpn junction structure in the direction of There is a risk that a so-called latch-up phenomenon may occur due to the trigger pulse. This latch-up phenomenon cannot be recovered unless the power is cut off, so if left untreated, an abnormally large current will flow through the terminal series, resulting in damage or burnout of the semiconductor device.

As a solution to this problem, a method of insulating and separating transistors from each other has been proposed. An example of this is shown in FIG. In FIG. 4, 21 is a substrate 22m formed by depositing a polycrystalline semiconductor.

Is 22b between transistors? An insulating film for insulation separation, 23 is a p-sugi oil sum layer of a large current n-channel transistor, 24
25 is the p-cedar oil column layer of the n-channel transistor, 25 is the low impurity concentration n-type drain region of the large current transistor, and 2
6 is an n-cedar oil region of a p-channel transistor, 27 is a drain region of a large current transistor, 28 is an insulating film that electrically isolates the transistor in the lateral direction, 29a,
29b and 29e are transistor gate insulating films;
0a, 30b, 30c are gate electrodes of transistors, 31a, 31b, 31c are insulating films that protect the gate electrodes of transistors, 32.33 is a source region of a large current transistor, 34 is a source region of an n-channel transistor, 35 36 is the drain region of the n-channel transistor, 37 is the drain region of the p-channel transistor, 38 is an insulating film for electrically separating the electrodes, and 39 is the large current transistor. Drain electrode, 40 is a source electrode of a large current transistor, 41 is a source electrode of an n-channel transistor, 42 is a drain/electrode of an n-channel transistor, 43 is a source electrode of a p-channel transistor, 44 is a p-channel transistor is the drain electrode of

A method of manufacturing a semiconductor device constructed in this way is shown in FIG.
This will be explained using a) to (j). First, as shown in Figure (a), for example, the main surface has a (100) crystal orientation.
A Kn-type region 46 is formed on a part of the first main surface of a shaped single-crystal semiconductor substrate 45. Next, as shown in FIG. 4B, an n-type single crystal semiconductor region 47i is formed on the main surface of the semiconductor substrate, and an insulating film 48 is further formed on this semiconductor region 47. After that, as shown in the same figure (C), this insulating film 48
Etch it in the specified place with the specified dimensions and press the button 48.
a, forming 48b. At this time, the button 48a is arranged so as to include the n shadow area 46 directly below it, and the other button 48b is arranged so as not to include the n shadow area. Thereafter, the semiconductor region 47. n shadow area 46. The active region 2 is formed by anisotropic etching in the direction of the semiconductor substrate 45 to form an island-like region having a laminated structure of the semiconductor substrate 45 and the drain region 25.
Laminated structure of 6a and semiconductor substrate 45 and active region 26
An island-like region is formed in which the regions of the laminated structure of a, 26b and the semiconductor substrate 45 are adjacent to each other. Next, the same figure (d)
After removing the battens 49B and 48b, as shown in FIG.
Then, n-type impurities are selectively diffused onto the first main surface side of the semiconductor substrate 45 to form the drain region 27 of the large current transistor. Next, as shown in FIG. 4E, after removing the insulating film 49, an insulating film 22 is formed on the first main surface side of the semiconductor substrate 45, and then K
For example, a polycrystalline semiconductor layer 21 is deposited to a predetermined thickness. Next, as shown in FIG. 4F, the second main surface of the semiconductor substrate 45 is polished over the entire surface until the polycrystalline semiconductor layer 21 appears. Next, as shown in FIG.
An insulating film 38a is formed on the second main surface of the transistor 5, and an insulator 28 is formed to electrically isolate the transistors in order to form both an n-channel transistor and a p-channel transistor in the region B2. , and region A, an n-type shadow region 27a and an n-type source region 50 are formed to connect the drain electrode of the large current transistor. Next, as shown in FIG. 6(h), an insulator 38 is formed on the main surface of the p-cedar oil-based region 24 for the n-channel transistor in region B2 and on the main surface of the n-cedar oil-based region 26 for the p-channel transistor.
A part of the insulator 38a on the source region 50 of the large current transistor in the region A is removed, and part of the active layer 23 and the drain region 25 is removed from the source region 50. A trench 51 for a gate electrode is formed by etching the semiconductor region up to the bottom. After that, the same figure (1
), the gate insulating film 2 of the Taisei diversion transistor is
9a, gate insulating film 2 of n-channel transistor
9b and gate insulating film 2 of p-channel transistor
After forming the gate electrodes 9C, the gate electrodes 30a are formed.

30b and 30e are formed. Thereafter, as shown in FIG. 2(j), gate electrodes 30a, 30b, 30c
Q) Insulating films 31a, 31b, 31 on exposed surfaces
After forming the respective source regions 34.c of the n-channel transistors. Drain region 35 and source region 36 of the p-channel transistor. A drain region 31 is formed, an insulating film 38b is formed on the second main surface side of the semiconductor substrate, and then a portion of the source and drain regions of each transistor is exposed by etching to form electrodes 39.4.
0, 41.42, and 43.44, respectively.

In this way, the configuration shown in FIG. 4 eliminates latch-up along the source region 36-active region 26-active layer 23-source region 33 path, which was a problem in the configuration shown in FIG. can be resolved.

[Problem to be solved by the invention]

However, according to the configuration shown in FIG. 4 described above, source region 36 - active region 26 - active layer 24 - source region 34
Since there is a 0 route, a complete solution has not been reached.

In order to cut off this path, it is necessary to confine the n-channel transistor and the p-channel transistor individually in island-like regions of the semiconductor substrate. When forming small transistors that are actually used in individual island regions, in order not to easily increase the area of the island region, the bottom surface of the island region formed in the step shown in FIG. It is necessary to reduce the size of the slam as much as possible. However, from Fig. 5(e) to (f
), in the process of polishing the semiconductor substrate 45 until the active layer 23.24 and the regions 25.26
．． It is impossible to uniformly control the thickness of the semiconductor substrate 45 to about 10 μm or less over the entire surface of the semiconductor substrate 45. Therefore, the surface dimensions of the island-like regions formed by anisotropic etching of the semiconductor substrate 45 are approximately 20 .mu.m.times.20 .mu.m or more, resulting in a significant increase in the dimensions of the integrated circuit.

Furthermore, since a polishing step is required, there is a problem in that it leads to an increase in cost. Furthermore, in the above configuration, the area of the drain region of the large TJLK transistor is narrower than in the configuration shown in FIG. There was a problem that

Therefore, the present invention has been made in view of the above-mentioned conventional problems, and its purpose is to provide various electrical characteristics from high to low withstand voltages and from large currents to small currents on the same semiconductor substrate. Manufacturing of semiconductor devices that combines semiconductor devices tjL' with high functionality and extremely high reliability, and eliminates the risk of latch-up due to trigger pulses from harsh external environments, 0A fluctuations, etc. The purpose is to provide a method.

[Means to solve the problem]

The semiconductor device according to the present invention is configured such that each semiconductor device is individually separated using an insulator.

A method for manufacturing a semiconductor device according to the present invention includes a substrate in which oxygen or nitrogen ions are implanted from the main surface side of the semiconductor substrate to form an embedded insulating layer inside the semiconductor substrate, and a predetermined semiconductor region exposed on the main surface is The buried insulating layer immediately below the semiconductor region is removed together, and a large current or high voltage transistor is formed in the area where the buried insulating layer is removed, and a small current or low voltage transistor is formed in the other area. It is something that forms.

[Effect]

In the present invention, the high-quality semiconductor substrate used at the start of manufacturing is itself used as the drain region of the high-current or high-voltage transistor, so the characteristics of the transistor are not sacrificed. 7) By thinning the semiconductor layer on the main surface, peripheral transistors mounted together to control large current or high withstand voltage transistors can be made to have a high number of transistors and operate at high speed. Furthermore, since K separates the peripheral transistors individually with an insulator layer, latch-up is eliminated.

〔Example〕

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a sectional view showing an embodiment of a semiconductor device according to the present invention. In the same figure, 52 indicates the crystal axis of the main surface (10
0), 53 is an insulating film formed by oxygen ion implantation, 54 is a semiconductor layer on the main surface side, 55
is a p-cedar oil column layer of a large current n-channel transistor, 5
6 is the p cedar oil column layer of the n-channel transistor, 5T is the p
Channel type transistor n cedar oil region, 58a r
58b+58c is the gate insulating film of the transistor, 59
a! 59b and 59c are gate electrodes of transistors, 60 is a drain region of a large current transistor, and 61
is the source region of the large current transistor, 62a, 6
2b and 62c are insulating films that protect the gate electrodes of the transistors, and 63 is the source 1 of the n-channel transistor.
Drain region of L64Un channel transistor, 6
Reference numeral 5 denotes a source region L66 of a p-channel transistor, reference numeral 67 indicates an insulating film for electrically separating electrodes, and reference numeral 68 indicates a lateral electrical connection between a large current transistor and another transistor. 69 is the source electrode of a large current transistor, 7G
71 is a source electrode of an n-channel transistor, 71 is a drain electrode of an n-channel transistor, 72 is a source electrode of a p-channel transistor, 73 is a drain electrode of a p-channel transistor, and 74 is an electrical connection between the transistors in the lateral direction. It is an insulating layer that separates the

FIGS. 2(a) to 2(i) are cross-sectional views of steps for explaining an embodiment of the method for manufacturing the semiconductor device shown in FIG. 1. In the figure, first, as shown in Figure (a), an insulating layer 53 is formed by implanting oxygen ions to leave a semiconductor layer 54 on the first main surface side of an n-type single crystal semiconductor substrate 52, for example. . Next, as shown in FIG. 5B, an insulating layer 74 is formed on the semiconductor layer 54 on the main surface side of the semiconductor substrate 52.
A part of the insulating layer T4 is etched to expose the semiconductor layer 54, and the exposed semiconductor substrate 52 is etched using the remaining insulating layer 74 as an etching mask.
A groove 75 is formed by etching with a depth of 1 from the insulating layer 53 to the semiconductor substrate 52. Thereafter, for example, a p-type semiconductor film is deposited so that at least the semiconductor substrate 52 is epitaxially grown on the bottom surface of the trench T5 on the first main surface side of the semiconductor substrate 52, as shown in FIG. 2C. As a result, a single crystal layer 55 is formed in the portion where the underlying semiconductor substrate 52 is the base, and a polycrystalline layer 55' is formed in the portion where the underlying insulator layer 74 is the base.

Next, as shown in Figure (1), only the polycrystalline layer 55 deposited in the process of Figure (C) is selectively removed by a chemical etching method, and after removing the insulating layer 74, the semiconductor substrate is etched. The first main surface side of the semiconductor substrate 52 is covered with an insulating film 76, and then an insulating material 68, for example, is deposited on the insulating film 76. Next, as shown in FIG. After exposing the insulating film 76 by uniformly etching it from the first main surface side of the semiconductor substrate 52, an n-type base region 61 is formed only in the large current transistor region on the first main surface side of the semiconductor substrate 52.Next, As shown in FIG. 3(f), after forming the p-cedar oil-based region 56 of the n-channel transistor and the n-cedar oil-based region 57 of the p-channel transistor, the region B3K
on the main surface of the p-cedar active region 56 of the n-channel transistor and the n-cedar oil-based region 5 of the p-channel transistor.
removing and exposing a part of the insulating film T6 on the main surface of T;
In addition, the source region 6 of the large current transistor in region A3
A groove 78t for a gate electrode is formed by removing a part of the insulating film 76 on the semiconductor substrate 1 and etching the semiconductor region from the source region 61 to the single crystal layer 55 and a part of the semiconductor substrate 52. In addition, an n-channel transistor and a p-type transistor are provided in region B3.
Insulator layers 77a and 77b are formed to electrically isolate the channel type transistors. After that, as shown in FIG.
, After forming the gate insulating film 58b of the n-channel transistor and the gate insulating film 58c of the p-channel transistor, gate electrodes 59a and 59b are formed, respectively.
, forming 59c. Thereafter, as shown in FIG. 6(6), insulating films 62m, 62b, and 62c are formed on the exposed surfaces of the gate electrodes 59a, 59b, and 59c, respectively. Drain regions 63, 64, 65, and 66 are formed. After that, the same figure (i
), an insulating film 6γ is formed on each transistor, and the source and drain regions 61, 63, 64°65.66
The upper part is exposed by etching and one electrode 69, 70 is formed.
, 71, 72, and 73, respectively.

With such a configuration and method, all transistors are completely electrically isolated by the insulator, eliminating the risk of latch-up. Further, since the drain region of the large current transistor can be arranged on the second main surface, the parasitic resistance of the drain can be sufficiently reduced.

Note that in the configuration shown in FIG. 1 described above, the plane orientation of the main surface of single crystal semiconductor substrate 52 is not limited to (100). When the plane orientation is set to (100), the mobility of electrons and holes on the main surface side of the active region 56, 57 of region B3 is the highest compared to cases where other plane orientations are selected, and the electrons and holes formed in region B3 are The gate of the transistor in which the structure is oriented is located in a plane orientation different from the main surface, and the mobility of electrons is smaller than that in the case of the plane orientation (100), so the on-resistance of the large current transistor increases relatively. On the other hand, if the main surface of the semiconductor substrate 52 has a plane orientation other than (4oO), the mobility of electrons and holes in the transistor in region B3 decreases, but the mobility of electrons in the transistor in region A3 't −
Therefore, the on-resistance of the large current transistor can be minimized. Therefore, which one to select is a problem that should be determined depending on the purpose of use of the semiconductor device, and is not a problem that can be determined uniquely.

〔Effect of the invention〕

As described above, according to the present invention, a wide variety of extremely excellent effects can be obtained as shown below. That is, (1) Since the insulating layer is formed by ion implantation, the thickness of the active region of the transistor formed on the insulating layer can be freely controlled within a certain range, and the characteristics of the transistor can be controlled.

(II) Since large current or high voltage transistors are manufactured in a semiconductor region that is epitaxially grown on a high quality semiconductor surface at the start of manufacturing, conventional technology can be used as is, and large current or high voltage transistors can be manufactured using There is no need to sacrifice the characteristics of high voltage transistors.

(itl) It is easy to completely insulate and separate MIS transistors individually.

11V) Free from the risk of latch-up caused by trigger pulses from harsh external environments, temperature fluctuations, etc.
The reliability of devices to which this semiconductor device is applied is dramatically improved.

(■) Since this is a method of insulating and separating transistors individually, it is possible to arbitrarily combine semiconductor devices with various electrical characteristics from high to low withstand voltages on the same semiconductor substrate, providing an extremely high degree of freedom in design. Become.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view showing an embodiment of a semiconductor device according to the present invention, and FIGS. 3 and 4 are cross-sectional views showing conventional semiconductor devices, and FIG. 5 (
=) to (j) are cross-sectional views of steps illustrating a conventional method for manufacturing a semiconductor device. Each part will be explained in detail below. 52... Semiconductor substrate whose main surface has a crystal axis of (100), 53... Insulating film formed by φ oxygen ion implantation, 54... Semiconductor layer, 55... Large current P-cedar oil column layer of n-channel transistor for use, 56...
P cedar oil column layer of n-channel transistor, 57...
N-cedar oil region of p-channel transistor, 58a,
58bl 58c...Transistor gate insulating film, 59a, 59b. 58c...gate electrode of transistor, 60...
・Drain region of large current transistor, 61...
Source region of large current transistor, 62a, 62
b, 62c...Insulating film for protecting the gate electrode of the transistor, 63...Source region of the n-channel transistor, 64--Drain a region of the n-channel transistor, ss...p Source region of channel type transistor, 66. Drain region of p-channel type transistor, 67... Insulating film for electrically separating the electrode amount, 68... High current transistor and other transistors. 1 horizontally between! electrically isolated insulator) ft, 69...source voltage ffl of the dog'1 diversion transistor, 70---- source voltage of the n-channel transistor, 71... the drain of the n-channel transistor Electrode, 72...source electrode of p-channel transistor, 73...drain electrode of p-channel transistor, T4...insulator layer for electrically separating transistors in the lateral direction, T5・・・Groove, 76・
...Insulating film, 77m, 7γb...Insulator layer. Patent applicant Nippon Telegraph and Telephone Corporation

Claims (2)

[Claims] (1) A first semiconductor substrate having a first conductivity type, a first insulating layer formed in a part of the first main surface of the first semiconductor substrate, and the first insulating layer. a first conductivity type semiconductor layer on the first conductivity type semiconductor layer; a p-channel MIS transistor and an n-channel MIS transistor formed near the main surface of the first conductivity type semiconductor layer; an n-channel MIS having a first electrode and a second electrode on a region on the main surface where the first insulating layer does not exist, and a third electrode on the second main surface of the first semiconductor substrate;
A semiconductor device comprising a transistor. (2) Oxygen or nitrogen ions are implanted into a first semiconductor substrate having at least one type of conductivity type region to a first position at a required depth from the first main surface side of the first semiconductor substrate. forming a second semiconductor substrate having a structure in which the first insulating layer and the first semiconductor layer are laminated into a film from the first semiconductor substrate by forming an insulating layer; Selective etching treatment that extends from the first semiconductor layer to the first insulating layer and a part of the first semiconductor substrate immediately below the first insulating layer in at least a part of the first main surface side of the second semiconductor substrate. forming a third semiconductor substrate in which a part of the first main surface side of the second semiconductor substrate has the same layer structure as the first semiconductor substrate; forming a fourth semiconductor substrate by forming a second semiconductor layer directly above at least the first semiconductor region on the first main surface side; and a step of forming a fourth semiconductor substrate on the first main surface side of the fourth semiconductor substrate. A first electrode, a second electrode, and a third electrode are provided near the main surface of the first semiconductor layer on the first insulating layer or the semiconductor layer on the first insulating layer including the first semiconductor layer. a step of forming a p-channel type MIS transistor and an n-channel type MIS transistor having a second semiconductor layer formed directly above the first semiconductor substrate on the first main surface side of the fourth semiconductor substrate; n-channel type M having a first electrode and a second electrode on the main surface and a third electrode on the second main surface side of the fourth semiconductor substrate
1. A method for manufacturing a semiconductor device, comprising the step of forming an IS transistor.