JP2008091935A - Integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a reliable integrated circuit formed on a semiconductor substrate capable of suppressing a drawback of a temperature rise that occurs in an SOI wafer having a uniform structure. <P>SOLUTION: A partial SOI structure is constituted by locally embedding an insulating material into a single crystal silicon substrate, and a circuit requiring a high speed operation is provided in a part of the SOI structure. Heat generated in an integrated circuit formed in a single crystal silicon layer on an insulating film is transmitted to an end portion of the insulating film, and thereafter is dissipated into the single crystal silicon with a thick region where no insulating film is formed. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor substrate and a manufacturing method thereof.

  Semiconductor silicon on an electrical insulating film is called SOI (Silicon On Insulator) and has recently attracted attention as a semiconductor device capable of high speed and high integration.

  FIG. 2 is a structural sectional view of this SOI wafer substrate. 21 is a single crystal silicon substrate having a thickness of 500 to 1000 μm, 22 is a silicon oxide film (BOX: Buried Oxide) which is an electrical insulator having a thickness of several hundred to several μm, and 23 is a thickness of several hundred to several μm. A silicon oxide film 23, which is an electrical insulator, is single crystal silicon having a thickness of several hundred to several μm.

  In the semiconductor integrated circuit formed on the SOI wafer, since the single crystal silicon layer (SOI layer) 23 on the electric insulating film 22 is very thin, the integrated circuit is particularly a complementary MIS transistor (complementary metal-insulator transistor). If the integrated circuit is formed on a conventional single crystal silicon wafer, the capacitance between the source and substrate, between the drain and substrate, and between the gate substrate is reduced and the speed of the integrated circuit can be increased. In contrast, the presence of the electrical insulator 22 has the advantage that the isolation region between the transistors can be made very narrow and high integration is possible.

  Although it is an SOI wafer having the above-mentioned excellent characteristics, since the insulating film 22 exists immediately below the thin single crystal silicon on which the integrated circuit is formed, it is generated by the current that flows when the integrated circuit is operating. The heat does not escape to the thick semiconductive single crystal silicon substrate under the insulating film 22, but the heat accumulates in the thin single crystal silicon layer 23, and the temperature of the thin single crystal silicon layer is changed over time. It will be raised with.

  When the integrated circuit is formed of complementary MIS transistors, if the transistor size is reduced for high integration, the current flowing in the transistor increases, and the degree of temperature rise also increases. If the temperature rises in a thin single crystal silicon layer, a large number of carrier trap levels are likely to be generated in the gate insulating film of the MIS transistor, resulting in fluctuations in transistor characteristics and further impairing the reliability of the integrated circuit. Become.

  An object of the present invention is to provide a semiconductor substrate capable of suppressing the above-described disadvantage of temperature rise in an SOI wafer and forming a highly reliable integrated circuit.

  An insulating film is locally formed in the single crystal silicon substrate for the purpose of releasing the heat accumulated in the thin single crystal silicon layer (SOI layer) 23. That is, a thin single crystal silicon layer on the insulating film is locally formed in the single crystal silicon substrate.

  When an integrated circuit is formed on the semiconductor substrate of the present invention having the above-described structure, not only the heat generated in the integrated circuit formed on the single crystal silicon in the region where the insulating film is not formed, but also the integrated circuit Dissipated into single crystal silicon with good thermal conductivity spreading underneath. Also, heat generated in the integrated circuit formed in the single crystal silicon layer on the insulating film is transmitted to the end of the insulating film and then dissipated into the thick single crystal silicon in the region where the insulating film is not formed. .

  As described above, in the integrated circuit of the present invention, not only the heat generated in the integrated circuit formed on the single crystal silicon in the region where the insulating film is not formed but also the heat spreading under the integrated circuit. The heat generated in the integrated circuit formed in the single crystal silicon layer on the insulating film is dissipated to the single crystal silicon having good conductivity, and is transmitted to the edge of the insulating film, and then the insulating film is not formed. It is dissipated in the thick single crystal silicon and does not deteriorate the reliability of the integrated circuit caused by an increase in heat, and maintains good characteristics.

  In addition, in the manufacturing method of the present invention of a semiconductor substrate in which an insulating film is embedded in a part of the region, it is possible to obtain a semiconductor substrate having a flat surface by either method of ion implantation or bonding. Has advantages.

  1 (a) and 1 (b) show an embodiment of the present invention. FIG. 1A is a plan view of a semiconductor substrate of the present invention, and FIG. 1B shows a cross-sectional structure diagram along a line A-A ′ in FIG. Reference numeral 11 denotes a single crystal silicon substrate, 12 denotes an insulating film such as a silicon oxide film embedded in the single crystal silicon substrate, and 13 denotes a single crystal silicon layer on the insulating film 12, that is, an SOI layer. Reference numeral 14 denotes a cutting line cut to indicate a certain orientation of the single crystal silicon. The insulating film 12 has a thickness of, for example, several hundred to several μm, and similarly the thin single crystal silicon layer 13 has a thickness of several hundred to several μm.

  FIG. 3 shows an example of a semiconductor device formed using the semiconductor substrate of the present invention shown in FIG. 31 is a single crystal silicon substrate, 32 is a silicon oxide film embedded in the single crystal silicon substrate 31 and having a thickness of several hundred to several μm, and 33 is a thickness of several hundred to several μm on the silicon oxide film 32. A thin single crystal silicon layer, that is, an SOI layer.

  Circuits 1 and 36 are formed on the left side of the single crystal silicon substrate 31 and in the region where the insulator is not buried, and 36 are also formed on the right side of the single crystal silicon substrate and in the region where the insulating film is not buried. Circuits 3 and 35 are circuits 2 formed on a thin single crystal silicon layer on the insulating film 32, respectively. The circuits 34, 35 and 36 are electrically connected to each other to form one integrated circuit having a certain function.

  There is no insulating film under the circuit 1 of 34 and the circuit 3 of 36, and the heat generated by the operation of these circuits has a thickness of several hundred μm or more under the circuit 3 of 34 and 1 of 36. Escape to the thick semiconductive single crystal silicon substrate 31. For this reason, carrier trap levels are not generated in the gate insulating film of the MIS transistor due to the increase in temperature, and the reliability of the transistor group constituting the circuits 1 and 36 of 34 is high and a stable circuit. It becomes.

  On the other hand, the 35 circuit 2 formed in the thin single crystal silicon layer above the insulating film 32, that is, the SOI layer 33 is a circuit that requires high speed. The reason why the integrated circuit formed of the MIS transistors formed in the SOI layer 33 has high speed will be described with reference to FIG.

  When the circuit 2 operates, the heat generated in the SOI layer 33 proceeds to the upper portions 37 and 381 at both ends of the insulating film 32, and is then dissipated to the entire thick single crystal silicon substrate 31 and stops in the SOI layer 33. There is no. For this reason, the temperature of the SOI layer 33 does not rise during the operation of the circuit 2, and no carrier trap level is generated in the gate insulating film of the MIS transistor group constituting the circuit 2. As a result, the reliability of these transistor groups is high, and the circuit 2 operates stably without fluctuation over time.

FIG. 4 shows a cross-sectional structure diagram of an N-type MIS transistor. The reason why the integrated circuit composed of the MIS transistors formed in the SOI layer has high speed will be briefly described with reference to FIG. 41 is a single crystal silicon substrate, 42 is an insulating film such as a silicon oxide film, 43 is a thin concentration, for example, a P-well made of P-type impurities of about 1 × 10 ¹⁶ cm ⁻³ , 44 is a gate insulating film, and 45 is a high concentration. For example, a gate made of polycrystalline silicon containing an N-type impurity of about 1 × 10 ²⁰ cm ⁻³ , 46 and 47 are each a source made of an N-type impurity of a high concentration, for example, about 1 × 10 ²⁰ cm ⁻³ It is a drain. The N-type MIS transistor includes a P well 43, a gate insulating film 44, a gate 45, a source 46, and a drain 47. Reference numeral 48 denotes a field oxide film made of a thick silicon oxide film for element isolation.

  The single-crystal silicon thickness of the P well 43 is, for example, about 0.6 μm. When operating the N-type MIS transistor, for example, the source potential is set to 0V, and the gate and drain are set to 5V. At this time, a depletion layer spreads under the gate, source, and drain. Dashed lines 49, 410, and 411 indicate boundaries of the depletion layer. The depletion layer is a high resistance region with no moving carriers. The depletion layer extends to the right side of the broken line 49, to the left side of 410, and to the upper side of 411.

  For example, if the depth of the source and drain is 0.3 μm, a depletion layer of about 0.9 μm spreads under the drain and about 0.3 μm under the source. The depletion layer is also in contact with the insulating film 42 under. For this reason, the capacitance between the source and the substrate (P well 43) and between the drain and the substrate (P well 43) includes the insulating film 42, and has a very small value. As a result, these parasitic capacitances are reduced, and an integrated circuit composed of MIS transistors formed in the SOI layer has high speed.

  FIG. 5 shows another embodiment of the present invention. The embodiment of the present invention shown in FIG. 5 has much in common with the embodiment of the present invention shown in FIG. Therefore, in FIG. 5, description of the names of the portions 31 to 38 common to FIG. 3 is omitted.

  In FIG. 5, a portion of the single crystal silicon under the silicon oxide film 32 which is an insulating film embedded in a partial region of the single crystal silicon substrate 31 is removed. Reference numerals 51 and 52 denote silicon nitride films, which serve as masks for removing the single crystal silicon under the silicon oxide film 32. When the single crystal silicon is removed, for example, the single crystal silicon substrate may be immersed in a potassium hydroxide solution (KOH solution) heated to 80 ° C. to 100 ° C., for example. The silicon oxide film 32 serves as an etching stopper when the single crystal silicon under the silicon oxide film 32 is removed by etching with a KOH solution, and the thin single crystal silicon film 33 on the silicon oxide film 32 is etched. It also plays a role in preventing After the single crystal silicon under the silicon oxide film 32 is removed, the silicon nitride films 51 and 52 may or may not be removed.

  A manufacturing method for producing the semiconductor substrate of the present invention shown in FIG. 1 will be described with reference to FIGS.

  6A to 6D are process cross-sectional views illustrating a manufacturing method for forming a semiconductor substrate of the present invention.

In FIG. 6A, reference numeral 61 denotes single crystal silicon, and 62 denotes a photoresist having a thickness of several μm coated on the entire surface of the single crystal silicon 61. In FIG. 6B, the photoresist at a location where oxygen is ion-implanted into the single crystal silicon 61 is removed by a photolithography process. Reference numeral 63 denotes a photoresist left by the photolithography process. In FIG. 6C, 64 indicates oxygen ions implanted into single crystal silicon. The acceleration energy when oxygen ions are implanted depends on how deep the silicon oxide film formed under the SOI layer is formed from the surface of the SOI layer. The amount of oxygen ions at the time of ion implantation is about 1 × 10 ¹⁸ cm ⁻² . In FIG. 6D, the photoresist film 63 is removed. Thereafter, when a thermal process of 900 ° C. or higher is applied, single crystal silicon and ion-implanted oxygen atoms react to form a good silicon oxide film 65. However, a good thin single crystal silicon layer 66, that is, an SOI layer is formed on the silicon oxide film 65.

  In FIG. 6, when oxygen ions are implanted, the location to be implanted is selected by removing only a desired portion of the photoresist film 62 applied on the single crystal silicon 61. However, in the method of manufacturing a semiconductor substrate according to the present invention, the method for selecting the position to be ion-implanted is not limited to the method in which the photoresist film 62 applied on the single crystal silicon 61 is removed only at a desired location. .

  7A to 7D are process cross-sectional views showing another embodiment of the manufacturing method for forming the semiconductor substrate of the present invention.

  In FIG. 7A, 71 is single crystal silicon, 72 is a silicon oxide film obtained by thermally oxidizing the single crystal silicon 71 to a thickness of several thousand to several μm, and 73 is on the silicon oxide film 72. The applied photoresist film is shown.

  In FIG. 7B, the photoresist and the silicon oxide film at the location where oxygen is ion-implanted into the single crystal silicon 61 are removed by a photolithography process. Reference numerals 74 and 75 respectively denote a photoresist and a silicon oxide film left by the photolithography process.

In FIG.7 (c), 76 shows the oxygen ion ion-implanted in a single crystal silicon. The acceleration energy when oxygen ions are implanted depends on how deep the silicon oxide film formed under the SOI layer is formed from the surface of the SOI layer. The amount of oxygen ions at the time of ion implantation is about 1 × 10 ¹⁸ cm ⁻² .

  In FIG. 7D, after the ion implantation of oxygen ions, the photoresist film 74 and the silicon oxide film 75 are removed, so that the entire surface becomes a single crystal silicon layer. Thereafter, when a thermal process of 900 ° C. or higher is applied, single crystal silicon and ion-implanted oxygen atoms react to form a good silicon oxide film 77. In addition, a good thin single crystal silicon layer 78, that is, an SOI layer is formed on the silicon oxide film 77.

  In FIG. 7, the silicon oxide film 72 and the photoresist film 73 are used to form the implantation window when oxygen ions are implanted. However, instead of the silicon oxide film 72, another insulating film such as a deposited silicon nitride film is used. Etc., and even if the photoresist film 73 is used thereon, it is possible to use it in one direction.

  6 and 7, the silicon oxide film is used as the insulating film under the SOI layer. However, other insulating films such as a silicon nitride film may be used. That is, in the embodiment of the present invention shown in FIGS. 6 and 7, oxygen ions are implanted, but nitrogen ions are implanted and then annealed to bring the silicon nitride film to a desired depth from the silicon surface. May be formed.

  8A to 8D, 9E to 9G, and 10H to 10J, the manufacturing method for forming the semiconductor substrate of the present invention is described. Another embodiment will be described.

  In FIG. 8A, 81 is single crystal silicon, 82 is a silicon oxide film obtained by thermally oxidizing the single crystal silicon 81 to a thickness of several hundreds of inches, 83 is silicon having a deposited thickness of 1000 to 2000 mm. A nitride film 84 is a photoresist film coated on the silicon nitride film 83.

  In FIG. 8B, a window 85 is opened at a desired position of the photoresist by a photolithography process.

  In FIG. 8C, the silicon nitride film 83 at the portion where the window of the photoresist film is opened is removed.

  In FIG. 8D, the photoresist film remaining on the silicon nitride film is removed and thermally oxidized to form a silicon oxide film 86 having a thickness of several thousand to several μm.

  In FIG. 9E, the remaining silicon nitride film is removed.

  In FIG. 9F, a photoresist film 87 is deposited on the entire upper surface of the silicon oxide films 82 and 86.

  In FIG. 9G, all of the thin silicon oxide film 82 and the deposited photoresist film 87 and a part of the thick silicon oxide film 86 are etched by dry etching or the like. As a result, silicon oxide films 88 whose surfaces are flush with the surface of the single crystal silicon are newly formed at a plurality of desired positions in the single crystal silicon substrate.

  Here, the single crystal silicon substrate used in the steps of FIG. 8A to FIG.

  In FIG. 10H, a new single crystal silicon substrate 89 (referred to as a B substrate) is prepared.

  In FIG. 10I, the A substrate and the B substrate are bonded together with the silicon oxide film 88 inside in a high-temperature oxygen atmosphere at 1100 to 1200.degree. A silicon oxide film 810 is formed around the A substrate and the B substrate.

  In FIG. 10J, the single crystal silicon on the A substrate side is polished and polished so that the single crystal silicon left on the silicon oxide film 88 is left in a desired thickness. As a result, the single crystal silicon substrate of the present invention as shown in FIG. 1B in which the silicon oxide film 88 is embedded in the single crystal silicon is completed. The silicon oxide film 810 around the single crystal silicon substrate may or may not be removed.

  The semiconductor substrate manufacturing method of the present invention shown in the process cross-sectional views of FIGS. 8A to 10J uses a so-called bonding method in which two single crystal silicon substrates are bonded to each other.

  The embodiment of the present invention shown in FIG. 8A to FIG. 10J is one representative example, and this is not necessarily the case.

  That is, in FIG. 8A, the silicon oxide film 82 is not always necessary.

  In FIG. 9 (f), a photoresist 87 is applied to the entire surface of the single crystal silicon substrate 81. However, the applied material is not necessarily limited to the photoresist, and a silicon oxide film, a silicon nitride film, and the like are applied. A silicon oxide film (commonly known as SOG: SPIN ON GLASS) formed by heat treatment at a temperature of about 400 ° C. or an insulating film such as polyimide may be used. By applying some kind of insulating film, the surface of the insulating film is flattened, and an etching condition that can obtain an etching rate almost equal to that of the silicon oxide film 86 is obtained. It can be formed flat as shown in 9 (g).

  11A to 11D, FIGS. 12E to 12G, and FIGS. 13H to 13I, cross-sectional views of the manufacturing method for forming the semiconductor substrate of the present invention. Another embodiment will be described.

  In FIG. 11A, reference numeral 1101 denotes a single crystal silicon substrate, and 1102 denotes a photoresist film coated on the single crystal silicon substrate 1101.

  In FIG. 11B, a window 1103 is opened at a desired position of the photoresist by a photolithography process. A silicon oxide film is buried under the window 1103 in the final process. Reference numeral 1104 denotes a photoresist left after the photolithography process.

  In FIG. 11C, the single crystal silicon in the portion where the window of the photoresist film is opened is etched to a desired depth by dry etching or the like. Reference numeral 1105 denotes a concave portion etched by single crystal silicon. The remaining photoresist 1104 is removed.

  In FIG. 11D, a silicon oxide film 1106 having a thickness of several thousand to several μm is formed by thermal oxidation.

  In FIG. 12E, a photoresist film 1107 is applied to the entire upper surface of the silicon oxide film 1106.

  In FIG. 12F, the entire surface of the photoresist film 1107 is etched by dry etching or the like until a silicon oxide film on the bottom surface 1108 of the single crystal silicon appears at a position etched by a desired depth in FIG. (Usually called etchback). As a result, silicon oxide films 1109 are formed at a plurality of desired positions on the surface of the single crystal silicon substrate 1101.

  Here, the single crystal silicon substrate used in the steps of FIG. 11A to FIG.

  In FIG. 12G, a new single crystal silicon substrate (referred to as a B substrate) 1110 is prepared.

  In FIG. 13H, the A substrate and the B substrate are bonded together with the silicon oxide film 1109 inside in a high temperature oxygen atmosphere of 1100 to 1200 ° C. A silicon oxide film 1111 is formed around the A substrate and the B substrate.

  In FIG. 13I, the single crystal silicon on the A substrate side is polished and polished so that the single crystal silicon left on the silicon oxide film 1109 is left in a desired thickness. As a result, the silicon oxide film 1109 is embedded in the single crystal silicon substrate 1112, and thin single crystal silicon layers 1113 are formed on the silicon oxide film 1109 at a plurality of desired locations in the silicon substrate. The single crystal silicon substrate of the present invention as shown in FIG. The silicon oxide film 1111 formed around the single crystal silicon substrate 1112 may or may not be removed.

  The semiconductor substrate manufacturing method of the present invention shown in the process cross-sectional views of FIGS. 11A to 12I uses a so-called bonding method in which two single crystal silicon substrates are bonded to each other.

  The embodiment of the present invention shown in FIG. 11A to FIG. 12I is one representative example, and this is not necessarily the case.

  That is, in FIG. 11D, the silicon oxide film 1106 formed by thermally oxidizing the single crystal silicon substrate is not necessarily a silicon oxide film. A silicon nitride film may be deposited instead of the silicon oxide film. In this case, 1109 in FIG. 13I is a silicon nitride film.

  In FIG. 12E, a photoresist film 1107 is deposited on the entire surface of the single crystal silicon substrate 1101. However, 1107 is not necessarily limited to the photoresist film. It may be a nitride film, a silicon oxide film formed by applying and heat-treating at a temperature of about 400 ° C. (commonly known as SOG: SPIN ON GLASS), or an insulating film such as polyimide. By forming an insulating film on the surface of the silicon substrate, flattening the surface of the insulating film, and obtaining an etching condition capable of obtaining an etching rate substantially equal to that of the silicon oxide film 1106, the subsequent etching can be performed to obtain single crystal silicon. The surface of the substrate can be formed flat as shown in FIG.

(A) is a top view of the semiconductor substrate of this invention, (b) is sectional drawing of the semiconductor substrate of this invention. It is a structure sectional view of an SOI wafer. It is a structure sectional view of a semiconductor device formed using a semiconductor substrate of the present invention. It is a structure sectional view of an N type MIS transistor. It is a structure sectional view of a semiconductor device formed using a semiconductor substrate of the present invention. (A)-(d) is process order sectional drawing which shows the manufacturing method of the semiconductor substrate of this invention. (A)-(d) is process order sectional drawing which shows the manufacturing method of the semiconductor substrate of this invention. (A)-(d) is process order sectional drawing which shows the manufacturing method of the semiconductor substrate of this invention. (E)-(g) is process order sectional drawing which shows the manufacturing method of the semiconductor substrate of this invention. (H)-(j) is process order sectional drawing which shows the manufacturing method of the semiconductor substrate of this invention. (A)-(d) is process order sectional drawing which shows the manufacturing method of the semiconductor substrate of this invention. (E)-(g) is process order sectional drawing which shows the manufacturing method of the semiconductor substrate of this invention. (H)-(i) is process order sectional drawing which shows the manufacturing method of the semiconductor substrate of this invention.

Explanation of symbols

11, 31, 61, 81 Monocrystalline silicon substrate 22 Silicon oxide film BOX
12, 32, 65, 88 Buried insulating film 64, 76 Oxygen ion 87, 1107 Photoresist 13, 33, 66, 1113 Thin single crystal silicon layer on insulating film

Claims (4)

A single crystal silicon semiconductor substrate;
The local region of the semiconductor substrate has a flat lower surface and an upper surface facing each other, which are disposed on the same surface and separated from the front surface and the back surface of the semiconductor substrate. A silicon oxide film in contact with a crystalline silicon semiconductor substrate;
A first circuit composed of a MIS transistor which is formed on the first surface of the semiconductor substrate on the silicon oxide film and requires high speed operation;
A second circuit composed of a MIS transistor formed on the second surface of the semiconductor substrate not embedded with the silicon oxide film, and the thickness of the semiconductor substrate below the first surface is several The heat generated in the first circuit formed in the first surface region is transferred to the end of the silicon oxide film, and then the silicon oxide film is formed. An integrated circuit characterized in that it is dissipated in a semiconductor substrate in a non-region. A semiconductor substrate formed with a silicon oxide film embedded in a planar local region and away from the front surface and the back surface;
A first circuit comprising a MIS transistor formed on a first surface of the semiconductor substrate on the silicon oxide film and having a depletion layer under the drain reaching the silicon oxide film;
The first circuit formed in the first surface region, the second circuit including a MIS transistor formed on the second surface of the semiconductor substrate not embedded with the silicon oxide film. The integrated circuit is characterized in that the heat generated in the step is transferred to an end portion of the silicon oxide film and then dissipated into a semiconductor substrate in a region where the silicon oxide film is not formed. A single crystal silicon semiconductor substrate;
The local region of the semiconductor substrate has a flat lower surface and an upper surface facing each other, which are disposed on the same surface and separated from the front surface and the back surface of the semiconductor substrate. A silicon oxide film in contact with a crystalline silicon semiconductor substrate;
A first circuit comprising a MIS transistor formed on a first surface of the semiconductor substrate on the silicon oxide film and having a depletion layer under the drain reaching the silicon oxide film;
The first circuit formed in the first surface region, the second circuit including a MIS transistor formed on the second surface of the semiconductor substrate not embedded with the silicon oxide film. The integrated circuit is characterized in that the heat generated in the step is transferred to an end portion of the silicon oxide film and then dissipated into a semiconductor substrate in a region where the silicon oxide film is not formed.   The integrated circuit according to claim 1, wherein a removal portion for exposing the lower surface of the silicon oxide film is formed in a semiconductor substrate between the silicon oxide film and a back surface of the semiconductor substrate.

Images