CN101958317A - Wafer structure and manufacturing method thereof - Google Patents
Wafer structure and manufacturing method thereof Download PDFInfo
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- CN101958317A CN101958317A CN2010102357212A CN201010235721A CN101958317A CN 101958317 A CN101958317 A CN 101958317A CN 2010102357212 A CN2010102357212 A CN 2010102357212A CN 201010235721 A CN201010235721 A CN 201010235721A CN 101958317 A CN101958317 A CN 101958317A
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- Prior art keywords
- semiconductor substrate
- buried oxide
- wafer structure
- wafer
- oxide layer
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- 238000004519 manufacturing process Methods 0.000 title claims abstract description 31
- 239000000758 substrate Substances 0.000 claims abstract description 60
- 239000004065 semiconductor Substances 0.000 claims abstract description 53
- 230000003287 optical effect Effects 0.000 claims abstract description 11
- 229910052760 oxygen Inorganic materials 0.000 claims abstract description 6
- 239000001301 oxygen Substances 0.000 claims abstract description 6
- -1 oxygen ions Chemical class 0.000 claims abstract description 6
- 238000000034 method Methods 0.000 claims description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 20
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 11
- 235000012239 silicon dioxide Nutrition 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 238000005530 etching Methods 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 4
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 4
- 238000005498 polishing Methods 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 238000000059 patterning Methods 0.000 claims description 2
- 238000007517 polishing process Methods 0.000 claims description 2
- 230000010354 integration Effects 0.000 abstract description 4
- 230000005693 optoelectronics Effects 0.000 abstract description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical group [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000005520 cutting process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000006467 substitution reaction Methods 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 1
- 238000002513 implantation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 238000002360 preparation method Methods 0.000 description 1
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Abstract
The invention provides a wafer structure comprising a semiconductor substrate embedded with a plurality of buried oxide layers, wherein the buried oxide layers are breadthwise generated in the semiconductor substrate at intervals. The invention also provides a manufacturing method of the wafer structure, comprising: injecting oxygen ions in the surface of a wafer; generating the buried oxide layers in a semiconductor substrate required to be oxidized; forming the base plate of an electrical appliance by the semiconductor substrate which is not embedded into the buried oxide layers; and forming the base plate of an optical device by the semiconductor substrate which is positioned above the buried oxide layers. The wafer is provided with the base plate capable of manufacturing the electrical appliances, and is integrated with the base plate for manufacturing the optical device so as to realize the integration of integrated optoelectronic elements.
Description
Technical Field
The invention relates to the technical field of semiconductor devices, in particular to a wafer preparation process.
Background
At present, chips are widely used in many modern electronic devices such as liquid crystal display devices, mobile phones, and personal digital assistants due to their high integration level, low power consumption, and small size.
Generally, a chip is obtained by the following manufacturing process: firstly, forming a wafer with a plurality of integrated circuits; then, testing each integrated circuit of the wafer; finally, each integrated circuit is diced from the wafer to produce chips. The existing wafer with a plurality of integrated circuits is mostly used as a substrate of an electric device, and the electric device which utilizes the special electric characteristics of semiconductor materials to complete specific functions can be used as equipment such as a rectifier, an oscillator, an amplifier and the like. The process of fabricating a plurality of integrated circuits on a wafer is well established, but in addition, there is no method of integrating other functions on the same wafer, which limits the development of semiconductors.
Disclosure of Invention
The present invention is made to solve the problem of single function of semiconductor devices on the same wafer, and an object of the present invention is to provide a wafer structure and a method for manufacturing the same, so that the wafer becomes a substrate of a photoelectric integrated device.
The wafer structure related to the invention comprises: a semiconductor substrate having a plurality of buried oxide layers embedded therein, the plurality of buried oxide layers being formed at laterally spaced intervals within the semiconductor substrate.
Preferably, in the wafer structure, the material of the semiconductor substrate is silicon, and the material of the buried oxide layer is silicon dioxide.
Preferably, in the wafer structure, the height of the semiconductor substrate embedded in the buried oxide layer is higher than the height of the semiconductor substrate not embedded in the buried oxide layer.
The invention further relates to a method for manufacturing a wafer structure, comprising the following steps: covering a mask layer on the semiconductor substrate, and then covering a layer of photoresist on the mask; patterning the photoresist, etching the mask layer by taking the patterned photoresist as a mask until the semiconductor substrate is exposed, then injecting oxygen ions into the surface of the wafer, generating a buried oxide layer in the exposed semiconductor substrate, respectively etching the residual photoresist and the mask layer on the semiconductor substrate, removing the photoresist and the mask layer, and finally polishing the surface of the wafer structure.
Preferably, in the method for manufacturing a wafer structure, the material of the mask layer is silicon dioxide or silicon nitride.
Preferably, in the method for manufacturing a wafer structure, a chemical mechanical polishing process is performed on a surface of the wafer structure.
Preferably, in the method for manufacturing a wafer structure, the semiconductor substrate not embedded in the buried oxide layer constitutes a substrate of an electric device, and the semiconductor substrate located above the buried oxide layer constitutes a substrate of an optical device. The buried oxide layer serves as an isolation layer between the substrates of the optical device.
According to the wafer structure, the wafer is provided with the substrate for manufacturing the electric device and the substrate for manufacturing the optical device, so that the integration of the photoelectric integrated element is realized.
According to the manufacturing method of the wafer structure, in the manufacturing process of the wafer, the semiconductor substrate positioned on the buried oxide layer and the semiconductor substrate not embedded in the buried oxide layer are combined into a unit and distributed on the wafer, the process is simple and efficient to manufacture, and the later cutting process is facilitated.
Drawings
The various aspects of the present invention will become more apparent after reading the detailed description of the invention with reference to the attached drawings. Wherein,
FIG. 1a is a schematic top view of a wafer structure;
FIG. 1b is a schematic cross-sectional view of a wafer structure;
FIG. 2a is a first step of a process schematic of a wafer structure fabrication method;
FIG. 2b is a second step of the process of the wafer structure manufacturing method;
FIG. 2c is a third step of the process schematic of the wafer structure fabrication method;
FIG. 2d is a fourth step of the process schematic of the wafer structure manufacturing method; and
fig. 2e is a fifth step of the process of the wafer structure manufacturing method.
Detailed Description
Embodiments of the present invention will be described in further detail below with reference to the accompanying drawings. Like reference numerals refer to like parts throughout the description.
According to the wafer structure and the manufacturing method of the wafer structure, the wafer is provided with the substrate capable of manufacturing the electric device and the substrate capable of manufacturing the optical device, and integration of the photoelectric integrated element is realized. In the manufacturing process of the wafer, the semiconductor substrate positioned on the buried oxide layer and the semiconductor substrate not embedded with the buried oxide layer are combined and distributed on the wafer, the process is simple and efficient, and the later cutting process is facilitated.
FIG. 1a is a schematic top view of a wafer structure. FIG. 1b is a cross-sectional view of a wafer structure. Referring to fig. 1a and 1b, a wafer 100 includes: a semiconductor substrate 101 embedded with a plurality of buried oxide layers 102, the plurality of buried oxide layers 102 being grown laterally spaced apart within the semiconductor substrate 101, the wafer 100 being a substrate for an optoelectronic integrated device. The material of the semiconductor substrate 101 is silicon and the material of the buried oxide layer 102 is silicon dioxide. The semiconductor substrate 101 not embedded in the buried oxide layer 102 constitutes the base plate of the electrical device, and the semiconductor substrate 101 located above the buried oxide layer 102 constitutes the base plate of the optical device. The buried oxide layer 102 serves as an isolation layer between the substrates of the optical device. The semiconductor substrate 101 not embedded in the buried oxide layer 102 and the semiconductor substrate 101 located above the buried oxide layer 102 constitute a base plate of the optoelectronic integrated device.
FIG. 2a is a first step of a process schematic of a wafer structure manufacturing method. Referring to fig. 2a, a mask layer 201 is covered on a semiconductor substrate 101, and the mask material of the mask layer 201 is silicon dioxide or silicon nitride, and it should be understood by those skilled in the art that the mask material is not limited to silicon dioxide or silicon nitride, but may also be a mask material commonly used in other integrated circuit processes; FIG. 2b is a second step of the process of the wafer structure manufacturing method. Referring to fig. 2b, a layer of photoresist 202 is covered on the mask layer 201. FIG. 2c is a third step of the process schematic of the wafer structure fabrication method. Referring to fig. 2c, a mask is used to define an area to be oxidized on the photoresist 202 and expose the area to light to remove the photoresist 202, so as to pattern the photoresist 202, and the patterned photoresist 202 is used as a mask to etch and remove the mask layer 201, so that the semiconductor substrate 101 in the area is exposed to the environment, and the photoresist 202 and a part of the mask layer 201 remain in the area not to be oxidized. Fig. 2d and fig. 2e are the fourth and fifth steps of the manufacturing method of the wafer structure. Referring to fig. 2d and 2e, oxygen ions 203 are implanted into the surface of the wafer 100, and after a heat treatment, the oxygen ions 203 react with silicon atoms of the semiconductor substrate 101 exposed to the environment to generate a plurality of buried oxide layers 102 spaced from each other inside the semiconductor substrate 101, the photoresist 202 and the mask layer 201 remain in regions not required to be oxidized to block the implantation of the oxygen ions 203 into the semiconductor substrate 101, no oxide is generated inside the semiconductor substrate 101 covered by the mask layer 201 and the photoresist 202, and the height of the semiconductor substrate 101 embedded in the buried oxide layers 102 is higher than the height of the semiconductor substrate 101 not embedded in the buried oxide layers 102. And respectively etching the residual photoresist 202 and the mask layer 201 on the semiconductor substrate 101, removing the photoresist 202 and the mask layer 201, and finally performing chemical mechanical polishing treatment on the surface of the structure of the wafer 100. The semiconductor substrate 101 not embedded in the buried oxide layer 102 constitutes the base plate of the electrical device, the semiconductor substrate 101 located above the buried oxide layer 102 constitutes the base plate of the optical device, and the buried oxide layer 102 serves as an isolation layer between the base plates of the optical device. The optoelectronic integrated components are integrated on one wafer 100.
Hereinbefore, specific embodiments of the present invention are described with reference to the drawings. However, those skilled in the art will appreciate that various modifications and substitutions can be made to the specific embodiments of the present invention without departing from the spirit and scope of the invention. Such modifications and substitutions are intended to be included within the scope of the present invention as defined by the appended claims.
Claims (9)
1. A wafer structure, comprising: a semiconductor substrate embedded with a plurality of buried oxide layers grown laterally spaced apart within the semiconductor substrate.
2. The wafer structure of claim 1, wherein the material of the semiconductor substrate is silicon.
3. The wafer structure of claim 1, wherein the material of the buried oxide layer is silicon dioxide.
4. The method of claim 1, wherein the semiconductor substrate embedded in the buried oxide layer has a height greater than a height of the semiconductor substrate not embedded in the buried oxide layer.
5. A method of fabricating a wafer structure, comprising:
a. covering a mask layer on the semiconductor substrate;
b. covering a layer of photoresist on the mask;
c. patterning the photoresist;
d. etching the mask layer by taking the patterned photoresist as a mask until the semiconductor substrate is exposed;
e. implanting oxygen ions into the surface of the wafer to generate a buried oxide layer in the exposed semiconductor substrate;
f. etching the residual photoresist and the mask layer on the semiconductor substrate respectively to remove the photoresist and the mask layer; and
g. and polishing the surface of the wafer structure.
6. The method as claimed in claim 5, wherein the mask layer is made of silicon dioxide or silicon nitride.
7. The method as claimed in claim 5, wherein the surface of the wafer structure is subjected to a chemical mechanical polishing process.
8. A method of fabricating a wafer structure according to claim 5 wherein the semiconductor substrate not embedded in the buried oxide layer constitutes a base plate of an electrical device.
9. The method of claim 5, wherein the semiconductor substrate on the buried oxide layer forms a base plate of an optical device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102357212A CN101958317A (en) | 2010-07-23 | 2010-07-23 | Wafer structure and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2010102357212A CN101958317A (en) | 2010-07-23 | 2010-07-23 | Wafer structure and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN101958317A true CN101958317A (en) | 2011-01-26 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2010102357212A Pending CN101958317A (en) | 2010-07-23 | 2010-07-23 | Wafer structure and manufacturing method thereof |
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH11297703A (en) * | 1998-04-15 | 1999-10-29 | Fuji Electric Co Ltd | Fabrication of semiconductor device |
| US6222253B1 (en) * | 1997-03-05 | 2001-04-24 | International Business Machines Corporation | Buried oxide layer in silicon |
| JP2002305294A (en) * | 2002-02-15 | 2002-10-18 | Seiko Instruments Inc | Semiconductor substrate and method of manufacturing the same |
| CN1748312A (en) * | 2003-02-19 | 2006-03-15 | 信越半导体股份有限公司 | Method for manufacturing soi wafer and soi wafer |
| CN1819218A (en) * | 2005-01-11 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device and manufacturing method thereof |
| JP2008091935A (en) * | 2007-11-02 | 2008-04-17 | Seiko Instruments Inc | Integrated circuit |
| CN101566705A (en) * | 2009-06-12 | 2009-10-28 | Nano科技(北京)有限公司 | Optoelectronic integrated circuit and substrate preparation method |
-
2010
- 2010-07-23 CN CN2010102357212A patent/CN101958317A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6222253B1 (en) * | 1997-03-05 | 2001-04-24 | International Business Machines Corporation | Buried oxide layer in silicon |
| JPH11297703A (en) * | 1998-04-15 | 1999-10-29 | Fuji Electric Co Ltd | Fabrication of semiconductor device |
| JP2002305294A (en) * | 2002-02-15 | 2002-10-18 | Seiko Instruments Inc | Semiconductor substrate and method of manufacturing the same |
| CN1748312A (en) * | 2003-02-19 | 2006-03-15 | 信越半导体股份有限公司 | Method for manufacturing soi wafer and soi wafer |
| CN1819218A (en) * | 2005-01-11 | 2006-08-16 | 恩益禧电子股份有限公司 | Semiconductor device and manufacturing method thereof |
| JP2008091935A (en) * | 2007-11-02 | 2008-04-17 | Seiko Instruments Inc | Integrated circuit |
| CN101566705A (en) * | 2009-06-12 | 2009-10-28 | Nano科技(北京)有限公司 | Optoelectronic integrated circuit and substrate preparation method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HONGLI SEMICONDUCTOR MANUFACTURE CO LTD, SHANGHAI Effective date: 20140514 |
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Effective date of registration: 20140514 Address after: 201203 Shanghai Zhangjiang hi tech park Zuchongzhi Road No. 1399 Applicant after: Shanghai Huahong Grace Semiconductor Manufacturing Corporation Address before: 201203 Shanghai Guo Shou Jing Road, Zhangjiang hi tech Park No. 818 Applicant before: Hongli Semiconductor Manufacture Co., Ltd., Shanghai |
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Application publication date: 20110126 |