JP2002305294A - Semiconductor substrate and method of manufacturing the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor substrate which suppresses defects of temperature rise generated in an SOI wafer, and which forms an integrated circuit of high reliability. SOLUTION: Insulators 13 are buried locally in a single-crystal silicon substrate 11.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor silicon is SOI on an electric insulating film.
(Silicon On Insnlator), which has recently attracted attention as a semiconductor device capable of high speed and high integration. FIG. 2 shows a sectional view of the structure of the SOI wafer substrate. Reference numeral 21 denotes a single crystal silicon substrate having a thickness of 500 to 1000 μm, 22 denotes a silicon oxide film (BOX: Baried Oxide) which is an electric insulator having a thickness of several hundreds to several μm, and 23 denotes a silicon oxide film of several hundreds to several μm. The silicon oxide film 23, which is an electrical insulator, is a single crystal silicon having a thickness of about several hundreds to several micrometers.

[0005] A semiconductor integrated circuit formed on an SOI wafer has a single crystal silicon layer (SOI layer) on an electric insulating film 22.
23 is very thin, especially when the integrated circuit is a complementary MIS.
In the case of a transistor (complementary metal / insulator transistor), the electric capacity between the source and the substrate, between the drain and the substrate, and between the gate and the substrate is reduced, and the speed of the integrated circuit can be increased. Compared to the case where an integrated circuit is formed on a silicon wafer, the presence of the electric insulator 22 allows the transistor to have a very small element isolation region between the transistors, and has the advantage that high integration is possible. Have.

[0004]

Although the SOI wafer has the above-mentioned excellent characteristics, the integrated circuit does not operate because the insulating film 22 exists immediately below the thin single crystal silicon on which the integrated circuit is formed. The heat generated by the current flowing during the operation does not escape to the thick semiconductive single-crystal silicon substrate under the insulating film 22, and the heat is accumulated in the thin single-crystal silicon layer 23, and The temperature of the crystalline silicon layer rises over time.

When an integrated circuit is formed by complementary MIS transistors, if the transistor size is reduced for higher integration, the current flowing in the transistor increases, and the degree of temperature rise also increases. When the temperature rises in the thin single-crystal silicon layer, a large number of carrier trap levels easily occur in the gate insulating film of the MIS transistor, which causes fluctuations in transistor characteristics and further impairs the reliability of the integrated circuit. Become.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor substrate capable of forming a highly reliable integrated circuit while suppressing the above-mentioned drawback of a rise in temperature of an SOI wafer.

[0007]

An insulating film is locally formed in a single crystal silicon substrate in order to release heat accumulated in a thin single crystal silicon layer (SOI layer). That is, a thin single crystal silicon layer over an insulating film is locally formed in a single crystal silicon substrate.

When an integrated circuit is formed on the semiconductor substrate of the present invention having the above-described structure, not only heat generated in the integrated circuit formed on the single crystal silicon in the region where the insulating film is not formed, but also the heat generated by the integrated circuit. The heat is diffused into single-crystal silicon having good thermal conductivity under the integrated circuit. In addition, heat generated in the integrated circuit formed in the single crystal silicon layer over the insulating film is transmitted to an end of the insulating film and then dissipated into thick single crystal silicon in a region where the insulating film is not formed. .

[0009]

1 (a) and 1 (b) show an embodiment of the present invention. FIG. 1A is a plan view of a semiconductor substrate of the present invention, and FIG. 1B is a cross-sectional structural view taken along a line AA ′ in FIG. 1A. 11 is a single crystal silicon substrate,
Reference numeral 12 denotes an insulating film such as a silicon oxide film embedded in a single crystal silicon substrate, and reference numeral 13 denotes a single crystal silicon layer on the insulating film 12, that is, an SOI layer. Reference numeral 14 denotes a cutting line cut to indicate a certain orientation of the single crystal silicon.
The insulating film 12 has a thickness of, for example, several hundreds of μm to several μm, and similarly, the thin single-crystal silicon layer 13 has a thickness of several hundreds of μm to several μm.

FIG. 3 shows an example of a semiconductor device formed using the semiconductor substrate of the present invention shown in FIG. Reference numeral 31 denotes a single-crystal silicon substrate; 32, a silicon oxide film which is an insulator having a thickness of several hundreds of μm to several μm embedded in the single-crystal silicon substrate 31; Is a thin single crystal silicon layer, that is, an SOI layer.

Reference numeral 34 denotes a circuit 1 formed on the left side of the single-crystal silicon substrate 31 and in a region where the insulator is not embedded.
36 is a circuit 3 formed on the right side of the single crystal silicon substrate and in a region where the insulating film is not buried, and 35 is a circuit 2 formed on a thin single crystal silicon layer on the insulating film 32, respectively. ing. The circuits 34, 35, and 36 are electrically connected to each other to form one integrated circuit having a certain function.

There is no insulating film under the circuits 1 of 34 and the circuit 3 of 36, and the heat generated by the operation of those circuits is several hundreds of thickness below the circuits 3 of 34 and 1 of 36. It escapes to a thick semiconductive single crystal silicon substrate 31 of μm or more. For this reason, when the temperature rises, the MIS
No carrier trap level is generated in the gate insulating film of the transistor, and the transistors forming the circuits 1 and 36 have high reliability and a stable circuit.

On the other hand, the 35 circuit 2 formed on the thin single-crystal silicon layer above the insulating film 32, that is, the SOI layer 33 is a circuit that requires particularly high speed. The reason why the integrated circuit including the MIS transistor formed in the SOI layer 33 has high speed will be described with reference to FIG.

By the operation of the circuit 2, the heat generated in the SOI layer 33 proceeds to the upper portions 37 and 381 at both ends of the insulating film 32, and is radiated from there to the entire thick single-crystal silicon substrate 31, and the SOI layer 33 It doesn't stop there. Therefore, the temperature of the SOI layer 33 does not rise during the operation of the circuit 2 and no carrier trap level is generated in the gate insulating film of the MIS transistor group forming the circuit 2. As a result, the reliability of the transistor group is high, and the circuit 2 operates stably without variation over time.

FIG. 4 is a sectional structural view of an N-type MIS transistor. The reason why an integrated circuit including MIS transistors formed in an SOI layer has high speed will be briefly described with reference to FIGS. 41 is a single crystal silicon substrate,
42 is an insulating film such as a silicon oxide film, 43 is a P well made of a P-type impurity having a low concentration, for example, about 1 × 10 16 cm −3, 44 is a gate insulating film, 45 is a high concentration, for example,
A gate made of polycrystalline silicon containing an N-type impurity of × 10 20 cm −3, and 46 and 47 are a source and a drain made of an N-type impurity of a high concentration, for example, about 1 × 10 20 cm −3. The N-type MIS transistor is a P-well 4
3, a gate insulating film 44, a gate 45, a source 46, and a drain 47. Reference numeral 48 denotes a field oxide film made of a thick silicon oxide film for element isolation.

The thickness of the single crystal silicon of the P well 43 is, for example, about 0.6 μm. When operating the N-type MIS transistor, for example, the potential of the source is set to 0 V, and the gate and the drain are set to 5 V. At this time, a depletion layer extends under the gate, source, and drain. Broken lines 49, 4
Reference numerals 10 and 411 indicate boundaries of the depletion layer. The depletion layer is a region of high resistance without mobile carriers. The depletion layer is broken line 4
9, the left side of 410 and the upper side of 411.

For example, the depth of the source and the drain is set to 0.
If the thickness is 3 μm, a depletion layer of about 0.9 μm spreads below the drain and about 0.3 μm spreads below the source, so that the depletion layer contacts the insulating film 42 below the drain as well as below the source. I do. Therefore, the source substrate (P well 4)
The capacitance between 3) and between the drain and the substrate (P well 43) includes the insulating film 42 and has a very small value. As a result, these parasitic capacitances are reduced, and the integrated circuit including the MIS transistors formed in the SOI layer has high speed.

FIG. 5 shows another embodiment of the present invention. FIG.
The embodiment of the present invention shown in FIG. 7 has many points in common with the embodiment of the present invention shown in FIG. Therefore, in FIG. 5, description of the names of the portions 31 to 38 common to FIG. 3 is omitted. In FIG. 5, a part of single-crystal silicon under a silicon oxide film 32 which is an insulating film embedded in a part of a single-crystal silicon substrate 31 is removed. Reference numerals 51 and 52 denote silicon nitride films, which serve as masks for removing single crystal silicon under the silicon oxide film 32. When removing single-crystal silicon, the single-crystal silicon substrate may be immersed in a potassium hydroxide solution (KOH solution) heated to, for example, 80 ° C. to 100 ° C. The silicon oxide film 32 serves as an etching stopper when the single crystal silicon under the silicon oxide film 32 is removed by etching with a KOH solution, and the thin single crystal silicon film 33 on the silicon oxide film 32 is etched. Also play a role in preventing After removing the single crystal silicon under the silicon oxide film 32, the silicon nitride films 51 and 52 may or may not be removed.

A method of manufacturing the semiconductor substrate of the present invention shown in FIG. 1 will be described with reference to FIGS. 6A to 6D are process cross-sectional views illustrating a manufacturing method for forming a semiconductor substrate according to the present invention.

In FIG. 6A, reference numeral 61 denotes single crystal silicon, and 62 denotes a photoresist having a thickness of several μm applied on the entire surface of the single crystal silicon 61. In FIG. 6B, oxygen is converted to single crystal silicon 6 by a photolithography process.
The photoresist at the location where the ion is to be implanted in 1 is removed. Reference numeral 63 denotes a photoresist remaining after the photolithography process. In FIG. 6C, reference numeral 64 denotes oxygen ions implanted into single crystal silicon. The acceleration energy at the time of implanting oxygen ions depends on the depth of the silicon oxide film formed under the SOI layer from the surface of the SOI layer. The amount of oxygen ions at the time of ion implantation is about 1.times.10@18 cm @ -2. FIG.
In (d), the photoresist film 63 is removed. Thereafter, when a heat step of 900 ° C. or more is applied, single-crystal silicon and the implanted oxygen atoms react with each other, and a good silicon oxide film 65 is formed. However, the silicon oxide film 6
5 has a good thin single crystal silicon layer 66, ie, SOI
A layer will be formed.

In FIG. 6, when oxygen ions are implanted,
Selection of a portion to be implanted was performed by removing only a desired portion of the photoresist film 62 applied on the single crystal silicon 61. However, in the method for manufacturing a semiconductor substrate of the present invention, as a method for selecting a position to be ion-implanted,
Photoresist film 6 applied on single crystal silicon 61
The method is not limited to the method of removing the desired portion 2 only.

FIGS. 7A to 7D are process sectional views showing another embodiment of a manufacturing method for forming a semiconductor substrate according to the present invention. In FIG. 7A, reference numeral 71 denotes single-crystal silicon; 72, a silicon oxide film obtained by thermally oxidizing the single-crystal silicon 71 to a thickness of several thousand to several μm;
Denotes a photoresist film applied on the silicon oxide film 72.

In FIG. 7B, the photoresist and the silicon oxide film at the portion where oxygen is to be ion-implanted into the single crystal silicon 61 are removed by a photolithography process. 7
Reference numerals 4 and 75 denote a photoresist and a silicon oxide film left by the photolithography process, respectively.

In FIG. 7C, reference numeral 76 denotes oxygen ions implanted into single crystal silicon. The acceleration energy at the time of implanting oxygen ions depends on the depth of the silicon oxide film formed under the SOI layer from the surface of the SOI layer. The amount of oxygen ions at the time of ion implantation is about 1.times.10@18 cm @ -2.

In FIG. 7D, after the ion implantation of oxygen ions, the photoresist film 74 and the silicon oxide film 75 are removed, so that the entire surface becomes a single crystal silicon layer having a flat surface. Thereafter, when a heat step of 900 ° C. or more is applied, single-crystal silicon and the implanted oxygen atoms react with each other, and a good silicon oxide film 77 is formed. Moreover,
An excellent thin single crystal silicon layer 78, that is, an SOI layer is formed on the silicon oxide film 77.

In FIG. 7, a silicon oxide film 72 and a photoresist film 73 are used to form an implantation window when oxygen ions are implanted, but another insulating film, for example, is deposited instead of the silicon oxide film 72. Even if a silicon nitride film or the like is used, and a photoresist film 73 is used thereon, it cannot be avoided.

Although the silicon oxide film is used as the insulating film below the SOI layer in the embodiments shown in FIGS. 6 and 7, another insulating film, for example, a silicon nitride film may be used. That is, in the embodiment of the present invention shown in FIGS. 6 and 7, oxygen ions are ion-implanted, but nitrogen ions are ion-implanted and then annealed, so that the silicon nitride film has a desired depth from the silicon surface. May be formed.

FIGS. 8A to 8D and FIGS. 9E to 9G.
Another embodiment of the manufacturing method for forming a semiconductor substrate according to the present invention will be described with reference to the process sectional views of FIGS. 8A, reference numeral 81 denotes single-crystal silicon; 82, a silicon oxide film obtained by thermally oxidizing the single-crystal silicon 81 to a thickness of several hundred Å; 83, a deposited silicon having a thickness of 1000 to 2,000 Å; Nitride film, 8
Reference numeral 4 denotes a photoresist film applied on the silicon nitride film 83.

In FIG. 8B, a window 85 is opened at a desired position of the photoresist by a photolithography process. In FIG. 8C, the silicon nitride film 83 where the window of the photoresist film is opened is removed.

In FIG. 8D, the photoresist film remaining on the silicon nitride film is removed and thermally oxidized to form a silicon oxide film 86 having a thickness of several thousand to several μm. In FIG. 9E, the remaining silicon nitride film is removed.

In FIG. 9F, a silicon oxide film 82
A photoresist film 87 is deposited on the entire surface of the substrate 86. In FIG. 9G, all of the thin silicon oxide film 82 and the deposited photoresist film 87 and the thick silicon oxide film 8 are formed.
Part 6 is etched by dry etching or the like.
As a result, a silicon oxide film 88 whose surface is flush with the surface of the single crystal silicon is newly formed at a plurality of desired positions in the single crystal silicon substrate.

Here, the single crystal silicon substrate used in the steps of FIGS. 8A to 9G is referred to as an A substrate. FIG.
0 (h), a new single crystal silicon substrate 89 (B
Substrate).

In FIG. 10 (i), 1100 to 120
The A and B substrates are bonded together in a high-temperature oxygen atmosphere at 0 ° C. with the silicon oxide film 88 inside. A silicon oxide film 810 is formed around the A substrate and the B substrate. FIG.
In (j), the single crystal silicon on the A substrate side is polished and polished so that the desired thickness of the single crystal silicon left on the silicon oxide film 88 is left. As a result, a single crystal silicon substrate of the present invention as shown in FIG. 1B in which the silicon oxide film 88 is embedded in the single crystal silicon is completed. The silicon oxide film 810 around the single crystal silicon substrate may or may not be removed.

The method of manufacturing a semiconductor substrate according to the present invention shown in the sectional views of FIGS. 8A to 10J uses a so-called bonding method of bonding two single crystal silicon substrates. is there. 8 (a) to 10 (j)
Examples of the present invention shown in is a typical example,
It is not always necessary to do so.

That is, in FIG. 8A, the silicon oxide film 82 is not always necessary. In FIG. 9F, a photoresist 8 is formed on the entire surface of the single crystal silicon substrate 81.
7 is applied, but the coating is not necessarily limited to a photoresist. A silicon oxide film, a silicon nitride film, and a silicon oxide film (commonly referred to as SOG: SPIN ON GL
ASS) or an insulating film such as polyimide. By applying some kind of insulating film to make the surface of the insulating film flat and obtaining an etching condition capable of obtaining an etching rate substantially equal to that of the silicon oxide film 86, the surface of the single crystal silicon substrate is etched by the subsequent etching. It can be formed flat as shown in FIG.

FIGS. 11 (a) to 11 (d) and FIGS.
Another embodiment of the manufacturing method for forming a semiconductor substrate of the present invention will be described with reference to (g) and the process sectional views of FIGS. 13 (h) to 13 (i). In FIG. 11A, 1101
Denotes a single crystal silicon substrate and 1102 denotes a photoresist film applied on the single crystal silicon substrate 1101.

In FIG. 11B, a window 1103 is opened at a desired position of the photoresist by a photolithography process. A silicon oxide film is buried under the window 1103 in a final step. Reference numeral 1104 denotes a photoresist remaining after the photolithography process.

In FIG. 11 (c), the single crystal silicon at the location where the window of the photoresist film is opened is etched to a desired depth by dry etching or the like. Reference numeral 1105 denotes a recess etched by single crystal silicon. The remaining photoresist 1104 is removed.

In FIG. 11D, a silicon oxide film 1106 having a thickness of several thousand to several μm is formed by thermal oxidation. In FIG. 12E, the silicon oxide film 11
A photoresist film 1107 is applied over the entire surface of the substrate 06.

In FIG. 12F, the photoresist film 1107 is subjected to dry etching or the like until a silicon oxide film on the bottom surface 1108 of the single crystal silicon at a location etched to a desired depth in FIG. Etching (usually called etch back). As a result, silicon oxide films 1109 are formed at a plurality of desired positions on the surface of single crystal silicon substrate 1101.

Here, the single crystal silicon substrate used in the steps of FIGS. 11A to 12F is referred to as an A substrate.
In FIG. 12 (g), a new single crystal silicon substrate (B
1110).

In FIG. 13 (h), 1100 to 120
The A and B substrates are bonded together in a high-temperature oxygen atmosphere at 0 ° C. with the silicon oxide film 1109 inside. A silicon oxide film 1111 is formed around the A substrate and the B substrate. FIG.
In 3 (i), the single crystal silicon on the A substrate side is polished and polished so that the single crystal silicon left on the silicon oxide film 1109 has a desired thickness. As a result, the silicon oxide film 1109 is formed on the single crystal silicon substrate 11.
12 and a thin single-crystal silicon layer 1113 formed on the silicon oxide film 1109 at a plurality of desired locations in the silicon substrate, as shown in FIG. Is completed. Silicon oxide film 1 formed around single crystal silicon substrate 1112
111 may or may not be removed.

The method of manufacturing a semiconductor substrate according to the present invention shown in the process sectional views of FIGS. 11A to 12I uses a so-called bonding method of bonding two single-crystal silicon substrates. is there. FIGS. 11A to 12
The embodiment of the present invention shown in (i) is one typical example, and is not necessarily limited to this.

That is, in FIG. 11D, the silicon oxide film 1106 formed by thermally oxidizing the single crystal silicon substrate does not necessarily need to be a silicon oxide film. Instead of the silicon oxide film, a silicon nitride film may be deposited. In this case, 11 in FIG.
09 becomes a silicon nitride film.

In FIG. 12E, a photoresist film 1107 is deposited on the entire surface of the single-crystal silicon substrate 1101. However, the photoresist film 1107 is not necessarily limited to the photoresist film, but may be a silicon oxide film formed by chemical vapor deposition. Film, silicon nitride film, silicon oxide film formed by applying and heat-treating at a temperature of about 400 ° C. (commonly called SOG: SPIN ON)
GLASS) or an insulating film such as polyimide. By forming an insulating film on the surface of the silicon substrate to obtain an etching condition that makes the surface of the insulating film flat and obtains an etching rate substantially equal to that of the silicon oxide film 1106, the single-crystal silicon The surface of the substrate can be formed flat as shown in FIG.

[0046]

As described above in detail, when a semiconductor substrate of the present invention has an integrated circuit formed thereon, the integrated circuit formed on the single crystal silicon in a region where the insulating film is not formed is formed. In addition to the heat generated in the above, it is dissipated to single-crystal silicon with good thermal conductivity spreading under the integrated circuit,
In addition, heat generated in the integrated circuit formed in the single crystal silicon layer over the insulating film is transmitted to the edge of the insulating film, and then dissipated into thick single crystal silicon in a region where the insulating film is not formed. The reliability of the integrated circuit does not decrease due to an increase in heat, and good characteristics are maintained.

In the method of the present invention for manufacturing a semiconductor substrate in which an insulating film is partially embedded in a semiconductor substrate, a semiconductor substrate having a flat surface can be obtained by either the ion implantation method or the bonding method. Have excellent advantages.

[Brief description of the drawings]

FIG. 1A is a plan view of a semiconductor substrate of the present invention, and FIG.
FIG. 1 is a cross-sectional view of a semiconductor substrate of the present invention.

FIG. 2 is a structural sectional view of an SOI wafer.

FIG. 3 is a structural sectional view of a semiconductor device formed using a semiconductor substrate of the present invention.

FIG. 4 is a structural sectional view of an N-type MIS transistor.

FIG. 5 is a structural sectional view of a semiconductor device formed using the semiconductor substrate of the present invention.

FIGS. 6A to 6D are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor substrate according to the present invention.

FIGS. 7A to 7D are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor substrate according to the present invention.

FIGS. 8A to 8D are cross-sectional views in the order of steps showing a method for manufacturing a semiconductor substrate according to the present invention.

9 (e) to 9 (g) are cross-sectional views in the order of steps showing the method for manufacturing a semiconductor substrate of the present invention.

10 (h) to 10 (j) are cross-sectional views in the order of steps showing the method for manufacturing a semiconductor substrate according to the present invention.

FIGS. 11A to 11D are cross-sectional views illustrating a method of manufacturing a semiconductor substrate according to the present invention in the order of steps.

FIGS. 12E to 12G are cross-sectional views in the order of steps showing the method for manufacturing a semiconductor substrate according to the present invention.

13 (h) to 13 (i) are cross-sectional views in the order of steps showing the method for manufacturing a semiconductor substrate according to the present invention.

[Explanation of symbols]

11, 31, 61, 81 Single-crystal silicon substrate 22 Silicon oxide film BOX 12, 32, 65, 88 Buried insulating film 64, 76 Oxygen ion 87, 1107 Photoresist 13, 33, 66, 1113 Thin single crystal on insulating film Silicon layer

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI theme coat ゛ (Reference) H01L 27/08 331 H01L 29/78 613Z 27/088 21/76 D 29/786 (72) Inventor Hiroaki Takasu 1-8, Nakase, Nakase, Mihama-ku, Chiba-shi, Chiba Prefecture Atsuko Sakurai Inventor Atsushi Sakurai 1-8-8, Nakase, Mihama-ku, Chiba-shi, Chiba F-term in Seiko Instruments Inc. 5F032 AA06 AA07 AA13 CA17 DA23 DA53 DA60 DA71 DA74 5F048 AC01 AC03 BA09 BA16 BC11 BG12 5F110 AA23 BB04 CC02 DD05 DD13 DD21 EE09 GG02 GG12 GG24 NN62 QQ17

Claims (2)

[Claims] A semiconductor substrate in which a silicon oxide film is formed in a region locally planar and buried away from the front surface and the back surface; and a semiconductor substrate surface on the buried silicon oxide film. A first circuit composed of a formed MIS transistor requiring high-speed operation, and a second circuit composed of a complementary MIS transistor formed on the surface of the semiconductor substrate in which the silicon oxide film is not embedded. An integrated circuit, comprising: two circuits. 2. A removing portion for exposing said silicon oxide film is formed in a semiconductor substrate between said silicon oxide film in which said semiconductor substrate is buried and a back side of said semiconductor substrate. Integrated circuit.