JP2002094032A - Semiconductor substrate and its manufacturing method, and semiconductor device using the substrate and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a semiconductor device, having superior gate breakdown voltage and capable of being manufactured in a high non-defective rate and an SOI substrate capable of forming its semiconductor device. SOLUTION: The SOI substrate comprises a CZ base 1, and a semiconductor layer region 3 made of an FZ single-crystal which is laminated on the base 1 and laminated via an oxide film 2. A MOS device is formed on the SOI substrate to provide superior gate breakdown voltage and to enhance non-defective rate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a semiconductor layer region made of a FZ crystal bonded to a CZ substrate via an insulating film, using a CZ substrate as a supporting substrate.
A semiconductor substrate that is an I-substrate and a method of manufacturing the substrate;
The present invention relates to a semiconductor device manufactured using the SOI substrate and a method for manufacturing the same.

[0002]

2. Description of the Related Art SOI (Sil) having a buried oxide film
When a semiconductor integrated circuit (LSI) is manufactured on an icon on insulator (IC) substrate, all the LSI elements formed on the surface layer of the SOI substrate have a structure completely separated by a dielectric (side and bottom surfaces of the element with a dielectric). ), The short channel effect accompanying high integration is suppressed, and low power consumption operation can be performed. For that purpose, SOI substrates are next-generation LS
It is expected as a semiconductor substrate for forming a highly integrated and highly functional semiconductor device such as I.

[0003] This SOI substrate has a single crystal silicon layer formed on an insulator such as an oxide film.
OX (Separation by Implant)
dOxygen) wafers and bonded SOI wafers are mainly known. In the SIMOX wafer, oxygen ions are introduced into the single crystal silicon substrate by ion implantation, and the oxygen ions and silicon atoms are chemically reacted by a subsequent annealing treatment to form a buried oxide film.

On the other hand, a bonded SOI wafer is an SOI substrate obtained by bonding two single-crystal silicon wafers with an oxide film interposed therebetween and thinning one of the two wafers. In the former SIMOX wafer, the thickness of the single crystal silicon layer, which is a thin film layer, is limited to several hundred nm due to the depth of introduction of oxygen ions, whereas in the latter bonded SOI wafer, the thickness of the single crystal silicon wafer is thick. And the thickness of the silicon single crystal layer, which is a thin film layer, can be set to several μm to several tens μm.

[0005] However, a bonded SOI wafer requires a heat treatment step for securing the mechanical strength of the bonded portion. That is, in a normal SOI wafer manufacturing process, after two CZ wafers manufactured by the CZ (Czochralski) method are bonded together, 1000 ° C.
In order to heat-treat at the above high temperature, and then to form a silicon single crystal layer as a thin film layer, a step of grinding and polishing one side of the CZ wafer is required.

In the heat treatment step after the bonding,
COP (Crystal O) originally present on CZ wafers
The inner wall of the “registered particle” is oxidized (the oxide film thickness is about 4 nm), and the COP grows and becomes large. After this heat treatment step, the CZ wafer on which the LSI elements and the like are to be formed is thinned and the bonded SO
An I-wafer is obtained, and the COP9 is placed on the surface of a silicon single crystal layer (semiconductor layer region 93) which is a thin film layer.
4 are exposed and micro holes 95 whose surface is oxidized are scattered (FIG. 27).

In FIG. 27, reference numeral 91 denotes a CZ base material, 9
2 is a bonded oxide film, 93 is a semiconductor layer region obtained by grinding and polishing a CZ base material, and 200 is a CZ-CZ-SOI substrate. Further, the COP 94 shown in a circular shape in the figure is a hollow defect having an octahedral structure of 100 nm to 200 nm in substance, and when this defect is exposed on the surface, as shown in an enlarged view, the cross-sectional shape of the hollow is triangular or multiple. It becomes square.

[0008]

As a result, when an LSI device such as a C-MOS shown in FIG. 28 is manufactured using a bonded SOI wafer, the gate oxide films 232 and 23 are formed.
The thickness of the gate oxide films 232 and 233 decreases due to the thickness of the gate oxide films 232 and 233 due to the presence of the minute holes 95.

Here, the structure of the C-MOS shown in FIG. 28 will be described. The n-type well region 2 is formed in the p-type semiconductor layer region 93.
31 and an n-channel MOSFET (N-MOSFET) are formed in the n-type well region 231.
An ET (P-MOSFET) is formed to complete a C-MOS. In the figure, 95 is a LOCOS oxide film, 232, 2
33 is a gate oxide film, 234 and 235 are gate electrodes, 2
37 and 238 are a p source region, a p drain region, and 239
Is a p ⁺ region, 240 and 241 are n source regions, n drain regions, 244 and 245 are source and drain electrodes of a P-MOSFET, and 247 and 248 are N-MOSFETs.
, 250 and 250 are metal electrodes.

In order to prevent a decrease in the breakdown voltage of the gate oxide film, an FZ (Floating) which is not affected by the COP is used.
Using a bonded SOI wafer (FIG. 29) manufactured from an FZ wafer manufactured by the Zone method,
The mechanical strength of the SOI wafer is reduced. In the figure, 97 is an FZ base material, 98 is an oxide film, 99 is a semiconductor layer region of FZ, and 300 is an FZ-FZ-SOI substrate.

[0011] This mechanical strength depends on the concentration of impurity oxygen present in the silicon crystal. Usually, the CZ wafer is
Owing to its manufacturing method, oxygen is inevitably contained on the order of 10 ¹⁸ atoms / cm ³ . In contrast, FZ
Since the impurity oxygen concentration in the wafer is 10 ¹⁶ / cm ³ or less, the FZ wafer is more fragile than the CZ wafer.

Therefore, when an FZ wafer is used in the heat treatment step after the bonding, the wafer may be warped or cracked. In this heat treatment step, if the heat treatment temperature is lowered, cracking or the like does not occur, but the problem of wafer warpage remains and the mechanical strength also decreases. In the manufacture of an IC device including a complicated and multi-step process, defocusing due to warpage cannot be ignored in lithography in a photo process, and a reduction in non-defective products and poor device characteristics are likely to occur.

An object of the present invention is to solve the above-mentioned problems,
An object of the present invention is to provide a semiconductor device which has excellent gate breakdown voltage characteristics and can be manufactured at a high yield rate, and a semiconductor substrate on which the semiconductor device can be formed.

[0014]

In order to achieve the above object, a semiconductor substrate having a CZ wafer and a semiconductor layer region made of FZ crystal bonded on the CZ wafer via an insulating film is provided. I do. Further, an FZ base made of an FZ wafer including a semiconductor layer region and a CZ made of a CZ wafer
A method of manufacturing a semiconductor substrate, comprising the steps of: bonding a Z substrate through an insulating film; and removing the FZ substrate while leaving the semiconductor layer region.

Further, a semiconductor device in which a device having a MOS structure is formed in a semiconductor layer region using the semiconductor substrate. A step of selectively forming a gate oxide film on a semiconductor layer region using the semiconductor substrate; a step of forming a gate electrode on the gate oxide film; and a step of forming a gate electrode on the surface layer of the semiconductor layer region. A method for manufacturing a semiconductor device includes a step of forming a source region and a drain region.

A step of forming a LOCOS oxide film for element isolation on a semiconductor layer region using the semiconductor substrate, and selectively forming a gate oxide film in a region surrounded by the LOCOS oxide film. Forming a gate electrode on the gate oxide film; and forming a source region and a drain region on a surface layer of the semiconductor layer region in a region surrounded by the LOCOS oxide film. The method is for manufacturing a semiconductor device.

As described above, by using the SOI substrate in which the semiconductor layer region of the FZ crystal is bonded to the CZ base material as the support substrate, the semiconductor element is manufactured in the semiconductor layer region free from the influence of the COP. Excellent gate breakdown voltage characteristics can be obtained. In addition, the mechanical strength, which is a problem in the case of the FZ single crystal, is compensated for by using the CZ base material, and the lithography process used in the device manufacturing process does not cause a defocus due to the warpage of the wafer, thereby increasing the mechanical strength. Semiconductor devices can be manufactured at a good product rate.

[0018]

FIG. 1 is a sectional view of a main part of a semiconductor substrate according to a first embodiment of the present invention. This semiconductor substrate is a bonded SOI substrate. This SOI substrate is composed of a CZ base material 1 and a semiconductor layer region 3 made of FZ single crystal bonded to the CZ base material 1 via a bonding oxide film 2. Hereinafter, this SOI substrate is referred to as FZ-CZ-S
OI substrate 100.

As described above, the CZ substrate 1 and the semiconductor layer region 3
Are bonded together via the oxide film 2, thereby obtaining the same mechanical strength as the CZ-CZ-SOI substrate 200 in which the CZ substrates are bonded to each other, and the warpage after the heat treatment step can be reduced. Further, by making the semiconductor layer region 3 a FZ single crystal,
The influence of COP can be eliminated in the semiconductor layer region 3 where the MOS device is formed.

In the heat treatment step, the oxide film 2 of the SOI substrate is made of oxygen (CO 2) contained in the CZ substrate 1 which is a supporting substrate.
Promotes the formation of P), but functions to prevent migration to the semiconductor layer region 3. 2 to 9 show a method of manufacturing a semiconductor substrate according to a second embodiment of the present invention, and are cross-sectional views of main steps in the order of steps. This method of manufacturing a semiconductor substrate is a method of manufacturing the FZ-CZ-SOI substrate 100 of FIG. In the following description, the conductivity type of the substrate is p-type, but may be n-type.

Oxide films 2a and 2b are formed on the surface of the p-type CZ substrate 1 (FIG. 2) (FIG. 3), and an oxide film is formed on the surface of the p-type FZ substrate 4 (FIG. 4). 2c and 2d are formed (FIG. 5). Next, the CZ substrate 1 having the oxide film formed thereon and F
Z substrate 4 is brought into contact with oxide films 2b and 2c (FIG. 6). Next, the CZ contacted via the oxide films 2b and 2c
The substrate 1 and the FZ substrate 4 are subjected to a pyrogenic oxidation heat treatment at 1200 ° C. for 2 hours. This heat treatment step is for firmly fixing the contact portion and ensuring the bonding strength between the base materials. By this heat treatment, the oxide films 2b and 2c are integrated into the bonded oxide film 2, and the thickness of the oxide film 2 is about 1 μm (FIG. 7).

Next, the oxide film 2d is removed, and the FZ base material 4 is removed.
Is ground to the grinding surface 3a shown in FIG. 7 (FIG. 8). Next, the ground surface 3a is polished, and the strained layer formed on the surface layer is removed, so that the semiconductor layer region 3 is formed. The distance between the polished surface 3b and the oxide film 2, that is, the thickness of the semiconductor layer region 3 is about 10 μm. Thus, FZ-C
A Z-SOI substrate 100 is manufactured. It is preferable to leave the oxide film 2a in order to prevent the SOI substrate from bending (FIG. 9).

FIGS. 10A and 10B are diagrams in which MOS capacitors are formed on the semiconductor substrate of FIG. 1. FIG. 10A is a plan view, and FIG. Sectional view,
FIG. 1C is a sectional view of a main part having a trench cut along the line AA in FIG. 1A, and FIG. 2D is a sectional view showing a LOCOS oxide film cut along the line AA in FIG. It is principal part sectional drawing.
FIGS. 10 (b) to 10 (d) are cross-sectional views of main parts of FIG.
FIG. 3A shows a region of a D portion indicated by a dotted line.

Referring to FIG. 10, 160 MOS capacitors having an oxide film 23 having a thickness of 25 nm and an area of 4 mm ² were formed in the plane of the FZ-CZ-SOI wafer 101. This MOS capacitor simulates the gate portion of a MOS device, and measures the withstand voltage of this MOS capacitor,
The gate breakdown voltage, which is the most important characteristic when a MOS device is formed, can be indirectly evaluated.

FIG. 2A is a diagram in which a plurality of MOS capacitors 21 are formed in the plane of the FZ-CZ-SOI wafer 101. Although five MOS capacitors 21 are shown here, 160 are actually formed. FIG. 3B simulates a gate portion of a MOS device having no element isolation region, and selectively forms an oxide film 23 corresponding to a gate oxide film on the semiconductor layer region 3 of the FZ-CZ-SOI substrate 100 of FIG. FIG. 3 is a diagram in which an electrode 22 corresponding to a gate electrode is formed on an oxide film 23. MOS capacitor 2
1 is composed of an electrode 22, an oxide film 23 and a semiconductor layer region 3.

FIG. 3C is a view showing a case where the trench 24 is formed, and corresponds to a case where the MOS devices are separated by the trench 24. FIG. 4D is a diagram in the case where the LOCOS oxide film 25 is formed, and corresponds to a case where the MOS devices are separated by the LOCOS oxide film 25. The withstand voltage characteristics of these MOS capacitors 21 were evaluated, and the results will be described.

FIG. 11 is a diagram showing a histogram of the dielectric breakdown electric field of the oxide film. The MOS capacitor 21 (product of the present invention) used here has the structure of FIG.
In the figure, both the conventional product and the product of the present invention are shown. The conventional product is a CZ-CZ-SOI substrate 200 shown in FIG.
Above, a MOS capacitor having the structure shown in FIG. 10B is manufactured. Note that the frequency on the vertical axis of the histogram is the percentage of breakdowns.

The initial withstand voltage characteristic is determined by the TZDB (Tim) of the oxide film 23 corresponding to the gate oxide film of the MOS capacitor 21.
e Zero Digital Break
down) properties were evaluated. The number of evaluated MOS capacitors 21 is 160. The TZDB characteristics are as follows:
A negative voltage is applied to the second side, and when the leak current flowing through the oxide film 23 becomes equal to or more than a certain value (1 mA / mm ² ), it is considered that the dielectric breakdown has occurred, and the applied voltage (initial withstand voltage) at that time is measured. Was evaluated. Here, a predetermined voltage is applied for 0.2 seconds, and in the next step, the voltage is increased by 0.25 MV / cm in terms of an electric field, and the voltage is increased until dielectric breakdown (to reach 1 mA / mm ² ). Was repeated.

The pickup (the point to which a positive voltage is applied) was taken from above the semiconductor layer region 3 and used as a positive electrode. The validity of this evaluation method was confirmed on a CZ wafer without a buried oxide film (an oxide film corresponding to 2 in the figure). Some conventional products cause dielectric breakdown from 5 MV / cm. On the other hand, the product of the present invention has no initial breakdown voltage and has no dielectric breakdown at such a low electric field.

Here, if the dielectric breakdown at 8 MV / cm or less is regarded as the initial withstand voltage defect, the yield rate of the conventional product is 5%.
In contrast to 9%, the non-defective product of the present invention has a remarkably excellent non-defective rate of 99%. The reason why the non-defective rate is improved is that the semiconductor layer region 3 made of the FZ single crystal which is not affected by the COP as described above is used.

FIG. 12 is a graph showing the relationship between the amount of destructive charge of the oxide film and the cumulative failure rate. This is because the TDDB (Time Dependent Di) of the MOS capacitor 21 is
It is an electronic breakdown characteristic evaluation. The number of evaluated MOS capacitors 21 is 40. The TDDB characteristic is based on the magnitude of the amount of charge that flows until the gate oxide film is finally destroyed by continuously applying a voltage to the electrode 22 so that the leakage current value of the oxide film 23 of the MOS capacitor 21 becomes constant. evaluated. FIG. 3 is a Weibull plot. In the display on the right vertical axis, F is the cumulative failure rate, and Ln indicates the natural logarithm.

From the measurement results, it can be seen that the TDDB characteristic of the product of the present invention is such that the breakdown charge Qbd is larger than that of the conventional product,
B characteristic is excellent. This is because the semiconductor layer region 3 which is not affected by the COP is used as described above. From this, the reliability of the gate oxide film of the MOS device is F
When the Z-CZ-SOI substrate 100 is used, CZ-CZ
-It can be higher than when the SOI substrate 200 is used.

The MO of the structure shown in FIGS. 10 (c) and 10 (d)
As for the S capacitor 21, as a result of evaluating the breakdown voltage characteristics of the oxide film 23, a result equivalent to that of the structure shown in FIG. This means that the trench 24 having the element isolation structure is formed.
That is, even if the LOCOS oxide film 25 is provided, the breakdown voltage characteristics of the oxide film 23 do not change. Therefore, even in an LSI in which a device is separated by a trench or a LOCOS oxide film, the use of the FZ-CZ-SOI substrate can improve the dielectric breakdown resistance of the gate oxide film.

As described above, when the MOS-LSI is formed using the FZ-CZ-SOI substrate, a semiconductor device having a high yield rate and high reliability can be manufactured. FIG. 13 is a sectional view showing a main part of a semiconductor device according to a third embodiment of the present invention. This semiconductor device uses an FZ-CZ-SOI substrate 100 in which a p-type CZ base material 1 and a p-type FZ single-crystal semiconductor layer region 3 are bonded together via an oxide film 2,
This is an example in which a C-MOS (composed of a p-channel MOSFET and an n-channel MOSFET) as an SI element is formed.

An n-well region 31 is selectively formed in the p-type semiconductor layer region 3 of FZ single crystal, and a p-channel MOSFET (P-MOSFET) is formed in the n-well region 31. N-channel MOSF on surface layer
Form ET. Here, a LOCOS oxide film 5 is used for element isolation. Thus, FZ-CZ-S
Semiconductor device (such as C-MOS) using the OI substrate 100
Formed, the breakdown voltage characteristics of the gate oxide film of the MOSFET are improved because there is no influence of the COP, and the occurrence of warpage in the heat treatment process is suppressed, thereby reducing the yield rate of non-defective products in manufacturing. It was able to be improved by about 10% as compared with.

Similar effects can be expected when a trench is formed as an element isolation region. In the figure,
32 is a gate oxide film of a P-MOSFET, 33 is NM
OSFET gate oxide film, 34 is a P-MOSFET gate electrode, 35 is an N-MOSFET gate electrode, 3
6 is an interlayer insulating film, 37 is a p source region, 38 is a p drain region, 39 is ap ⁺ region for making ohmic contact between the semiconductor layer region 3 and the metal electrode 50, 40 is an n source region, and 41 is an n drain region. Region, 42 is n-well region 3
Reference numeral 43 denotes an n ⁺ region for making ohmic contact between the first and metal electrodes 49; 43, a gate wiring of a P-MOSFET;
4 is a source electrode (wiring) of the P-MOSFET, 45 is P
-Drain electrode (wiring) of MOSFET, 46 is N-M
OSFET gate wiring; 47, an N-MOSFET source electrode (wiring); 48, an N-MOSFET drain electrode (wiring); 49, a P-MOSFET reference potential metal electrode (wiring); and 50, an N-MOSFET Is a metal electrode (wiring) having a reference potential.

FIGS. 14 to 26 are cross-sectional views of a main part of a semiconductor device according to a fourth embodiment of the present invention. P of FZ-CZ-SOI substrate 100
An oxide film 61 is grown on the entire surface of the semiconductor layer region 3 of the mold type,
In a lithography step (photo step), an opening is formed in the resist 62 at a position where an n-well region is to be formed, and the oxide film 61 is removed by etching using the resist 62 as a mask.
Next, an n-type impurity 64 is implanted into the semiconductor layer region 3 from the opening by ion implantation 63 (FIG. 14). 64 in the figure
Is an ion-implanted impurity. In some cases, ions are implanted through the oxide film 61 using the resist 62 as a mask without removing the oxide film 61.

Next, the resist 62 is removed and thermally diffused to form the n-well region 31, and then the oxide film 61 and the oxide film formed by thermal diffusion are removed (FIG. 15). Next, an oxide film 65 formed on the surface by pyrogenic oxidation and a nitride film 66 formed on the surface by a low pressure CVD method are laminated, covered with a resist 67, and selectively opened (FIG. 1).
6).

Next, using the resist 67 as a mask, the nitride film 66 is removed, and thereafter, ion implantation 69 as field ion implantation is performed. Reference numeral 70 in the figure denotes an ion-implanted impurity (FIG. 17). Next, ashing (ashing)
To remove the resist 67, and to perform LOCO by thermal oxidation.
An S oxide film 5 (field oxide film) is formed (FIG. 1)
8).

Next, the nitride film 66 is removed, and the oxide film 65 thereunder is also removed by etching (FIG. 19). Next,
An oxide film 73 serving as a gate oxide film is formed on the entire surface, and NM
A portion to be an OSFET is covered with a resist 74, and ion implantation for threshold adjustment (channel ion implantation) is performed by ion implantation 75. Reference numeral 76 in the figure denotes an ion-implanted impurity (FIG. 20).

Next, the resist 74 is removed, and the P-MO
A portion to be the SFET is covered with a resist 77, and ion implantation for threshold adjustment is performed by ion implantation 78. Reference numeral 79 in the figure denotes an ion-implanted impurity (FIG. 21). Next, the resist 77 is removed, and polysilicon 80 to be a gate electrode is formed on the entire surface by CVD (FIG. 2).
2).

Next, the polysilicon 80 is selectively etched away using a resist (not shown) as a mask to form gate electrodes 34 and 35. At this time, the oxide film 73 is also etched but remains partially. Here, the remaining film is not shown. The oxide film 73 under the gate electrodes 34 and 35 becomes the gate oxide films 32 and 33 (FIG. 23). Next, ion implantation (not shown) is performed using the resist 81 as a mask, and PM-
A p ⁺ region 39 for obtaining potentials of the p source region 37, the p drain region 38 and the semiconductor layer region 3 of the OSFET is formed, and the resist 81 is removed (FIG. 24).

Next, ion implantation (not shown) is performed using the resist 82 as a mask to form an n ⁺ region 42 for obtaining the potentials of the n source region 40, the n drain region 41 and the n well region 31 of the N-MOSFET. The resist 82 is removed (FIG. 25). Next, PSG (phosphorus glass)
The film is reflowed to form an interlayer insulating film 36, a contact hole is opened in the interlayer insulating film 36, and an Al metal film is used.
Source electrodes 44 and 47, drain electrodes 45 and 48, gate wires 43 and 46, and metal electrodes 49 and 50 are formed (FIG. 26). The electrodes 44, 45, 47, 48, 49,
Reference numeral 50 also serves as a metal wiring. Next, a passivation film (not shown) is coated to complete a C-MOS which is an LSI element.

[0044]

According to the present invention, the MOS device is connected to the F
By forming it in the semiconductor layer region of Z single crystal, COP
The reliability of the semiconductor device can be improved by eliminating the influence of the defect and improving the breakdown voltage characteristics of the gate oxide film. Further, by using a CZ base material as a support substrate and bonding a semiconductor layer region of an FZ crystal through an oxide film, mechanical strength is increased, and a SOI substrate is prevented from cracking in a heat treatment step. By suppressing the occurrence of sol, it is possible to prevent the focus from being defocused in the lithography process and to increase the yield rate.

[Brief description of the drawings]

FIG. 1 is a sectional view of a main part of a semiconductor substrate according to a first embodiment of the present invention;

FIG. 2 is a sectional view of a main part process in a method of manufacturing a semiconductor substrate according to a second embodiment of the present invention;

FIG. 3 is a sectional view of a main part step in the method for manufacturing a semiconductor substrate according to the second embodiment of the present invention, following FIG. 2;

FIG. 4 is a sectional view of a main step in a method for manufacturing a semiconductor substrate according to a second embodiment of the present invention, following FIG. 3;

FIG. 5 is a sectional view of a main part step in the method for manufacturing a semiconductor substrate according to the second embodiment of the present invention, following FIG. 4;

FIG. 6 is a sectional view of a main step in a method for manufacturing a semiconductor substrate according to a second embodiment of the present invention, following FIG. 5;

FIG. 7 is a sectional view of a main step of a method for manufacturing a semiconductor substrate according to a second embodiment of the present invention, following FIG. 6;

FIG. 8 is a sectional view of a main step in the method for manufacturing a semiconductor substrate according to the second embodiment of the present invention, following FIG. 7;

FIG. 9 is a sectional view of a main step in the method for manufacturing a semiconductor substrate of the second embodiment of the present invention, following FIG. 8;

10A and 10B are diagrams showing a MOS capacitor formed on the semiconductor substrate of FIG. 1, wherein FIG. 10A is a plan view, FIG. 10B is a cross-sectional view of a main part taken along line AA of FIG. a) A cross-sectional view of a main part having a trench groove cut along the line AA, (d) is a sectional view of (a) A
Sectional view of main part having LOCOS oxide film cut along line -A

FIG. 11 is a diagram showing a histogram of a dielectric breakdown electric field of an oxide film.

FIG. 12 is a diagram showing the relationship between the amount of charge breakdown of an oxide film and the cumulative failure rate;

FIG. 13 is a sectional view of a main part of a semiconductor device according to a third embodiment of the present invention;

FIG. 14 is a sectional view of a main part manufacturing process in a method of manufacturing a semiconductor device according to a fourth embodiment of the present invention;

FIG. 15 is a cross-sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 14;

FIG. 16 is a sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 15;

FIG. 17 is a cross-sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 16;

FIG. 18 is a sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 17;

FIG. 19 is a sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 18;

FIG. 20 is a sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 19;

FIG. 21 is a cross-sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 20;

FIG. 22 is a cross-sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 21;

FIG. 23 is a cross-sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 22;

FIG. 24 is a cross-sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 23;

FIG. 25 is a sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 24;

FIG. 26 is a sectional view of a main part manufacturing step in the method for manufacturing a semiconductor device according to the fourth embodiment of the present invention, following FIG. 25;

FIG. 27 is a sectional view of a conventional CZ-CZ-SOI substrate.

FIG. 28 is a sectional view of a main part of a semiconductor device using a conventional CZ-CZ-SOI substrate;

FIG. 29 is a sectional view of an FZ-FZ-SOI substrate;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 CZ base material 2 Oxide film (bonded oxide film) 2a, 2b, 2c, 2d Oxide film 3 Semiconductor layer region 4 FZ base material 5 LOCOS oxide film 21 MOS capacitor 22 Electrode 23 Oxide film (corresponding to gate oxide film) 24 Trench groove 25 LOCOS oxide film 32, 33 Gate oxide film 34, 35 Gate electrode 100 FZ-CZ-SOI substrate 200 CZ-CZ-SOI substrate 300 FZ-FZ-SOI substrate

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat ゛ (Reference) H01L 27/08 331 H01L 29/78 626C 29/786 627D 21/336 (72) Inventor Hitoshi Kuribayashi Kawasaki, Kanagawa Prefecture 1-1-1 Tanabe-Shinda, Ichikawasaki-ku F-term in Fuji Electric Co., Ltd. (reference) HJ13 NN02 NN25 NN62 NN66 QQ17 QQ19

Claims (5)

[Claims] 1. A semiconductor substrate comprising: a CZ wafer; and a semiconductor layer region made of FZ crystal bonded to the CZ wafer via an insulating film. 2. An FZ comprising an FZ wafer including a semiconductor layer region.
A method of manufacturing a semiconductor substrate, comprising: bonding a Z base and a CZ base made of a CZ wafer via an insulating film, and removing the FZ base while leaving the semiconductor layer region. 3. A semiconductor device, wherein a device having a MOS structure is formed in a semiconductor layer region using the semiconductor substrate according to claim 1. 4. A step of selectively forming a gate oxide film on a semiconductor layer region using the semiconductor substrate according to claim 1, and a step of forming a gate electrode on the gate oxide film. Forming a source region and a drain region in a surface layer of the semiconductor layer region. 5. A step of forming a LOCOS oxide film for element isolation on a semiconductor layer region using the semiconductor substrate according to claim 1; and forming a LOCOS oxide film in a region surrounded by the LOCOS oxide film. Selectively forming a gate oxide film; forming a gate electrode on the gate oxide film;
Forming a source region and a drain region in a surface layer of the semiconductor layer region in a region surrounded by a COS oxide film.