JP2002359362A - Element for estimating substrate, its manufacturing method, and estimation method of soi substrate - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an element for estimating a substrate which can estimate rightfully quality of a silicon layer and an insulating layer (buried oxide film) in an SOI substrate wherein an MOS type semiconductor element for estimating the silicon layer and an MOS type semiconductor element for estimating a withstanding voltage of the buried oxide film are formed on the one SOI substrate. SOLUTION: The element for estimating a substrate is used for estimating the SOI substrate 20 wherein the silicon layer 23 is formed on the buried oxide film 22. In the element, an MOS capacitor 30 is formed on the silicon layer 23, a diffusion layer 23a having an opposite type to that of the silicon layer 23 is formed on a silicon layer 23 in the periphery of the MOS capacitor 30, and a diffusion layer 23b having the opposite type is also formed on a prescribed region of the silicon layer 23 in a part except the periphery of the MOS capacitor 30.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI (Silicon) having a structure in which a silicon layer is formed on an insulator or an insulating layer.
On Insulator) An element for evaluating a substrate called a substrate, a method for manufacturing the same, and a method for evaluating an SOI substrate using the element for evaluating a substrate, more specifically, the quality of a silicon layer and an insulating layer in an SOI substrate is properly determined. The present invention relates to a device for evaluating a substrate, a method for manufacturing the same, and a method for evaluating an SOI substrate using the device for evaluating a substrate.

[0002]

2. Description of the Related Art High-performance system software and data
With the advancement of large-capacity data and the development of portable terminals, next-generation semiconductor integrated circuits with high speed and low power consumption are in great demand. The SOI substrate can be used instead of a bulk wafer that has been used up to now without greatly changing the existing LSI manufacturing process, and the speed of the semiconductor device manufactured thereon has been reduced and the power consumption has been reduced. Is attracting attention as a semiconductor substrate that can be realized.

A semiconductor device manufactured using this SOI substrate has a great advantage that a withstand voltage is high and a soft error rate of α rays is low. In particular, thin-film SOI
Substrate (SO with silicon active layer less than 1 μm thick)
When the MOS type semiconductor device formed on the I-substrate is operated in the fully depleted type, the PN junction area of the source / drain can be reduced, thereby reducing the parasitic capacitance and increasing the speed of device driving. be able to. Further, since the capacity of the buried oxide film as the insulating layer is inserted in series with the capacity of the depletion layer formed immediately below the gate oxide film, the capacity of the depletion layer is substantially reduced. The subshred coefficient can be reduced to the theoretical limit value, and low power consumption can be realized. The MOS type semiconductor device formed on the SOI substrate in this manner can achieve high speed and low power consumption without significantly changing the existing LSI manufacturing process.

When evaluating the quality of a normal bulk substrate,
The method called MOS withstand voltage evaluation method has been widely and generally used (Ultra-thin silicon oxide film formation and interface evaluation technology p.96:
Realize, published in 1997). According to this method,
When evaluating the quality of the p-type silicon substrate, a negative bias is applied to the upper metal electrode so that the silicon substrate is in an accumulation state, and a voltage at which the gate oxide film causes dielectric breakdown is obtained. A MOS type semiconductor device showing a withstand voltage is regarded as a non-defective product. The quality of the silicon substrate is determined based on the ratio of non-defective MOS type semiconductor devices in one substrate. For a silicon substrate obtained by a general CZ method, 40 to 60
%, An epitaxial wafer can provide a good pressure-resistant product rate of almost 100%.

Since an SOI substrate has an insulating layer (buried oxide film), electrical contact cannot normally be made from the back side of the substrate, and it is necessary to form an electrical contact on the front side of the substrate. When the silicon layer of the SOI substrate is relatively thick, a method for reducing the contact resistance;
For example, if a method of increasing the impurity concentration of the silicon layer portion in contact with the contact metal, or performing a sintering heat treatment, etc., it is possible to perform an evaluation equivalent to the conventional MOS withstand voltage evaluation method.

FIG. 7 is a cross-sectional view showing a conventional MOS-type evaluation element for evaluating an SOI substrate. In FIG. 7, reference numeral 10 denotes an SOI substrate. A buried oxide film 12 is formed, and a silicon layer 13 is formed on the buried oxide film 12. A gate oxide film 14 is formed on the silicon layer 13, and a poly-Si electrode 15 is formed on the gate oxide film 14.
Are formed, and the silicon layer 13 and the gate oxide film 1 are formed.
4. The MOS type semiconductor element is constituted by the poly-Si electrode 15. A hole 16 is formed in the gate oxide film 14 near the poly-Si electrode 15, a top contact 17 is formed around the hole 16, and a diffusion layer 18 is formed in the silicon layer 13 below the top contact 17. Low contact resistance between the top contact 17 and the silicon layer 13 is achieved.

Since the buried oxide film 12 is present in the SOI substrate 10, for example, when the dielectric breakdown characteristics and the like of the MOS type semiconductor element are evaluated, the back side of the SOI substrate 10 and the polysilicon
The electrical connection with the electrode 15 could not be established, and the top contact 17 was formed on the silicon layer 13 side as described above. The contact resistance between the top contact 17 and the diffusion layer 18 increases the carrier concentration in the silicon layer 13 (> 1).
0 ¹⁹ / cm ³ ) can be suppressed to a considerably low level.

In the SOI substrate 10, the silicon layer 13
As well as the quality of the buried oxide film 12, the quality of the buried oxide film 12 becomes important. As one method of evaluating the breakdown voltage of the buried oxide film 12, when the thickness of the silicon layer 13 is reduced to 1 μm or less, the impurity concentration of the entire silicon layer 13 is increased, and the silicon layer 13 is buried using the electrode as an electrode. Oxide film 12
A method of evaluating the withstand voltage of a semiconductor device has been used.

[0009]

However, in the structure of the element for substrate evaluation described above, when evaluating the thin film SOI substrate, the MOS type semiconductor element for evaluating the silicon layer 13 and the withstand voltage of the buried oxide film 12 are reduced. Since the structure is different from that of the MOS type semiconductor element for evaluation,
There is a problem that the OS type semiconductor element cannot be manufactured by the same manufacturing process, and different wafers must be prepared and manufactured separately for each evaluation.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and includes a MOS type semiconductor element for evaluating a silicon layer and a MOS type semiconductor element for evaluating a withstand voltage of a buried oxide film. SOI formed on substrate
Silicon layer and insulating layer (buried oxide film) on substrate
It is an object of the present invention to provide a substrate evaluation element for properly evaluating the quality of a substrate, a method of manufacturing the same, and a method of evaluating an SOI substrate using the substrate evaluation element.

[0011]

In order to achieve the above object, a substrate evaluation element (1) according to the present invention comprises:
In a substrate evaluation element for evaluating a substrate in which a silicon layer is formed on an insulator or an insulating layer, a MOS capacitor is formed on the silicon layer, and the silicon layer around the MOS capacitor is formed on the silicon layer. And a diffusion layer of the opposite type is formed in a predetermined region of the silicon layer outside the periphery of the MOS capacitor.

For example, in the above-described conventional method for evaluating a p-type substrate, a negative bias is applied to the poly-Si electrode so that the silicon layer is in an accumulation state. The quality of the thin silicon layer cannot be accurately evaluated. This is because the thinning of the silicon layer increases the resistance value of the silicon layer itself, so that a correct voltage is not applied to the gate oxide film. According to the substrate evaluation element (1), the MO
When a positive bias is applied to the upper metal electrode of the S capacitor and the diffusion layer is grounded, if the positive bias exceeds a threshold voltage determined by the carrier concentration of the silicon layer, immediately below the gate oxide film. Then, an n-type inversion layer is formed, and the applied voltage is efficiently applied to the entire gate oxide film. For this reason, the quality of the thinned silicon layer on the SOI substrate can be correctly evaluated without being affected by the thinning of the silicon layer and without generating an electric field concentrated portion in the gate oxide film region. Also, C
From the V measurement, the correct substrate carrier concentration of the thinned silicon layer can be obtained.

When evaluating the quality of the insulating layer (buried oxide film), a negative bias is applied to the upper metal electrode of the opposite type diffusion layer formed in a predetermined region of the silicon layer. If the supporting substrate of the insulating layer is grounded, the diffusion layer becomes an electrode, and the applied voltage is efficiently applied to the insulating layer. For this reason, the quality of the insulating layer in the SOI substrate can be correctly evaluated without being affected by the thinning of the insulating layer and without causing electric field concentrated portions in the insulating layer. As described above, according to the substrate evaluation element (1), the MOS type semiconductor element for evaluating the silicon layer and the MOS type semiconductor element for evaluating the withstand voltage of the insulating layer (buried oxide film) are provided. It can be formed on one SOI substrate.

The method (1) for manufacturing a device for evaluating a substrate according to the present invention comprises the steps of: (a) forming a gate electrode and a predetermined region at a predetermined location on a silicon layer via a gate oxide film; Forming a region (b) forming a diffusion layer of a type opposite to the type of the silicon layer in the silicon layer in the periphery below the gate electrode and in the predetermined region.

According to the method (1) for manufacturing a substrate evaluation element, the SOI substrate can be formed without being affected by the thinning of the silicon layer in the SOI substrate, and without creating an electric field concentration portion in the gate oxide film region. The quality of the thinned silicon layer and the insulating layer can be evaluated correctly, and the insulating layer in the SOI substrate can be inspected without being affected by the thinning of the insulating layer, and without causing an electric field concentration place in the insulating layer. It is possible to easily manufacture a substrate evaluation element capable of performing a correct quality evaluation of a layer.

In the method (1) for evaluating an SOI substrate according to the present invention, a bias is applied to the gate electrode of the MOS capacitor when the silicon layer is evaluated using the above-described element (1) for substrate evaluation. And applying a bias to the diffusion layer in the predetermined region when evaluating the insulation layer, and setting a support substrate of the insulation layer to the ground when evaluating the insulation layer. According to the SOI substrate evaluation method (1), the correct quality evaluation of the silicon layer and the correct quality evaluation of the insulating layer are performed in one way.
It can be easily done in c.

[0017]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a device for evaluating a substrate according to the present invention, a method for manufacturing the same, and an SOI using the device for evaluating a substrate will be described.
An embodiment of a method for evaluating a substrate will be described with reference to the drawings. 1 (a) to 1 (d) and 2 (a) to 2 (c) are cross-sectional views schematically showing a manufacturing process of the substrate evaluation element according to the embodiment, and FIG. 2 shows the SOI substrate 20 before being applied. In the figure, reference numeral 21 denotes a Si support substrate. A buried oxide film (insulating layer) 22 is formed on the Si support substrate 21, and a silicon layer 23 is formed on the buried oxide film 22.

First, the silicon layer 2 of the SOI substrate 20
3, for example, at 900 to 1000 ° C. for 30 to 50 minutes,
A gate oxide film 24 having a thickness of 5 to 40 nm is formed in a 100% oxygen atmosphere. Next, on the gate oxide film 24, at 600-700 ° C. for 30-60 minutes, at a pressure of 0.4-0.
A poly-Si layer 25 having a thickness of 200 to 500 nm is formed by CVD using SiH ₄ and N ₂ as source gases at 7 hPa (FIG. 1B).

Next, a photoresist layer (not shown) is formed on the poly-Si layer 25, and a photolithography process is performed to form a gate electrode and a predetermined region outside the periphery of the gate electrode. A photoresist pattern (not shown) having a predetermined shape is formed. Next, using the photoresist pattern as a mask, the poly-Si layer 25 is etched. This etching process is performed by using HF / HNO ₃ / CH ₃ C
Wet etching with OOH or a mixed solution such as HF / HNO ₃ / H ₂ O, SF ₆ , Cl ₂ , HB
r, plasma dry etching using BCl ₃ or the like (FIG. 1C). Thereafter, the gate oxide film 24 at the portion where the poly-Si layer 25 has been etched is removed by wet etching using HF or BHF (FIG. 1D).

Thereafter, POCl is used for the purpose of lowering the resistance of the poly-Si layer 25 and forming the n-type diffusion layers 23a and 23b.
A phosphorus diffusion treatment is performed at 850 to 950 ° C. for 8 to 16 minutes using ₃ + O ₂ + N ₂ (FIG. 2A). Instead of this phosphorus diffusion treatment, in another embodiment, P ⁺ and As ⁺ are ion-implanted under the conditions of ion implantation energy of 20 to 60 keV.
May be performed.

Then, an interlayer insulating oxide film 26 having a thickness of 30 to 70 nm is formed by a CVD method at 800 to 900 ° C. and 0.3 to 0.7 hPa using SiH ₄ + N ₂ O as a source gas (FIG. 2B). )). This interlayer insulating oxide film 26 is formed by the above-described CVD method.
A thermal oxidation method at 0 to 1200 ° C. in a diluted oxygen atmosphere or a 100% oxygen atmosphere may be used.

Next, a photoresist layer (not shown) is formed on the interlayer insulating oxide film 26, and a photolithography process is performed to form a contact hole pattern (not shown) having a predetermined shape. Next, using this photoresist pattern as a mask, the interlayer insulating oxide film 26 is etched.
This etching is performed by wet etching using HF or BHF, or CF ₄ , CHF ₃ , C ₆
It is performed by plasma dry etching using F ₃ , C ₃ F ₈ or the like.

After that, the electrode 2 serving as a top contact
To form 7, 28, 29, Al, Al-Si-
A metal layer made of Cu, W, Ti or the like is formed to a thickness of about 0.5 to 3 μm by a sputtering method or a CVD method. Next, a photoresist layer (not shown) is formed on the metal layer,
A photoresist pattern (not shown) having an electrode pattern of a predetermined shape is formed by performing a photolithography process. Next, using the photoresist pattern as a mask, the metal layer is etched to form electrodes 27, 28 and 29. When the metal layer is formed of Al, this etching is performed by wet etching using a mixed solution such as H ₃ PO ₃ + CH ₃ COOH, or by using CCl ₄ , BCl
₃ , plasma dry etching using BBr ₃ , HBr or the like.

In the above embodiment, the case where the silicon layer 23 is p-type has been described as an example.
3 is not limited to a p-type at all, and may be an n-type. When the silicon layer 23 is an n-type, boron diffusion may be performed instead of phosphorus diffusion. In this case, when the SOI substrate 20 is evaluated, a negative bias is applied to the poly-Si layer 25 to form a p-type inversion layer on the silicon layer 23, so that the insulation of the gate oxide film 24 can be accurately determined. Destruction evaluation can be performed.

The SOI substrate has a structure in which a silicon semiconductor layer is formed on a buried oxide film 22.
In addition to an I (Silicon On Insulator) substrate, an amorphous silicon layer or a polysilicon layer as a silicon layer may be formed on a glass substrate or a quartz substrate as an insulator. By the above process,
On a SOI substrate 20, a poly-Si layer 25 and a gate oxide film 2
4 and MOS capacitor 3 made of silicon layer 23
0, the diffusion layer 23b, the buried oxide film 22, and Si
The MOS capacitor 31 composed of the support substrate 21 is formed.

In evaluating the thinned silicon layer 23 of the SOI substrate 20 having the above structure, a positive bias is applied to the upper metal electrode 27 of the MOS capacitor 30, and the diffusion layer 23a
Is the ground. Then, when the positive bias exceeds the threshold voltage determined by the carrier concentration of the silicon layer 23, an n-type inversion layer is formed immediately below the gate oxide film 24, and the applied voltage is efficiently increased. It will cover the entire film 24. For this reason, the gate oxide film 2 is not affected by the thinning of the silicon layer 23, and no electric field is concentrated in the region of the gate oxide film 24.
4, the quality of the thinned silicon layer 23 in the SOI substrate 20 can be evaluated correctly without causing dielectric breakdown. Further, a correct substrate carrier concentration of the thinned silicon layer 23 can be obtained from the CV measurement.

In evaluating the buried oxide film 22 of the SOI substrate 20 having the above-described structure, a negative bias is applied to the upper metal electrode 29 of the MOS capacitor 31 and the Si support substrate 21 is grounded. Then, the applied voltage is efficiently applied to the entire buried oxide film 22 immediately below the diffusion layer 23b. Therefore, the buried oxide film 22 is not affected by the thinning of the silicon layer 23, no electric field concentration occurs in the region of the buried oxide film 22. Correct quality evaluation of the buried oxide film 22 can be performed.

In evaluating the SOI substrate 20,
As shown in FIG. 3, the electron concentration in the n-type inversion layer is increased,
Further, light irradiation may be performed to reduce the resistance of the silicon layer 23.

[0029]

Examples and Comparative Examples Hereinafter, a device for evaluating a substrate according to the present invention, a method for manufacturing the same, and an SOI using the device for evaluating a substrate will be described.
Examples of a method for evaluating a substrate and comparative examples will be described. First, several elements for substrate evaluation shown in FIG. 2C (Example) and FIG. 7 (Comparative Example) were manufactured under the following conditions.

Example 1 SOI substrate used SIMOX Silicon layer 23 Thickness: 0.1 μm Buried oxide film 22 Film thickness: 0.1 μm Etching: Wet etching by HF Gate oxide film 24 Film thickness: 25 nm Poly Forming method of Si layer 25: CVD method: 630 ° C .: 0.3 hPa Phosphorus diffusion treatment: 900 ° C .: POCl ₃ + O ₂ + N ₂ film thickness: 0.4 μm ・ Diffusion layer 23a and poly Si layer 25 are used as a mask to form diffusion layer 23b. Forming POCl ₃ + O ₂ + N ₂ using phosphorus diffusion treatment at 900 ° C. for 15 minutes Example 2 SOI substrate used Bonded SOI Other conditions are the same as those in Example 1.

Comparative Example : Thickness of silicon layer 13: 0.1 μm Thickness of buried oxide film 12: 0.1 μm Diffusion layer 18 Forming method: PBF coating diffusion method Heat treatment conditions: 800 ° C., 10 minutes Gate oxide film 14 Film thickness: 25 nm ・ Poly-Si electrode 15 and method: CVD method Top contact 17 Phosphorus diffusion treatment: 900 ° C. Formation: AlEB vapor deposition Film thickness: 0.8 μm

[0032] Characteristics Measurements Figure 4 of the evaluation device using the evaluation device according to Examples 1 and 2 produced by the above conditions, shows a result of measuring the withstand voltage characteristics of the gate oxide film 24, conducted 5 The results of measuring the breakdown voltage characteristics of the buried oxide film 22 using the evaluation elements according to Examples 1 and 2 are shown. FIG. 6 illustrates the breakdown voltage characteristics of the gate oxide film 14 measured using the evaluation element according to the comparative example. The results are shown.

In the device according to the comparative example, the IV curve in the high electric field region does not rise due to the influence of the series resistance component of the silicon layer 13, and only a part of the applied voltage is applied to the gate oxide film 14. No dielectric breakdown phenomenon could be observed.

On the other hand, in the evaluation elements according to the first and second embodiments, since the resistance component of the silicon layer 23 can be neglected, a voltage can be accurately applied to the gate oxide film 24, and the gate oxide film having a dielectric breakdown crystal defect can be used. Dielectric breakdown occurs in the film 24,
The gate oxide film 24 having no crystal defects does not cause dielectric breakdown,
The quality evaluation of the gate oxide film 24 was possible. Also, S
There is a difference between IMOX and bonded SOI,
It was confirmed that X had less B mode failure.

Further, in the evaluation elements according to the first and second embodiments, it is possible to accurately evaluate the breakdown voltage characteristics of the buried oxide film 22, and there is a difference between the SIMOX and the bonded SOI. It was confirmed that dielectric breakdown occurred at a low electric field.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views schematically showing a manufacturing process of a substrate evaluation element according to an embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views schematically showing a manufacturing process of a substrate evaluation element according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing another measurement method for the substrate evaluation element according to the embodiment of the present invention.

FIG. 4 is a graph showing a withstand voltage measurement curve of a gate oxide film of a device for evaluating a substrate according to an example.

FIG. 5 is a graph showing a withstand voltage measurement curve of a buried oxide film of a substrate evaluation element according to an example.

FIG. 6 is a graph showing a withstand voltage measurement curve of a gate oxide film of a substrate evaluation element according to a comparative example.

FIG. 7 is a cross-sectional view showing a conventional MOS capacitor as a substrate evaluation element.

[Explanation of symbols]

 Reference Signs List 20 SOI substrate 21 Si support substrate 22 buried oxide film 23 silicon layer 23a, 23b diffusion layer 24 gate oxide film 25 polySi layer 26 interlayer insulating oxide film 27 electrode 28 electrode 29 electrode

Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (reference) H01L 21/822 H01L 27/08 331E 27/04 27/04 T 27/08 331 29/78 624 29/786 F term ( Reference) 4M106 AA07 AB01 AB20 AC02 CA14 CA70 5F038 DT11 EZ06 EZ20 5F048 AC10 BA16 BB05 BB06 5F110 AA24 CC02 DD02 DD03 DD05 DD13 EE09 EE38 FF02 GG02 GG12 GG13 GG15 HL03 HL04 HL06 NN23 NN24 NN23

Claims (3)

[Claims] 1. A substrate evaluation element for evaluating a substrate having a silicon layer formed on an insulator or an insulating layer, wherein a MOS capacitor is formed on the silicon layer.
A diffusion layer of a type opposite to the type of the silicon layer is formed in the silicon layer around the MOS capacitor, and
A device for evaluating a substrate, wherein a diffusion layer of the opposite type is formed in a predetermined region of the silicon layer outside a periphery of a capacitor. (A) forming a gate electrode and a region for separating a predetermined region at a predetermined position on a silicon layer via a gate oxide film; and (b) forming a peripheral region below the gate electrode and Forming a diffusion layer of a type opposite to the type of the silicon layer in the silicon layer in the predetermined region. 3. The method for evaluating a silicon layer using the element for substrate evaluation according to claim 1, wherein a bias is applied to a gate electrode of the MOS capacitor, and the diffusion layer is grounded. When evaluating the insulating layer, a bias is applied to the diffusion layer in the predetermined region, and a substrate for evaluating the insulating layer is used as a ground, wherein the substrate evaluation element according to claim 1 is used. Evaluation method for SOI substrate.