JP2001077336A - Substrate evaluation element and its manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To precisely evaluate a SOI substrate by forming a MOS capacitor on a silicon layer and forming the diffusion layer of a type opposite to that of the silicon layer in the silicon layer at the periphery of the MOS capacitor. SOLUTION: A MOS capacitor 30 formed of a polysilicone layer 25, a gate oxide film 24 and a silicon layer 23 is formed on a SOI substrate 20. When positive bias is applied to the upper metal electrode 29 of the MOS capacitor 30 and a diffusion layer 23a is set to be ground at the time of evaluating the SOI substrate 20, an n-type inversion layer is speedily formed just below the gate oxide film 24 and applied voltage is efficiently given to the gate oxide film 24 when positive bias exceeds threshold voltage decided by the carrier concentration of the silicon layer 23. The quality of the thinned silicone layer 23 in the SOI substrate 20 can precisely be evaluated without being affected by the thinning of the silicon layer 23 without generating a part where electric field is concentrated in the area of the gate oxide film 24 and without insulating destruction in the gate oxide film 24.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an SOI (Silicon) having a structure in which a silicon layer is formed on an insulator or an insulating layer.
The present invention relates to a substrate evaluation element called a substrate and a method of manufacturing the same, and more particularly, to a substrate evaluation element for properly evaluating the quality of a silicon layer in an SOI substrate and a method of manufacturing the same.

[0002]

2. Description of the Related Art High-performance system software and data
With the advancement of large-capacity data and the development of portable terminals, next-generation semiconductor integrated circuits with high speed and low power consumption are in great demand. The SOI substrate can be used instead of a bulk wafer that has been used up to now without greatly changing the existing LSI manufacturing process, and the speed of the semiconductor device manufactured thereon has been reduced and the power consumption has been reduced. Is attracting attention as a semiconductor substrate that can be realized.

A semiconductor device manufactured using this SOI substrate has a great advantage that a withstand voltage is high and a soft error rate of α rays is low. In particular, thin-film SOI
Substrate (SO with silicon active layer less than 1 μm thick)
When the MOS type semiconductor device formed on the I-substrate is operated in the fully depleted type, the PN junction area of the source / drain can be reduced, thereby reducing the parasitic capacitance and increasing the speed of device driving. be able to. Further, since the capacity of the buried oxide film as the insulating layer is inserted in series with the capacity of the depletion layer formed immediately below the gate oxide film, the capacity of the depletion layer is substantially reduced. The subshred coefficient can be reduced to the theoretical limit value, and low power consumption can be realized. The MOS type semiconductor device formed on the SOI substrate in this manner can achieve high speed and low power consumption without significantly changing the existing LSI manufacturing process.

When evaluating the quality of a normal bulk substrate,
The MOS withstand voltage evaluation method has been widely and generally used (silicon thermal oxide film and its interface, p.225 Realize, published in 1991). According to this method, when evaluating the quality of the p-type silicon substrate, a negative bias is applied to the upper metal electrode so that the silicon substrate is in an accumulation state,
A voltage at which a gate oxide film causes dielectric breakdown is obtained, and a MOS semiconductor device having a higher breakdown voltage than a predetermined judgment voltage is determined as a non-defective product.
The quality of the silicon substrate is determined based on the ratio of non-defective MOS type semiconductor devices in one substrate. With a silicon substrate obtained by a general CZ method, a good yield rate of 40 to 60% can be obtained for an epitaxial wafer, and almost 100% can be obtained for an epitaxial wafer.

Since an SOI substrate has an insulating layer (buried oxide film), electrical contact cannot normally be made from the back side of the substrate, and it is necessary to form an electrical contact on the front side of the substrate. When the silicon layer of the SOI substrate is relatively thick, a method for reducing the contact resistance;
For example, if a method of increasing the impurity concentration of the silicon layer portion in contact with the contact metal, or performing a sintering heat treatment, etc., it is possible to perform an evaluation equivalent to the conventional MOS withstand voltage evaluation method.

FIG. 4 is a sectional view showing a conventional MOS-type evaluation element for evaluating an SOI substrate. In FIG. 4, reference numeral 10 denotes an SOI substrate. A buried oxide film 12 is formed, and a silicon layer 13 is formed on the buried oxide film 12. A gate oxide film 14 is formed on the silicon layer 13, and a poly-Si electrode 15 is formed on the gate oxide film 14.
Are formed, and the silicon layer 13 and the gate oxide film 1 are formed.
4. The MOS type semiconductor element is constituted by the poly-Si electrode 15. A hole 16 is formed in the gate oxide film 14 near the poly-Si electrode 15, a top contact 17 is formed around the hole 16, and a diffusion layer 18 is formed in the silicon layer 13 below the top contact 17. Low contact resistance between the top contact 17 and the silicon layer 13 is achieved.

Since the buried oxide film 12 is present in the SOI substrate 10, for example, when the dielectric breakdown characteristics and the like of the MOS type semiconductor element are evaluated, the back side of the SOI substrate 10 and the poly-Si
The electrical connection with the electrode 15 could not be established, and the top contact 17 was formed on the silicon layer 13 side as described above. The contact resistance between the top contact 17 and the diffusion layer 18 increases the carrier concentration in the silicon layer 13 (> 1).
0 ¹⁹ / cm ³ ) can be suppressed to a considerably low level.

[0008]

However, in the structure of the substrate evaluation element for forming the top contact 17 described above, when the thin film SOI substrate is evaluated, the silicon layer 13 is formed.
May affect the electrical characteristic value and may not be properly evaluated. In order to prevent the resistance value of the silicon layer 13 from affecting the electrical characteristic value, it is desirable that the formation position of the diffusion layer 18 be as close as possible to the capacitor portion of the MOS type semiconductor element (immediately below the edge of the poly-Si electrode 15). . Ideally, as shown in FIG. 5, it is desirable that the diffusion layer 18 is brought close to just below the edge of the poly-Si electrode 15, and that the structure does not overlap with the poly-Si electrode 15.

However, the top contact 1 having such a structure
It is extremely difficult to uniformly form 7 and diffusion layer 18 over the entire area of SOI substrate 10. For example, when ion implantation for forming the diffusion layer 18 is performed in a self-alignment manner using the poly-Si electrode 15 as a mask, the diffusion layer region naturally expands by the subsequent heat treatment, and the diffusion layer 18 is formed below the poly-Si electrode 15. It is unavoidable to overlap with the poly-Si electrode 15. When such overlap occurs, electric field concentration occurs in the region of the gate oxide film 14 above the diffusion layer 18, so that dielectric breakdown of the gate oxide film 14 easily occurs, and correct quality evaluation of the silicon layer 13 in the SOI substrate 10 is performed. You will not be able to do it. Also, MO
A correct substrate carrier concentration cannot be obtained from the CV measurement of the S capacitor.

Further, a silicon layer 13 having a thickness of 1 μm or less is required for an SOI substrate for fabricating a next-generation MOS type semiconductor device in order to realize higher speed and lower power consumption. Even if the contact resistance on the surface of the silicon layer 13 is reduced, the resistance of the silicon layer 13 itself increases due to thinning, and a predetermined voltage cannot be applied to the gate oxide film 14 of the MOS type semiconductor device to be evaluated. There was a problem that the quality of the valid silicon layer 13 could not be evaluated.

One solution to this problem is to increase the impurity concentration of the silicon layer (Gate Oxide) in order to reduce the resistance value directly below the gate oxide film of the silicon layer itself.
Integrity on ITOX-SIMOX Wafer: Proc.IEEE Int.SOI
Conf. Oct. 1996, p.162) has been proposed. But,
In this method, ions must be implanted or thermally diffused to introduce impurities into the silicon layer, which leaves a problem that the process becomes complicated and that the impurity concentration of the silicon layer that can be evaluated is limited. I was

The present invention has been made in view of the above problems, and has as its object to provide a substrate evaluation element capable of correctly evaluating an SOI substrate and a method of manufacturing the same.

[0013]

Means for Solving the Problems To achieve the above object, a substrate evaluation element (1) according to the present invention is a substrate evaluation element for evaluating a substrate having a silicon layer formed on an insulating layer. A MOS capacitor is formed on the silicon layer, and a diffusion layer of a type opposite to that of the silicon layer is formed in the silicon layer around the MOS capacitor.

For example, in the above-described conventional method for evaluating a p-type substrate, a negative bias is applied to the poly-Si electrode so that the silicon substrate is in an accumulation state. The quality of the thin silicon layer cannot be accurately evaluated. This is because the thinning of the silicon layer increases the resistance value of the silicon layer itself, so that a correct voltage is not applied to the gate oxide film. According to the substrate evaluation element (1), the M
When a positive bias is applied to the upper metal electrode of the OS capacitor and the diffusion layer is grounded, if the positive bias exceeds a threshold voltage determined by the carrier concentration of the silicon layer, immediately below the gate oxide film. Then, an n-type inversion layer is formed, and the applied voltage is efficiently applied to the entire gate oxide film. For this reason, the quality of the thinned silicon layer on the SOI substrate can be correctly evaluated without being affected by the thinning of the silicon layer and without generating an electric field concentrated portion in the gate oxide film region. Also, C
From the V measurement, the correct substrate carrier concentration of the thinned silicon layer can be obtained.

Further, the substrate evaluation element (2) according to the present invention.
Is characterized in that, in the device for substrate evaluation (1), the insulating layer is an oxide film, and the silicon layer is a silicon semiconductor layer. According to the substrate evaluation element (2), it is possible to perform a correct quality evaluation of the SOI substrate for fabricating the next generation MOS type semiconductor device.

Further, the element (3) for evaluating a substrate according to the present invention.
Is characterized in that, in the above-described device for substrate evaluation (1), the insulator is a glass substrate or a quartz substrate, and the silicon layer is an amorphous silicon layer or a polysilicon layer. According to the substrate evaluation element (3), for example, it is possible to correctly evaluate the quality of an SOI substrate for producing a next-generation TFT active matrix type liquid crystal device.

The method (1) for manufacturing a device for evaluating a substrate according to the present invention comprises the steps of: (a) forming a gate electrode at a predetermined position on a silicon layer via a gate oxide film; Forming a diffusion layer of a type opposite to that of the silicon layer in the silicon layer around the lower part of the gate electrode.

According to the method (1) for manufacturing a substrate evaluation element, the SOI substrate can be formed without being affected by the thinning of the silicon layer in the SOI substrate and without causing an electric field concentration portion in the gate oxide film region. It is possible to easily manufacture a substrate evaluation element capable of performing correct quality evaluation of a thinned silicon layer in the above.

In the method (2) for manufacturing a device for evaluating a substrate according to the present invention, in the method for manufacturing the device for evaluating a substrate (1), the process for forming the diffusion layer is a thermal diffusion doping process. It is characterized by: According to the method (2) for manufacturing a substrate evaluation element, the diffusion layer having excellent film quality can be easily formed.

In the method (3) for manufacturing a substrate evaluation element according to the present invention, in the method for manufacturing a substrate evaluation element (1), the process for forming the diffusion layer is an ion implantation process. It is characterized by. According to the method (3) for manufacturing a substrate evaluation element, the carrier concentration in the diffusion layer can be easily adjusted to a desired range by adjusting the ion implantation amount.

[0021]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a device for evaluating a substrate and a method of manufacturing the same according to the present invention. 1 (a) to 1 (d) and 2 (a) to 2 (c) are cross-sectional views showing respective steps of a method for manufacturing a substrate evaluation element according to an embodiment, and FIG. 2 shows the SOI substrate 20 before being applied. In the figure, reference numeral 21 denotes a Si support substrate, on which a buried oxide film 22 is formed, and on the buried oxide film 22, a silicon layer 23 is formed.

First, for example, 9
A gate oxide film 24 having a thickness of 5 to 40 nm is formed in a 100% oxygen atmosphere at 00 to 1000 ° C. for 30 to 50 minutes. Next, at 600 to 700 ° C. on the gate oxide film 24,
30 to 60 minutes, pressure 0.4 to 0.7 hPa, thickness 200 to 5 by CVD using SiH ₄ and N ₂ as source gases.
A 00 nm poly-Si layer 25 is formed (FIG. 1B).

Next, a photoresist layer (not shown) is formed on the poly-Si layer 25, and a photolithography process is performed to form a photoresist pattern (not shown) having a predetermined shape. Next, using the photoresist pattern as a mask, the poly-Si layer 25 is etched. This etching treatment is performed by wet etching using a mixed solution of HF / HNO ₃ / CH ₃ COOH or HF / HNO ₃ / H ₂ O, or plasma dry etching using SF ₆ , Cl ₂ , HBr, BCl ₃ or the like. (FIG. 1C). Thereafter, the gate oxide film 24 at the portion where the poly-Si layer 25 has been etched is removed by wet etching using HF or BHF (FIG. 1D).

Thereafter, for the purpose of lowering the resistance of the poly-Si layer 25 and forming the n-type diffusion layer 23a, POCl ₃ + O ₂ +
A phosphorus diffusion treatment is performed at 850 to 950 ° C. for 8 to 16 minutes using N ₂ (FIG. 2A). In addition, instead of this phosphorus diffusion process, in another embodiment, the ion implantation energy
P ⁺ and As ⁺ ion implantation may be performed under the conditions of 20 to 60 keV.

Then, an interlayer insulating oxide film 26 having a thickness of 30 to 70 nm is formed by a CVD method at 800 to 900 ° C. and 0.4 to 0.7 hPa using SiH ₄ + N ₂ O as a source gas (FIG. 2B). )). This interlayer insulating oxide film 26 is formed by the above-described CVD method.
A thermal oxidation method at 0 to 1200 ° C. in a diluted oxygen atmosphere or a 100% oxygen atmosphere may be used.

Next, a photoresist layer (not shown) is formed on the interlayer insulating oxide film 26, and a photolithography process is performed to form a contact hole pattern (not shown) having a predetermined shape. Next, using this photoresist pattern as a mask, the interlayer insulating oxide film 26 is etched.
This etching is performed by wet etching using HF or BHF, or CF ₄ , CHF ₃ , C
_This is performed by plasma dry etching using ₆ F ₃ , C ₃ F ₈ or the like.

After that, the electrode 2 serving as a top contact
8, 29 to form Al, Al-Si-Cu,
Sputtering or CVD of a metal layer made of W, Ti, etc.
It is formed to a thickness of about 0.5 to 3 μm by a method. Next, a photoresist layer (not shown) is formed on the metal layer, and a photolithography process is performed to form a photoresist pattern (not shown) having an electrode pattern of a predetermined shape. Next, using the photoresist pattern as a mask, the metal layer is etched to form electrodes 28 and 29. When the metal layer is formed of Al, the etching process may be wet etching using a mixed solution such as H ₃ PO ₃ + CH ₃ COOH, or CCl ₄ , BCl ₃ , BBr ₃ , H
This is performed by plasma dry etching using Br or the like.

In the above embodiment, the case where the silicon layer 23 is of p-type has been described as an example.
3 is not limited to the p-type, but may be of the n-type. When the silicon layer 23 is of the n-type, boron diffusion may be performed instead of phosphorus diffusion. In this case, when the SOI substrate 20 is evaluated, the poly-Si layer 25
By forming a p-type inversion layer on the silicon layer 23 by applying a negative bias, the dielectric breakdown of the gate oxide film 24 can be accurately evaluated.

As an SOI substrate, an SOI substrate having a structure in which a silicon semiconductor layer is formed on a buried oxide film 22 is used.
In addition to an I (Silicon On Insulator) substrate, an amorphous silicon layer or a polysilicon layer as a silicon layer may be formed on a glass substrate or a quartz substrate as an insulator. By the above process,
On a SOI substrate 20, a poly-Si layer 25 and a gate oxide film 2
4 and MOS capacitor 30 composed of silicon layer 23
Is formed.

When the SOI substrate 20 having the above configuration is evaluated, a positive bias is applied to the upper metal electrode 29 of the MOS capacitor 30 and the diffusion layer 23a is grounded.
When the positive bias exceeds a threshold voltage determined by the carrier concentration of the silicon layer 23, an n-type inversion layer is immediately formed immediately below the gate oxide film 24, and the applied voltage is efficiently increased. Will take the whole. For this reason, the SOI substrate 20 is not affected by the thinning of the silicon layer 23, does not have an electric field concentrated portion in the region of the gate oxide film 24, and does not cause dielectric breakdown in the gate oxide film 24. The quality of the thinned silicon layer 23 can be correctly evaluated. Further, a correct substrate carrier concentration of the thinned silicon layer 23 can be obtained from the CV measurement.

In evaluating the SOI substrate 20,
As shown in FIG. 3, the electron concentration in the n-type inversion layer is increased,
Further, light irradiation may be performed to reduce the resistance of the silicon layer 23.

[0032]

Examples and Comparative Examples Hereinafter, examples of the element for evaluating a substrate according to the present invention and a method for manufacturing the same and comparative examples will be described.
First, several elements for substrate evaluation shown in FIG. 2C (Example) and FIG. 4 (Comparative Example) were manufactured under the following conditions.

Example : Thickness of silicon layer 23: 0.2 μm Thickness of buried oxide film 22: 0.21 μm Etching: wet etching by HF Thickness of gate oxide film 24: 25 nm Poly-Si layer 25 Method: CVD Formation of method Phosphorus diffusion treatment: 900 ° C. POCl ₃ + O ₂ + N ₂ film thickness: 0.4 μm ・ Formation of diffusion layer 23a Phosphor diffusion at 900 ° C. for 12 minutes using POCl ₃ + O ₂ + N ₂ using polySi layer 25 as a mask processing

Comparative Example : Thickness of silicon layer 13: 0.2 μm Thickness of buried oxide film 12: 0.21 μm Method of forming diffusion layer 18: PBF coating diffusion method Heat treatment condition: 800 ° C., 10 minutes Gate oxidation Film 14 Thickness: 25 nm ・ Poly-Si electrode 15 and method: CVD method Top contact 17 Phosphorus diffusion treatment: Formation at 900 ° C. AlEB evaporation Film thickness: 0.8 μm

[0035] Characteristics Measurements Figure 6 of the evaluation device using the evaluation device according to the embodiment was manufactured by the above conditions, shows a result of the oxide dielectric breakdown voltage characteristics of the gate oxide film 24 was measured in Comparative Example 7 4 shows the results of measuring the oxide film breakdown voltage characteristics of the gate oxide film 14 using the evaluation element according to (1). In the device according to the comparative example, the IV curve in the high electric field region does not rise due to the influence of the series resistance component of the silicon layer 13, only a part of the applied voltage is applied to the gate oxide film 14, and the dielectric breakdown of the gate oxide film 14 occurs. The phenomenon could not be observed. On the other hand, in the evaluation element according to the example, the resistance component of the silicon layer 23 can be neglected, so that a voltage can be accurately applied to the gate oxide film 24, and the gate oxide film 24 having a dielectric breakdown crystal defect has no dielectric breakdown. The resulting gate oxide film 24 having no crystal defects did not cause dielectric breakdown, and the quality of the silicon layer 23 could be evaluated.

[Brief description of the drawings]

FIGS. 1A to 1D are cross-sectional views showing respective manufacturing steps of a substrate evaluation element according to an embodiment of the present invention.

FIGS. 2A to 2C are cross-sectional views illustrating respective manufacturing steps of a substrate evaluation element according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing another measurement method for the substrate evaluation element according to the embodiment of the present invention.

FIG. 4 is a cross-sectional view showing a conventional MOS capacitor as a substrate evaluation element.

FIG. 5 is a cross-sectional view showing a conventional MOS capacitor as a substrate evaluation element.

FIG. 6 is a graph showing an oxide film breakdown voltage measurement curve of a substrate evaluation element according to an example.

FIG. 7 is a graph showing an oxide film breakdown voltage measurement curve of a substrate evaluation element according to a comparative example.

[Explanation of symbols]

 Reference Signs List 20 SOI substrate 21 Si support substrate 22 buried oxide film 23 silicon layer 23a diffusion layer 24 gate oxide film 25 polySi layer 26 interlayer insulating oxide film 28 electrode 29 electrode

Continued on front page F-term (reference) 4M106 AA07 AA10 AA20 AB12 AB15 AB17 BA14 CA12 CA27 CA70 CB02 5F110 AA24 BB01 CC02 DD02 DD03 DD05 DD13 EE09 EE36 FF02 FF23 GG02 GG13 GG15 GG24 GG44 HJ01 NN03 NN23 NN03 NN NN37 NN72 QQ05

Claims (6)

[Claims] 1. A substrate evaluation element for evaluating a substrate having a silicon layer formed on an insulator or an insulating layer, wherein a MOS capacitor is formed on the silicon layer.
A substrate evaluation element, wherein a diffusion layer of a type opposite to that of the silicon layer is formed in the silicon layer around the MOS capacitor. 2. The device according to claim 1, wherein the insulating layer is an oxide film, and the silicon layer is a silicon semiconductor layer. 3. The device according to claim 1, wherein the insulator is a glass substrate or a quartz substrate, and the silicon layer is an amorphous silicon layer or a polysilicon layer. 4. A step of forming a gate electrode at a predetermined position on a silicon layer via a gate oxide film. 4. The step of forming a gate electrode on the silicon layer below the gate electrode. A method for manufacturing a substrate evaluation element, comprising a step of forming a diffusion layer of a type opposite to a type. 5. The method according to claim 4, wherein the process for forming the diffusion layer is a thermal diffusion doping process. 6. The method according to claim 4, wherein the process for forming the diffusion layer is an ion implantation process.