JP2006135097A - Method and element for evaluating semiconductor substrate - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method and an element for evaluating the quality of a semiconductor substrate conveniently in a short time with high precision without forming an isolation oxide film, metal wiring or the like on the surface of the substrate when a semiconductor substrate having a semiconductor layer formed on an insulator or an insulating layer is evaluated. <P>SOLUTION: The method for evaluating a semiconductor substrate having a semiconductor layer formed on an insulator or an insulating layer comprises a step for forming a gate oxide film on the semiconductor layer, forming a gate conductive film on the gate oxide film, forming at least two adjacent dielectric breakdown electrodes and one evaluation electrode from the gate conductive film and then forming a low resistance layer at least on the semiconductor layer located between the dielectric breakdown electrodes, and a step for dielectrically breaking a part of the gate oxide film by applying a field between the dielectric breakdown electrodes. Subsequently, electrical characteristics of the gate oxide film between the dielectric breakdown electrode and the evaluation electrode are evaluated. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a method for producing and evaluating a substrate evaluation element for evaluating a semiconductor substrate in which a semiconductor layer is formed on an insulator or an insulating layer, and a semiconductor substrate evaluation element. The present invention relates to a method for evaluating electrical characteristics of a semiconductor layer and an evaluation element.

  For example, there is a silicon substrate as a semiconductor substrate that is widely used as an integrated circuit. However, with the increase in system speed and integration and the development of mobile terminals, semiconductor devices with higher speed and lower power consumption are even more popular. It has been demanded. Under such circumstances, an SOI wafer having an SOI (Silicon On Insulator) structure in which a silicon layer is formed on an insulator or an insulating layer corresponds to a higher speed and lower power consumption of the device. By using wafers, devices can be fabricated without significantly changing existing equipment and processes for bulk wafer device processes that do not have an SOI structure, resulting in higher device speed and lower power consumption. Is attracting attention as something that can be easily achieved.

  On the other hand, as a quality evaluation method for a normal silicon substrate (bulk wafer) having no SOI structure, a GOI (Gate Oxide Integrity) method is widely used. In the GOI method, for example, as shown in a plan view and a cross-sectional view in FIG. 4, a surface of a silicon substrate 11 to be evaluated is oxidized to form a gate oxide film 12, and a metal electrode is formed on the gate oxide film 12. 13 (or polysilicon electrode) is formed, and a MOS capacitor having a MOS (Metal Oxide Semiconductor) structure is fabricated as an evaluation element. For the MOS capacitor thus manufactured, the back surface of the silicon substrate 11 is connected to the ground, and a voltage is applied to the metal electrode 13 so that the silicon substrate 11 is on the storage side. For example, when the conductivity type of the silicon substrate 11 is P type, the silicon substrate 11 becomes the accumulation side by applying a negative voltage. Thus, the dielectric breakdown behavior of the gate oxide film 12 is measured by applying a voltage.

  At this time, if there is no crystal defect or impurity such as COP (Crystal Originated Particles) in the silicon substrate, the dielectric breakdown of the gate oxide film exhibits intrinsic breakdown characteristics inherent to the oxide film itself. However, when crystal defects or the like are present on the substrate, the insulating properties as the original insulating film are deteriorated, so that the oxide film breakdown electric field strength is lowered when the dielectric breakdown characteristics of the gate oxide film are measured. Therefore, the quality of the silicon substrate 11 can be evaluated by measuring the dielectric breakdown characteristics of the gate oxide film 12.

  On the other hand, when an SOI wafer is evaluated by the conventional GOI method, for example, as shown in FIG. 5, the SOI wafer 19 is a buried oxide film (BOX oxide film) that is an insulator between a support substrate 18 and a silicon layer 16. Since 17 is present, electrical contact cannot be made from the back surface of the wafer, and a ground for making electrical contact must be separately formed on the wafer front side. In order to solve such a problem, as shown in FIG. 5, in addition to the gate oxide film 12 ′ and the metal electrode 13 ′, the surface of the silicon layer 16 can be electrically contacted on the wafer surface side. A method of forming a metal capacitor 14 as an evaluation element by forming a metal wiring 14 and an isolation oxide film 15 that insulates these metal wirings is disclosed (for example, see Patent Document 1 and Non-Patent Document 1). However, this MOS capacitor has a very complicated structure as compared with the MOS capacitor for bulk wafer evaluation shown in FIG.

  As another solution, a BOX oxide film is partially removed by etching, and a polysilicon layer doped with a dopant to reduce the resistance value is embedded in the portion from which the BOX oxide film has been removed. Although there is a method in which electrical connection is made and electrical contact can be made from the back side of the substrate (see Patent Document 2), this method requires a complicated process of partially etching the BOX oxide layer. is there.

  Thus, conventionally, the fabrication of a MOS capacitor for evaluating the silicon layer of an SOI wafer by the GOI method requires a long and complicated process, and it takes a long time to complete the evaluation. Also, in terms of equipment, in addition to an apparatus necessary for manufacturing an element for bulk wafer evaluation, an oxide film for element isolation (hereinafter sometimes referred to as an interlayer insulating film) is formed by a CVD (Chemical Vapor Deposition) method or the like. Equipment, metal (mainly Al) wiring technology, etc. are required, and a simpler evaluation method is desired.

JP 2002-359362 A Japanese Patent Laid-Open No. 10-335405 IEEE Trans. on Electron Dev. , Vol. 48, no. 2, p307 (2001)

  In the present invention, when evaluating a semiconductor substrate having a semiconductor layer formed on an insulator or an insulating layer, it is not necessary to form an isolation oxide film or a metal wiring on the surface of the substrate, and the quality of the semiconductor substrate can be simplified. It is another object of the present invention to provide a method and a semiconductor substrate evaluation element that can be evaluated with high accuracy in a short time.

  In order to achieve the above object, the present invention is a method for evaluating a semiconductor substrate having a semiconductor layer formed on an insulator or an insulating layer, wherein a gate oxide film is formed on the semiconductor layer, and the formed gate is formed. A gate conductive film is formed on the oxide film, and at least two adjacent dielectric breakdown electrodes and one evaluation electrode are formed from the formed gate conductive film, and at least positioned between the dielectric breakdown electrodes. Performing a step including a step of forming a low-resistance layer on the semiconductor layer and a step of applying a electric field between the dielectric breakdown electrodes to dielectrically break down a part of the gate oxide film, and then performing the dielectric breakdown electrodes A method for evaluating a semiconductor substrate is provided, wherein an electrical characteristic of the gate oxide film between the electrode and the evaluation electrode is evaluated.

Thus, when evaluating a semiconductor substrate, first, a gate oxide film and a gate conductive film are sequentially formed on the semiconductor layer, and at least two adjacent dielectric breakdown electrodes and one evaluation electrode are formed by patterning the gate conductive film. And an electrode. And after that, a step of forming a low resistance layer at least in the semiconductor layer located between the dielectric breakdown electrodes and a step of dielectrically breaking a part of the gate oxide film by applying an electric field between the dielectric breakdown electrodes Then, the electrical characteristics of the gate oxide film between the dielectric breakdown electrode and the evaluation electrode are evaluated. This eliminates the need for conventional processes and devices for forming a metal wiring such as an interlayer insulating film and aluminum, and processes necessary for patterning. It becomes unnecessary, and the evaluation process is shortened, so that quick evaluation can be performed at low cost. Further, by including a step of forming a low resistance layer in the semiconductor layer, the connection resistance between the electrodes can be lowered regardless of the resistivity and thickness of the semiconductor layer, so that highly accurate evaluation can be performed.
It should be noted that the effect of the present invention can be obtained by performing any of the steps of forming the low resistance layer and the step of dielectric breakdown of a part of the gate oxide film first.

In this case, it is preferable that the resistance value of the low resistance layer to be formed is 5 kΩ or less.
Thus, if the resistance value of the low resistance layer is 5 kΩ or less, not only the contact resistance between the semiconductor layer and the electrode but also the connection resistance between the electrode and the electrode is sufficiently small, requiring complicated processes and expensive equipment. Therefore, highly accurate evaluation can be performed more reliably. The resistance value of the low resistance layer is preferably low. However, if the resistance value is too low, the doping amount of the dopant becomes too large and affects the characteristics of the evaluation element itself.

Further, a semiconductor substrate having a thickness of the semiconductor layer of 5 μm or less can be used.
As described above, even when a semiconductor substrate having a thin semiconductor layer thickness of 5 μm or less and having a high connection resistance between the electrode and the electrode as well as a contact resistance between the semiconductor layer and the electrode is usually used in the present invention. In this evaluation method, the connection resistance can be lowered due to the presence of the low resistance layer, so that a highly accurate evaluation can be performed without requiring a complicated process or expensive equipment.

In addition, a semiconductor substrate in which the semiconductor layer is made of silicon can be evaluated.
In this way, it is possible to evaluate a semiconductor layer made of silicon, which is a material that is widely used for the formation of semiconductor elements, so that the evaluation results can be used widely and effectively for product quality investigation and assurance of various semiconductor elements. can do.

The low resistance layer is preferably formed using a thermal diffusion method.
In this way, if the low resistance layer is formed using the thermal diffusion method, the dopant also enters the portion immediately below the outer periphery of the electrode, the contact resistance between the electrode and the semiconductor layer can be reliably reduced, and the dopant is relatively inexpensive. Can be doped to form a low resistance layer.

  The present invention also relates to an element for evaluating a semiconductor substrate, comprising a semiconductor substrate having a semiconductor layer formed on an insulator or an insulating layer, a gate oxide film formed on the semiconductor layer, and the gate oxide film. And at least two adjacent dielectric breakdown electrodes made of a conductive film and one evaluation electrode, and the semiconductor layer has at least a low resistance layer formed between the dielectric breakdown electrodes. An element for evaluating a semiconductor substrate is provided (claim 6).

  As described above, the semiconductor substrate on which the semiconductor layer is formed on the insulator or the insulating layer, the gate oxide film formed on the semiconductor layer, and at least the adjacent conductive film formed on the gate oxide film. Conventionally, it is an element for evaluating a semiconductor substrate that includes two dielectric breakdown electrodes and one evaluation electrode, and the semiconductor layer has at least a low resistance layer formed between the dielectric breakdown electrodes. In addition, since it can be manufactured without using the process and apparatus for forming metal wiring such as an interlayer insulating film and aluminum, and the process necessary for patterning, the cost for introducing and maintaining the equipment is not required. Since the evaluation process can be shortened, it becomes a semiconductor substrate evaluation element that can be promptly evaluated at low cost. In addition, since the low resistance layer is formed and the connection resistance between the electrodes is low regardless of the resistivity and thickness of the semiconductor layer, the semiconductor substrate evaluation element can be evaluated with high accuracy. .

In this case, it is preferable that the low resistance layer has a resistance value of 5 kΩ or less.
Thus, if the resistance value of the low resistance layer is 5 kΩ or less, the contact resistance between the semiconductor and the electrode is sufficiently small, and the device can be evaluated with high accuracy. The resistance value of the low resistance layer is preferably low. However, if the resistance value is too low, the doping amount of the dopant becomes too large and affects the characteristics of the evaluation element itself.

The electrode is preferably made of polysilicon.
Thus, if the electrode is made of polysilicon, it is easy to process and is easy to form.

The semiconductor layer may have a thickness of 5 μm or less.
As described above, even if the semiconductor layer is as thin as 5 μm or less, and the connection resistance between the electrodes is usually high, the semiconductor substrate evaluation element of the present invention has a low connection resistance due to the presence of the low resistance layer. Therefore, highly accurate evaluation can be performed without requiring a complicated process or expensive equipment.

The semiconductor layer is preferably made of silicon.
In this way, if it is made of silicon that is widely used for semiconductor element manufacturing, the evaluation results of this evaluation element should be widely and effectively used for the investigation and guarantee of the product quality of various semiconductor elements. Can do.

Further, it is preferable that the gate oxide film has a dielectric breakdown portion formed between the dielectric breakdown electrodes.
As described above, if the gate oxide film has a breakdown portion formed between the breakdown electrodes, the characteristics can be evaluated quickly and at low cost by connecting the breakdown electrode to the ground. it can.

  According to the evaluation method of the present invention, when evaluating a semiconductor substrate having a semiconductor layer formed on an insulator or an insulating layer, a conventional process and apparatus for forming a metal wiring such as an interlayer insulating film and aluminum are performed. In addition, since the process necessary for patterning is not required, the cost for introducing and maintaining the equipment is not required, and the evaluation process is shortened, so that quick evaluation can be performed at low cost. Furthermore, by including a step of forming a low resistance layer in the semiconductor layer, not only the contact resistance between the semiconductor layer and the electrode but also the connection resistance between the electrode and the electrode can be lowered regardless of the resistivity and thickness of the semiconductor layer. Highly accurate evaluation can be performed.

  In addition, since the element for evaluating a semiconductor substrate of the present invention can be produced without using a conventional process and apparatus for forming a metal wiring such as an interlayer insulating film or aluminum, and a process necessary for patterning, Therefore, the cost for introducing and maintaining the equipment is unnecessary, and the evaluation process is shortened, so that the element for semiconductor substrate evaluation capable of rapid evaluation at low cost is obtained. In addition, a low-resistance layer is formed, and not only the contact resistance between the semiconductor layer and the electrode but also the connection resistance between the electrode and the electrode is low regardless of the resistivity and thickness of the semiconductor layer. It becomes the element for semiconductor substrate evaluation which can be performed.

Hereinafter, the present invention will be described in detail.
As described above, for example, a MOS capacitor for evaluating a silicon layer of an SOI wafer by the GOI method requires a long and complicated process, and it takes a long time to complete the evaluation. In addition to equipment necessary for manufacturing an element for bulk wafer evaluation, facilities for CVD method and metal wiring technology for forming an interlayer insulating film for element isolation are also required. Another method requires a complicated process of partially etching the BOX oxide layer. Therefore, a simpler evaluation method is desired.

  Therefore, the present inventors have made a gate oxide film by applying an electric field between the electrodes of two adjacent MOS capacitors after fabricating a MOS capacitor on an SOI wafer as a simpler, lower cost and quick evaluation method. After dielectric breakdown occurs in a part of the electrode, connect one of the electrodes to the ground, and evaluate the electrical characteristics of the gate oxide film between the other electrode and the electrode of the other MOS capacitor that was not used for dielectric breakdown I came up with a way to do.

As a result of further studies on this method, the present inventors have found that in the above method, not only the contact resistance between the silicon layer and the electrode but also the connection resistance between the electrode and the electrode is increased, and the evaluation may not be performed correctly. I found out. For example, when an SOI wafer having a silicon layer thickness of 5 μm or less is evaluated, the influence of the BOX oxide film increases, so that not only the contact resistance between the silicon layer and the electrode but also the connection resistance between the electrode and the electrode In some cases, it was too large to be evaluated with high accuracy.
Therefore, in the above method, the present inventors form a low resistance layer at least in the semiconductor layer located between the electrodes causing the dielectric breakdown before or after the step of causing the dielectric breakdown after manufacturing the MOS capacitor on the SOI wafer. As a result, the present inventors completed the present invention by conceiving that the connection resistance can be lowered regardless of the thickness of the semiconductor layer and its resistivity, and that highly accurate evaluation can be performed.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, but the present invention is not limited thereto.
FIG. 1 is a schematic cross-sectional explanatory view showing an example of a semiconductor substrate evaluation element according to the present invention when an SOI wafer in which a semiconductor layer is a silicon layer (SOI layer) is used. The semiconductor substrate evaluation element 1 includes an SOI wafer 5 in which an SOI layer 4 is formed on a BOX oxide film 3 on a support substrate 2, a gate oxide film 6 formed on the SOI wafer 5, and a gate oxide film 6. At least two adjacent dielectric breakdown electrodes 7a and 7b and one evaluation electrode 8 formed above are provided, and the SOI layer 4 has at least a low resistance layer 9 between the dielectric breakdown electrodes 7a and 7b. It is formed. Here, the dielectric breakdown electrode is an electrode used for applying an electric field for dielectric breakdown of a part of the gate oxide film before the evaluation of the wafer, and the evaluation electrode is evaluated during the evaluation of the wafer. It is an electrode used in order to apply the electric field for. Evaluation terminals 10a and 10b are connected to the evaluation electrode 8 and one dielectric breakdown electrode, for example, the dielectric breakdown electrode 7a, and the other dielectric breakdown electrode 7b is connected to the ground. Alternatively, the dielectric breakdown electrode 7b may be connected to the evaluation terminal 10b, and the dielectric breakdown electrode 7a may be connected to the ground. The low resistance layer 9 may be formed at a place other than between the dielectric breakdown electrodes 7a and 7b, for example, between the dielectric breakdown electrode 7b and the evaluation electrode 8 as shown in FIG. Three or more dielectric breakdown electrodes may be formed as long as they are adjacent to each other, and two or more evaluation electrodes may be formed. In addition, since it is possible to evaluate a semiconductor layer made of silicon, which is a material generally used for manufacturing semiconductor elements, the evaluation results of this evaluation element are used to investigate and guarantee the product quality of various semiconductor elements. It can be used widely and effectively.

  If the resistance value of the low resistance layer 9 is 5 kΩ or less, the contact resistance between the SOI layer 4 and the electrodes 7a, 7b, 8 is sufficiently small, and the dielectric breakdown electrodes (7a, 7b) and the evaluation The connection resistance between the electrodes (8, 7a) is sufficiently small, and the device can be evaluated with high accuracy. The resistance value of the low resistance layer is preferably lower. However, if the value is too low, the doping amount of the dopant becomes too large and affects the characteristics of the evaluation element itself. Therefore, for example, the lower limit is preferably about 100Ω. .

The electrodes 7a, 7b, and 8 are not particularly limited as long as they are made of a conductive film. However, if they are made of polysilicon, the electrodes 7a, 7b, and 8 are easy to process and can be easily formed.
Also, the SOI layer 4 can have a thickness of 5 μm or less. If the semiconductor layer such as the SOI layer is as thin as 5 μm or less, the contact resistance / connection resistance is usually high due to the influence of the BOX oxide film, etc., but the semiconductor substrate evaluation element of the present invention has a low resistance layer. Since it is formed and has low contact resistance and connection resistance, highly accurate evaluation can be performed without requiring complicated processes and expensive equipment.

  When the SOI layer 4 is evaluated using the semiconductor substrate evaluation element 1, an electric field is applied to the dielectric breakdown electrodes 7a and 7b, and a part of the gate oxide film between the electrodes is dielectrically broken, not shown. It is assumed that a dielectric breakdown part has been formed. An element in which a dielectric breakdown portion is formed in this manner can easily obtain an electrical contact without forming an interlayer insulating film or a metal wiring by using expensive equipment or complicated processes, and can be obtained quickly and at low cost. Characteristic evaluation can be performed.

  Next, a method for producing such a semiconductor substrate evaluation element and evaluating an SOI wafer will be described. 2A to 2F are process diagrams showing an example of an SOI wafer evaluation method according to the present invention.

  First, an SOI wafer is prepared as a pre-process. Since an SOI wafer having a semiconductor layer made of silicon can be evaluated in this way, the evaluation result can be widely and effectively used for investigation and guarantee of product quality of various semiconductor elements. The SOI wafer is not particularly limited, but can be used to evaluate an SOI wafer having an SOI layer thickness of 5 μm or less. As described above, even when using an SOI wafer having a thickness as thin as 5 μm or less and usually having a high contact resistance / connection resistance with an electrode due to the influence of a BOX oxide film, the contact resistance / Since the connection resistance can be lowered, highly accurate evaluation can be performed without requiring a complicated process or expensive equipment. Particularly, in recent years, the thickness of the SOI layer has been made thinner, and the present invention is particularly effective for evaluation of a thin SOI layer of 1 μm or less.

Next, as shown in FIG. 2A, the SOI wafer is oxidized by a normal method such as thermal oxidation to form a gate oxide film 6 on the SOI layer. The thickness of the gate oxide film is not particularly limited, and is usually 25 nm. In particular, when the SOI layer thickness is 100 nm or less, the thickness of the gate oxide film is about 8 nm.
Next, as shown in FIG. 2B, a gate conductive film is formed over the gate oxide film. The gate conductive film is generally a polysilicon film, and is deposited using, for example, a CVD method. This polysilicon film is generally doped with phosphorus to lower the resistance value. The phosphorus doping method is not particularly limited, and may be performed by a thermal diffusion method or the like after deposition of the polysilicon film, but a Doped Poly-Si method in which phosphorus is also doped at the time of deposition of the polysilicon film can be used.

  Next, as shown in FIG. 2C, an electrode pattern is formed from this polysilicon film by photolithography and etching. At this time, at least two adjacent dielectric breakdown electrodes 7a and 7b and one evaluation electrode 8 are formed. Thus, a plurality of MOS capacitors having a MOS structure in which a gate oxide film and a polysilicon electrode are sequentially stacked on the SOI layer are formed.

Next, as shown in FIG. 2D, a low resistance layer is formed by doping a dopant into at least the SOI layer located between the dielectric breakdown electrodes using the formed electrode as a mask. In this case, if the resistance value of the low resistance layer is 5 kΩ or less, the contact resistance between the SOI layer and the electrode is sufficiently small, the connection resistance between the electrode and the electrode is also sufficiently small, and complicated processes and expensive equipment are required. Therefore, highly accurate evaluation can be performed more reliably. For example, the lower limit of the resistance value of the low resistance layer is preferably about 100Ω. The method of forming the low resistance layer is not particularly limited. For example, if the thermal diffusion method in which phosphorous glass (POCl ₃ ) is deposited on the wafer surface and annealed in a nitrogen gas atmosphere is performed, then the low resistance layer is formed, for example, rather than by ion implantation. Low cost and high productivity are preferable.
Although a gate oxide film is formed between the MOS capacitors, since it is a thin oxide film, it is possible to sufficiently diffuse the dopant into the SOI layer even if phosphorus glass is deposited thereon.

  After the diffusion of the dopant, the deposited phosphorus glass is removed with, for example, a 2.5% HF aqueous solution. At this time, care must be taken not to etch the gate oxide film around the electrode in order to perform highly accurate measurement.

Next, as shown in FIG. 2 (E), an electric field is applied between two adjacent dielectric breakdown electrodes 7a and 7b to cause a partial breakdown of the gate oxide film 6 to make electrical contact. . The application of this electric field is not particularly limited as long as a part of the gate oxide film can be broken down, and a method of applying a constant voltage or current until a part of the gate oxide film is broken may be used. This contact resistance needs to be lowered sufficiently, and it is more preferable to apply as much electrical stress as possible. It is preferable to apply an electrical stress so that the resistance between the two electrodes is 1 kΩ or less. Thus, the influence on the measurement can be reduced by setting the resistance to 1 kΩ or less.
Note that either the step of forming the low resistance layer shown in FIG. 2D and the step of dielectric breakdown of the gate oxide film shown in FIG. 2E may be performed first.

  Next, as shown in FIG. 2F, the electrical characteristics of the gate oxide film between the dielectric breakdown electrode and the evaluation electrode are evaluated. In this evaluation, GOI measurement is performed using one of the MOS capacitors having breakdown and an undestructed MOS capacitor. A MOS capacitor that has already been destroyed has a sufficiently low resistance, and one electrode of this MOS capacitor is connected to the ground to enable highly accurate measurement. In the case of a P-type wafer, a voltage is applied to the wafer surface so as to be positively charged, that is, depleted and inverted.

  With the evaluation method described above, the quality of the SOI layer of the SOI wafer can be accurately evaluated. Moreover, the conventional process and apparatus for forming a metal wiring such as an interlayer insulating film and aluminum and the process necessary for patterning can be eliminated, so that the cost for introducing and maintaining the equipment is not required. In addition, since the evaluation process is shortened, a quick evaluation can be performed at a low cost.

EXAMPLES Hereinafter, although an Example demonstrates this invention further in detail, it cannot be overemphasized that this invention is not limited to this.
(Example)
A bonded SOI wafer having a P-type conductivity and a diameter of 200 mm was used as a sample for characteristic evaluation. The dopant of this P-type wafer is boron. At this time, the thickness of the SOI layer was 70 nm, and the thickness of the BOX oxide film was 145 nm.

  Next, the SOI wafer is subjected to a thermal oxidation treatment in a dry oxygen atmosphere at 900 ° C. for about 10 minutes to form a gate oxide film having a thickness of 8 nm on the SOI layer. Phosphorus is formed on the gate oxide film by a CVD method. A polysilicon layer doped with was deposited. At this time, the thickness of the polysilicon layer was set to about 300 nm, and the phosphorus doping amount was set to about 25Ω / □ in terms of sheet resistance.

Next, after photolithography was performed on this polysilicon layer, wet etching was performed using hydrofluoric acid to form two adjacent dielectric breakdown electrodes and one evaluation electrode, thereby producing a MOS capacitor. All the electrodes had an electrode area of 8 mm ² . In order to remove the oxide film formed on the back surface of the SOI wafer, a resist is applied to the gate oxide film and the electrode on the front surface side of the SOI wafer to protect it, and the back surface is wet etched with a dilute HF aqueous solution. Processed.

Thereafter, phosphorus glass is deposited on the surface of the SOI wafer at 750 ° C. for 30 minutes, followed by annealing at 1000 ° C. for 1 hour in a nitrogen gas atmosphere, and thermal diffusion of phosphorus is performed on the SOI layer to form a low resistance layer. . The resistance value of the formed low resistance layer was about 500Ω.
Next, the phosphorus glass deposited using 2.5% HF aqueous solution was removed. The etching rate at this time was 0.3 nm / sec, and etching was carefully performed using a monitor wafer so that the gate oxide film around the electrode was not etched.

Next, the gate oxide film was subjected to dielectric breakdown by applying a stress current between the dielectric breakdown electrodes using a tester connected to a full auto prober. The stress current was constant at 50 mA, and the application time was 3 seconds. Each electrode had an electrode area of 8 mm ² and a resistance between the electrodes of about 400Ω. In addition, the prober and wiring which used the measure against noise were used.

Finally, one of the dielectric breakdown electrodes was connected to the ground, a voltage was applied between the evaluation electrode and the other of the dielectric breakdown electrodes, and the SOI layer was evaluated by the GOI method. A voltage ramp-up method was used for the voltage application at this time. The application conditions at that time were an averaging time of 20 msec and a step voltage height of 0.25 MV / cm, and the averaging after the voltage step increase. The time was 200 msec.
Such measurement was performed on 16 SOI wafers manufactured under the same conditions. The graph of the IV characteristic obtained at this time is shown in FIG. The IV characteristic curves of all the wafers almost coincided with each other, and it was confirmed that highly accurate characteristic evaluation was performed.

The present invention is not limited to the above embodiment. The above-described embodiment is an exemplification, and the present invention has substantially the same configuration as the technical idea described in the claims of the present invention, and any device that exhibits the same function and effect is the present invention. It is included in the technical scope of the invention.
For example, although the SOI wafer has been described in the above embodiment, the present invention may be applied to a semiconductor substrate in which a semiconductor layer is formed on another insulator, such as an SGOI (SiGe On Insulator) wafer or a GOI (Ge On Insulator) wafer. The evaluation method and the evaluation element of the invention can be applied.

It is the cross-sectional schematic explanatory drawing which showed an example of the element for semiconductor substrate evaluation according to this invention about the case where the SOI wafer whose semiconductor layer is a silicon layer (SOI layer) is used. It is process drawing which shows an example of the evaluation method of the SOI wafer according to this invention. It is a grab which shows the IV characteristic of the SOI wafer in an Example. It is explanatory explanatory drawing explaining GOI method, (a) is a top view, (b) shows sectional drawing. It is the cross-sectional schematic explaining the method of evaluating an SOI wafer by the conventional GOI method.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Element for semiconductor substrate evaluation, 2 ... Support substrate, 3 ... BOX oxide film, 4 ... SOI layer,
5 ... SOI wafer, 6 ... Gate oxide film, 7a, 7b ... Dielectric breakdown electrode,
8 ... Evaluation electrode, 9 ... Low resistance layer, 10a, 10b ... Evaluation terminal,
DESCRIPTION OF SYMBOLS 11 ... Silicon substrate, 12, 12 '... Gate oxide film, 13, 13' ... Metal electrode,
14 ... Metal wiring, 15 ... Isolation oxide film, 16 ... Silicon layer,
17 ... buried oxide film (BOX oxide film), 18 ... support substrate,
19 ... SOI wafer.

Claims (11)

  A method for evaluating a semiconductor substrate having a semiconductor layer formed on an insulator or an insulating layer, wherein a gate oxide film is formed on the semiconductor layer, a gate conductive film is formed on the formed gate oxide film, Forming at least two adjacent dielectric breakdown electrodes and one evaluation electrode from the formed gate conductive film, and then forming a low resistance layer on at least the semiconductor layer located between the dielectric breakdown electrodes And a step of applying an electric field between the dielectric breakdown electrodes to cause dielectric breakdown of a part of the gate oxide film, and then the gate between the dielectric breakdown electrode and the evaluation electrode A method for evaluating a semiconductor substrate, comprising evaluating electrical characteristics of an oxide film.   2. The semiconductor substrate evaluation method according to claim 1, wherein a resistance value of the low resistance layer to be formed is set to 5 k [Omega] or less.   The semiconductor substrate evaluation method according to claim 1, wherein a semiconductor substrate having a thickness of the semiconductor layer of 5 μm or less is used.   The semiconductor substrate evaluation method according to claim 1, wherein the semiconductor layer is made of silicon.   The method for evaluating a semiconductor substrate according to claim 1, wherein the low resistance layer is formed by a thermal diffusion method.   An element for evaluating a semiconductor substrate, comprising a semiconductor substrate having a semiconductor layer formed on an insulator or an insulating layer, a gate oxide film formed on the semiconductor layer, and a conductive film formed on the gate oxide film. It comprises at least two adjacent dielectric breakdown electrodes made of a film and one evaluation electrode, and the semiconductor layer has at least a low resistance layer formed between the dielectric breakdown electrodes. Semiconductor substrate evaluation element.   The element for evaluating a semiconductor substrate according to claim 6, wherein the low resistance layer has a resistance value of 5 kΩ or less.   The element for evaluating a semiconductor substrate according to claim 6, wherein the electrode is made of polysilicon.   The element for evaluating a semiconductor substrate according to claim 6, wherein the semiconductor layer has a thickness of 5 μm or less.   The element for evaluating a semiconductor substrate according to claim 6, wherein the semiconductor layer is made of silicon.   The element for evaluating a semiconductor substrate according to claim 6, wherein the gate oxide film has a dielectric breakdown portion formed between the dielectric breakdown electrodes.

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