JP3159249B2 - Diffusion check transistor for measurement - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a semiconductor device,
In particular , diffusion check tracing for bipolar transistor measurements.
Transistor and a semiconductor device using the measurement result .

[0002]

2. Description of the Related Art FIG. 15 shows a conventional transistor in which an emitter region is formed by impurity diffusion from polysilicon. The silicon bipolar transistor having the polysilicon emitter structure is excellent in that the current amplification factor is increased, and is currently the mainstream.

A conventional semiconductor device and a method for manufacturing the same will be described with reference to the drawings.

[0004] Bipolar Semiconductor Devices by David J. Ruleston (David J. Roul
ston, “Bipolar Semiconductor Devices,” McGraw-H
ill, pp. 343-345 (1990).

FIG. 15 is a sectional view showing an example of the first conventional semiconductor device. This is a sectional view of a transistor called Super Self-aligned process Technology (abbreviated as SST), which is developed by Sakai et al. Of NTT, in the order of the manufacturing process. Here, an opening for the emitter is formed, and after depositing undoped polysilicon on the entire surface of the wafer, arsenic is added to the polysilicon by an ion implantation method, and a region within a certain distance from the emitter opening is processed by photolithography and dry etching. Leave N ⁺ type polysilicon on top. Further, by performing a heat treatment, arsenic is diffused from polysilicon to single crystal silicon to form an emitter.

Next, as a second prior art, a bipolar transistor having an intrinsic base layer formed by an epitaxial growth method will be described.

[0007] A second conventional semiconductor device and a method of manufacturing the same are described in Self-Aligned Selective MBE Technology for High Performance Bipolar Transistors by Sato et al. (International Electron Device Meeting (IEDM)) 1990, p.
p. This will be described with reference to 607-610.

FIG. 16 is a sectional view of an example of the second conventional semiconductor device. On the P ^- type silicon substrate 1, N ⁺
Type buried layer 2, and further thereon an N ⁻ type silicon epitaxial layer 3, a LOCOS oxide film 1 for element isolation
4, and an N ⁺ -type collector lead-out region 15 are formed. The silicon substrate 100 is configured as described above.
The surface of the silicon substrate 100 is covered with a silicon oxide film 6.

The silicon oxide film 6 has an opening 101 for exposing a part of the silicon collector layer 3 constituting the collector region and forming a base, and an opening 102 for exposing the collector lead-out region 15. .

On the silicon oxide film 6, a P ⁺ -type base electrode polysilicon film 7 is selectively formed. The polysilicon film 7 protrudes horizontally from the edge of the opening 101 into the opening. A P-type polysilicon layer 10 is formed from the lower surface of the protruding portion to the silicon collector layer 3 constituting the collector region.

On the other hand, in the exposed portion of the silicon collector layer 3, a P-type base region 9 is formed of single crystal silicon by selective epitaxial growth. The polysilicon layer 10 and the P-type base region 9 are in contact with each other.

In the opening 102, an N-type polysilicon layer 21 is formed.
Are formed and are in contact with the collector lead-out region 15. The P-type base region 9 and the polysilicon layers 7 and 10 are covered with the silicon nitride film 8 and the silicon oxide film 11 except for the emitter formation portion.
An N-type emitter region 16 made of single crystal silicon is formed in an exposed portion of the P-type base region 9. Aluminum-based emitter electrode 18b, base electrode 18a, and collector electrode 18c are in contact with emitter polysilicon 17, polysilicon layers 7 and 8, respectively.

This second prior art is also the same as the first prior art in that the emitter polysilicon is processed by a photolithography step and an etching step.

[0014]

In the first and second conventional semiconductor devices (patterning the emitter polysilicon) and the method of manufacturing the same, N as an emitter electrode is used.
⁺ -Type polysilicon is deposited on the entire surface of the silicon substrate, photoresist is patterned on the polysilicon, and the polysilicon is patterned by dry etching. As a result, a step in the thickness of the emitter polysilicon is formed immediately above the emitter.

[0015] However, it is difficult to pattern fine dimensions by a photolithography process when there are irregularities compared to a flat surface. That is, it is advantageous to use light having a short wavelength to process fine dimensions, but light having a short wavelength has a shallow focal depth. Therefore, it is not suitable for miniaturization as the step of the surface unevenness is large.

Therefore, as a method of not increasing the level difference just above the emitter, there is a structure in which the emitter polysilicon exists only inside the emitter opening (hereinafter, this structure is called a plug structure). There are two ways to realize this structure.

As a first method of forming a plug structure,
After the emitter polysilicon is deposited, there is a method of etching back by a dry etch method. Further, a photolithography process for patterning the emitter polysilicon can be omitted, which is advantageous in terms of cost. However, according to this forming method, the characteristics cannot be checked because the polysilicon deposited on the large opening is completely removed during the etch back.

As a second method, polysilicon is deposited by a selective crystal growth method, and arsenic is added by an ion implantation method to form an emitter polysilicon. According to this forming method, the polysilicon is formed only in the opening on the intrinsic base, so that there is no step of the emitter polysilicon described above. However, according to this method, the emitter size of a transistor used as a product used inside the circuit is on the order of several μm, whereas the emitter size of a diffusion check transistor for checking characteristics used in a manufacturing stage is 100 μm. A size around the corner is required, and the transistor characteristics of both do not always match. The reason is,
If the dimensions of the emitter are significantly different, arsenic is not sufficiently added to the inside of the fine opening to the bottom of the polysilicon at the time of ion implantation, and as a result, the state of diffusion of the emitter impurity (here, arsenic) differs in the size of the opening. Will change.

Recent high-performance bipolar transistors include:
In order to realize the high speed, the base junction depth X _JB ,
And the emitter junction depth X _JE is extremely shallow.
For example, the IEEE Ripple E International Electron Device Meeting (IEEE International Elect
ron Devices Meeting (IEDM)) 1989 pp. 221
According to -224, it is reported that the base depth is 0.09 μm. As a method of forming the emitter, an emitter region is usually formed by diffusing an N-type impurity such as arsenic or phosphorus from the emitter polysilicon from the surface of the single crystal base region by performing a heat treatment (hereinafter referred to as "emitter indentation"). I do. This diffusion is significantly affected by the state of the interface between the single crystal base and the emitter polysilicon.
In other words, a natural oxide film having a thickness of about 10 Å exists on the surface of the single crystal base before the polysilicon is deposited. The natural oxide film thickness varies from wafer to wafer and the film thickness uniformity within the same wafer surface is poor. Therefore, in the emitter indenting step, the characteristics are measured by injecting only one emitter as a test (hereinafter, the transistor to be measured is referred to as "diffusion check transistor"), and from the result, the remaining wafers of the same lot are indented. An approach is taken.

However, according to the prior art method of selectively forming the emitter polysilicon described above, if the emitter is formed in a region having a size that can be probed (for example, 80 μm ² or more), the state of the emitter pressing can be monitored. Measurement is possible. However, the size of the emitter of the transistor as a product actually used inside the circuit is 1
The transistor for monitoring is several tens of μm, whereas the diffusion of the emitter impurity is different from that of μm or less. Therefore, it is difficult to estimate the transistor inside the circuit by measuring the diffusion check transistor. The reason why the characteristics are different between the two is not exactly known, but the state of stress generation due to the difference in the thermal expansion coefficient between the insulating film (for example, a silicon nitride film or a silicon oxide film) surrounding the emitter polysilicon and the polysilicon. Is presumed to be different due to the difference in

Therefore, it is necessary to perform a diffusion check on a transistor having an emitter of the same size as a transistor used inside the circuit. However, in this case, there is a problem described below.

That is, the first problem is that the transistor characteristics cannot be measured in the course of the process.

The reason is that, in a transistor having a conventional structure, unless the emitter polysilicon is patterned by a combination of a lithography step and dry etching, a dimension (dimension of about 1 μm) that can be probed from the emitter of a transistor having a fine emitter (dimension of about 1 μm). For example, 100μ
it can not be formed to the electrode pads of the m ² or more).

An object of the present invention is to produce a transistor having a structure in which the transistor characteristics of a bipolar transistor having an emitter polysilicon structure embedded in a plug shape inside a fine-sized emitter can be measured immediately after the emitter is pushed. It is in.

[0025]

On the other hand, according to the present invention, a groove having a size approximately equal to the size of the emitter is formed in the green film, and the emitter polysilicon is buried in the groove to be drawn out. By connecting this lead-out portion to a large-area N-type single-crystal silicon region electrically separated from the collector, a diffusion check transistor is manufactured without a photolithography step.

According to this method, a photolithography process for processing the emitter polysilicon can be omitted, thereby realizing a low cost and improving the flatness immediately above the emitter, thereby promoting finer wiring processing.

[0027]

Next, a first embodiment of the present invention will be described with reference to the drawings.

In this embodiment, an npn-type bipolar transistor will be described. However, it goes without saying that the present invention can be applied to a pnp-type bipolar transistor.

FIG. 1A is a longitudinal sectional view of a first embodiment of a diffusion check transistor used for manufacturing a semiconductor device according to the present invention, and FIG. 1B is a plan view thereof. That is, a vertical cross-sectional view and a plan view of a diffusion check transistor for monitoring the indentation of the emitter.

FIG. 2A is a longitudinal sectional view of a transistor having a fine emitter dimension as a product used inside a circuit, and FIG. 2B is a plan view thereof.

A P ⁻ type silicon substrate 1 having a resistivity of 10 to 15 Ωcm, an N ⁺ type buried layer 2 thereon, and N ⁻ type silicon epitaxial layers 3 ₁ and 3 ₂ thereon. A layer 3 is formed, an insulator buried trench 5 for element isolation is formed, and a p ⁺ type buried layer 4 for a channel stopper is provided below the trench.

The surface of N ⁻ type silicon epitaxial layer 3 is covered with silicon oxide film 6.

The silicon oxide film 6, opening to expose a portion of the silicon collector layer 3 ₁ which constitutes the collector region, and an opening 101 for the base form, to reach the buried layer 2 to form a collector lead-out 201 (hereinafter abbreviated as a collector opening). In this figure, the lateral dimension of the collector opening 201 is large enough (eg, 100 μm square) to allow a needle to be used for monitoring.

On the silicon oxide film and on the silicon collector layer constituting the collector region inside the opening 101,
A P ⁺ type base electrode polysilicon film 7 is selectively formed.

On the other hand, the exposed portion of silicon collector layer 3 _1, the opening 101 inside the n-type single crystal silicon,
p-type single crystal silicon intrinsic base region 9, also on the lower surface of the p ⁺ type base electrode polysilicon 7 p ⁺ -type polysilicon layer 10 is formed, the intrinsic base region 9 and the p ⁺ -type polysilicon layer 10 Is connected.

On the side surface of the collector opening 201, an N ⁺ type polysilicon layer 12-b is formed.

Further, (there is about 100μm square dimensions, direct probe can be) outside the silicon collector layer 3 ₁ and another adjacent silicon collector layer 3 emitter tip provided in _second opening 301 of the trench 5 Lateral and intrinsic base 9
There is N ⁺ polysilicon 12-a for an emitter electrode on top.

FIG. 1B shows another base probe opening 401 (the base probe opening is also 100).
It has a size of about μm square and can be directly probed.)

Next, the main steps of the first embodiment of the present invention will be described with reference to the drawings.

A P ^- type (10 to 15 Ωcm resistivity)
0) Arsenic is ion-implanted into the silicon substrate 1 having a plane orientation through a silicon oxide film (not shown) of several hundred angstroms. The implantation conditions include, for example, an energy of 50 kV to 120 kV and a dose of 5E15 to 2E16.
cm ^-2 is appropriate. Next, damage recovery when injected,
1000 ° C. for arsenic activation and forcing
Treat at a temperature of 1150 ° C. Thus, the N ⁺ type buried layer 2 is formed.

Next, after the entire surface of the silicon oxide film is removed, an N ^- type silicon epitaxial layer 3 is formed by an ordinary method. An appropriate growth temperature is 950 ° C. to 1050 ° C., and SiH ₄ or SiH ₂ Cl ₂ is used as a source gas. 5E15 using PH ₃ as doping gas
Contains impurities of ~ 2E16 cm ^-3 and has a thickness of 0.8 μm
〜1.3 μm is appropriate. Thus, the N ^- type silicon epitaxial layer 3 is formed on the buried layer.

Next, trench 5 for element isolation and p ⁺
The channel stopper 4 is formed. First, a thermal oxide film (not shown) having a thickness of 20 nm to 50 nm is formed on the surface of the epitaxial layer 3 and a silicon nitride film (not shown) having a thickness of 70 nm is formed.
and a silicon oxide film 400
nm (not shown). Subsequently, a photoresist (not shown) is patterned by photolithography, and part of a three-layer structure of a silicon oxide film, a silicon nitride film, and a silicon oxide film is removed by dry etching. After removing the photoresist, a trench for trench isolation reaching the silicon substrate 1 is formed using the uppermost silicon oxide film as a mask material.

Next, boron is supplied with an energy of 100 KeV,
The channel stopper buried layer 4 is formed by ion implantation with a dose of 1E13 / cm ^-2 and heat treatment for activation. Next, a green material (polysilicon, silicon oxide film, or the like) is deposited as a filler inside the trench groove. Here, the description will be continued assuming that BPSG is deposited. BPSG (not shown) is set to the groove width (for example, 0.8 μm).
m to 1.5 μm. Here, 1.0 μm is described as an example)
Is deposited twice as thick as that of
C. for 1 hour) to flatten the surface.

The silicon nitride film is removed by etch back of the insulating film and heated phosphoric acid, and HF of the silicon oxide film is removed.
Through the removal by the system solution to expose the surface of the silicon collector layer 3 _1. The conditions for these etch backs are selected so that the final shape is substantially flat.

Next, silicon collector layer 3 ₁ of the surface,
It is covered with a silicon oxide film 6. The film thickness is 50
nm to 200 nm is appropriate, and here 100 nm
It is.

Next, polysilicon is deposited. An appropriate thickness of the polysilicon is 200 nm to 350 nm, and here is 250 nm. Since this polysilicon is used as the base electrode polysilicon in the future, boron is ion-implanted (for example, 30 keV, 5E15 to 2E1).
6 cm ^-2 ) and heat treatment for activation is performed.

Next, after patterning the photoresist, unnecessary polysilicon is removed by dry etching. In this manner, the P ⁺ type base electrode polysilicon 7 is formed.

Subsequently, a silicon nitride film 8 is deposited to a thickness of about 150 nm by LPCVD (the thickness of the silicon nitride film is suitably from 100 nm to 200 nm).

Although FIGS. 3 (a) and 3 (b) are drawn as if they have similar dimensions, the dimensions in the horizontal direction are actually completely different. That is, the dimension between the trenches 5 in the same figure is about 100 μm in FIG. 3A, and is as small as about 10 μm in FIG. 3B.

This state is shown in FIG. 3 (a) (diffusion check transistor for characteristic check) and FIG. 3 (b) (micro-sized transistor used as a product used inside the circuit).

Next, a photoresist 20 is formed on a portion where an emitter will be formed in the future by ordinary photolithography.
An opening is formed in (FIGS. 4A and 4B). Subsequently, the silicon nitride film is removed by anisotropic dry etching.

This state is shown in FIG. 4A (diffusion check transistor) and FIG. 4B (fine-sized transistor as a product).

[0053] The film thickness of the silicon oxide film 6 which is not covered in this case the base electrode polysilicon 7 (FIG. 4 (a)) is reduced slightly, a problem as long as the silicon collector layer 3 ₁ is not exposed Since it is not necessary, the drawing is drawn ignoring the decrease in film thickness.

Subsequently, the polysilicon for the base electrode is removed by dry etching to remove the photoresist.

This state is shown in FIG. 5 (a) (diffusion check transistor) and FIG. 5 (b) (transistor of fine dimensions as a product).

Further, a silicon nitride film is deposited to a thickness of 50 to 100 nm by the LPCVD method. Here, the silicon nitride film at the bottom of the opening is completely removed again by anisotropic dry etching. As a result, the side surface of the base electrode polysilicon 7 inside the opening is covered with the silicon nitride film 8.

This state is shown in FIG. 6A (diffusion check transistor) and FIG. 6B (fine-sized transistor of the product).

Next, exposed portions of the silicon collector layer 3 ₁ which constitutes the collector region by etching the silicon oxide film 6 of the opening bottom by HF-based etchant to form an opening 101 for the base form . The dimension of the lower surface of the polysilicon for the base electrode that exposes the silicon oxide film 6 by etching is smaller than the thickness of the polysilicon for the base electrode. For example, 100 nm to 25
0 nm is appropriate, and here, it was 200 nm.

This state is shown in FIG. 7A (diffusion check transistor) and FIG. 7B (fine sized transistor as a product).

At this time, in the transistor for diffusion check, one side of the opening 101 is formed so as to be located on the trench 5 as is apparent from FIG.

Next, an intrinsic base is formed by a selective epitaxial growth method as in the prior art. As a growth condition, an LPCVD method, a gas source MBE method, and the like can be used. Here, the UHV / CVD method will be described as an example.

Si ₂ H ₆ flow rate 3 sccm, temperature 605
C is an example of the condition.

[0063] At this time, the exposed portion of silicon collector layer 3 ₁ p-type single crystal silicon base region 9 is formed. At the same time, the polysilicon layer 10 P-type toward the silicon collector layer 3 ₁ which constitutes the collector region from the lower surface of the protruding portion of the base electrode polysilicon 7 is formed. The base region 9 and the polysilicon layer 10 continue to grow until they come into contact with each other.

Subsequently, the side wall of the silicon oxide film 11 is formed by depositing a silicon oxide film by LPCVD and performing anisotropic dry etching. The diffusion transistor shows the opening 101 and the product shows the opening 102. . This state is shown in FIG. 8 (a) (diffusion check transistor) and FIG. 8 (b) (fine-sized transistor as a product).

Subsequently, an opening 201 for the collector probe and an opening 301 for the emitter probe are formed by photolithography and dry etching. At this time, the emitter opening 101 and the emitter probe opening 301 are at least overlapped on the trench 5. The reason for this is that the trench for burying n ⁺ -type polysilicon in a later step is formed by the emitter opening 101 and the emitter probe opening 301.
This is because it is necessary to be connected with. At this time, the greenery buried in the trench in the overlap portion is slightly dented.

This state is shown in FIG. 9 (a) (vertical sectional view of the diffusion check transistor), FIG. 9 (b) (plan view of the diffusion check transistor), and FIG. 10 (transistor used in the circuit).

Further, n-type impurities (for example, phosphorus and arsenic)
Is deposited by LPCVD. In this case, about 5E20 cm ^{-3 of} phosphorus was added.
The thickness of the polysilicon is suitably about 1.5 to 2 times the dimension of the emitter opening 101, and
000 nm is suitable. Here, it was 8000 nm.

This state is shown in FIG. 11 (a) (diffusion check transistor) and FIG. 11 (b) (fine sized transistor as a product).

Subsequently, the polysilicon is etched back, and a base probe opening 401 is formed by a photolithography step and dry etching. Inside the opening, the base electrode polysilicon is exposed.

Next, a heat treatment for pushing the emitter is performed, and the base region 9 surrounded by the side wall of the silicon oxide film 11 is formed.
Then, an N-type emitter region 13 of single crystal silicon is formed.

In this way, the diffusion check transistor of the first embodiment shown in FIGS. 1A and 1B is formed.

The probe opening 2 of the transistor shown in FIG.
01, 301, and 401 all have dimensions large enough to directly probe, and the emitter region 13 is 1 μm.
m, which is a fine size of, for example, 0.2 to 0.6 μm, and realizes the same size as the inside of the circuit. At this stage, the state of formation of the emitter is directly measured, and if the pressing of the emitter is insufficient, additional pressing is performed.

Subsequently, a green film (for example, a silicon oxide film)
Transistor whose surface is covered with a product (Fig. 2
For (a)), the contacts reaching the polysilicon for the emitter, base, and collector electrodes are opened, and an aluminum-based alloy is sputtered, followed by photolithography and anisotropic dry etching to perform aluminum-based emitter electrode, base electrode, and Form a collector electrode.

Here, the extent to which the characteristics of the present invention are improved by the present invention as compared with the prior art will be described. This means that the characteristics of a transistor having an emitter of the same size as that of the transistor can be confirmed during the diffusion process.

[0075]

Next, a second embodiment of the present invention will be described with reference to the drawings.

FIG. 12 is a longitudinal sectional view of a diffusion check transistor for measurement according to a second embodiment of the present invention.

The operation is basically the same as that of the first embodiment.
The only difference is the base part. That is, the base formed by selective epitaxial growth is a p-type SiGe alloy (for example, a layer having a uniform Ge concentration of 10%, a 100 angstrom layer with no boron concentration added from below, and 7E
This is a laminated film in which a boron added region of 18 cm ^-3 has a thickness of 400 angstroms) and a silicon layer for forming an emitter by diffusion in the future (boron is not added and has a thickness of, for example, 200 angstroms). This laminated film is the intrinsic base layer 29. Naturally, the addition of Ge and boron to the polycrystalline layer 30 formed simultaneously also changes to reflect this.

The advantage of the second embodiment is that the current amplification factor h
In addition to the fact that the FE can be easily improved, and that it is easily affected by the leak current of the collector-base junction caused by lattice mismatch, the importance of monitoring during diffusion as in the present invention is high.

Next, a third embodiment is shown in FIG.

In this embodiment, the intrinsic base is formed by a diffusion method. That is, the base electrode polysilicon 37 is covered with the green film (for example, silicon nitride film) 38. There is a graft base 39 formed by diffusing boron from the base electrode polysilicon 37 in contact with the silicon collector 3. There is an intrinsic base 40 formed by ion implantation. An emitter region 42 is formed on the intrinsic base in a region surrounded by an absolutely green film (for example, a silicon oxide film) 41 by diffusing n-type impurities from the emitter electrode polysilicon 12.

The advantages of this embodiment will now be described. first,
In the second embodiment, of the side surfaces of the intrinsic bases 9 and 29, the portion located above the trench 5 is covered with a green film (for example, a silicon oxide film 11. However, this covering is insufficient. In this case, the emitter electrode polysilicon 12 comes into contact also with the side surface portion, in which case the diffusion of the n-type impurity also occurs from the side surface of the intrinsic base, resulting in the emitter region formed on the side surface. May come into contact with the silicon collector and not operate as a transistor.
In this embodiment, since the base and the emitter are sequentially diffused into the silicon collector 3, there is no danger that the emitter region and the silicon collector are short-circuited.

Next, a fourth embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG.

In this embodiment, the emitter opening 101 and the emitter probe opening 301 are connected by two or more grooves. The advantage of this embodiment is that the resistance is reduced by increasing the number of connection portions between the two, so that the influence of the voltage drop can be eliminated.

[0084]

As described above, according to the present invention, a transistor having an emitter having the same dimensions as a transistor used in a circuit can be formed during a diffusion step without a photolithography step for processing polysilicon for an emitter electrode. There is an effect that characteristics can be confirmed.

[Brief description of the drawings]

FIG. 1A is a vertical sectional view of a first embodiment of a diffusion check transistor for measurement used in a semiconductor manufacturing method of the present invention, and FIG. 1B is a plan view thereof.

2A is a longitudinal sectional view of a first embodiment of the semiconductor device of the present invention, and FIG. 2B is a plan view thereof.

FIGS. 3A and 3B are cross-sectional views of main processes of manufacturing a semiconductor device according to the first embodiment, showing process results up to the formation of a base electrode polysilicon 7 and a silicon nitrogen film 8, and FIG. FIG. 1B is a longitudinal sectional view of the product.

FIG. 4 is a sectional view of a main step of manufacturing the semiconductor device according to the first embodiment.
Shows the result of the process of removing the unnecessary portion of the silicon nitrogen film 8, (a) is a longitudinal sectional view of the diffusion check transistor,
(B) is a longitudinal sectional view of the product.

FIGS. 5A and 5B are cross-sectional views of a main process of manufacturing the semiconductor device of the first embodiment, showing a result of a process of removing a photoresistor and removing an unnecessary portion of polysilicon 7 for a base electrode, and FIG. (B) is a longitudinal sectional view of the product.

FIG. 6 is a cross-sectional view of a main process of manufacturing the semiconductor device according to the first embodiment, showing the process results up to the side surface coating of the base electrode polysilicon 7 and the removal of the silicon nitride film at the bottom of the opening; FIG. 4 is a vertical cross-sectional view of a transistor, and FIG.

FIGS. 7A and 7B are cross-sectional views of main processes of manufacturing the semiconductor device of the first embodiment, showing a result of a process in which an opening 101 is completed by removing a silicon oxide film in a corresponding portion, and FIG. And (b) are longitudinal sectional views of the product.

FIG. 8 is a sectional view of a main process of manufacturing the semiconductor device according to the first embodiment.
(A) is a longitudinal sectional view of a diffusion check transistor, and FIG.
(B) is a longitudinal sectional view of the product.

FIG. 9 is a cross-sectional view of a main process of manufacturing the semiconductor device according to the first embodiment, showing a result of forming openings 201 and 301;
(A) is a longitudinal sectional view of a diffusion check transistor, (b)
Is a plan view thereof.

FIG. 10 is a cross-sectional view of a main process of manufacturing the semiconductor device according to the first embodiment, and is a longitudinal cross-sectional view showing a result of a process of forming a product opening 202;

FIGS. 11A and 11B are cross-sectional views of main processes of manufacturing a semiconductor device according to the first embodiment, showing the results of an N ⁺ type polysilicon 12 deposition process, FIG.
(B) is a longitudinal sectional view of the product.

FIG. 12 is a sectional view of a second embodiment of a diffusion check transistor used in the method of manufacturing a semiconductor device according to the present invention.

FIG. 13 is a sectional view of a third embodiment of a diffusion check transistor used in the method of manufacturing a semiconductor device according to the present invention.

FIG. 14 is a plan view of a fourth embodiment of the diffusion check transistor used in the semiconductor device manufacturing method of the present invention.

FIG. 15 is a longitudinal sectional view showing a step of manufacturing a semiconductor device according to a conventional technique.

FIG. 16 is a cross-sectional view of a conventional semiconductor device.

[Explanation of symbols]

Reference Signs List 1 P ⁻ type silicon substrate 2 N ⁺ type buried layer 3 N ⁻ type silicon epitaxial layer for collector 3 ₁ silicon collector layer 3 ₂ silicon collector layer 4 P ⁺ layer for channel stopper 5 green trench buried trench 6 silicon oxide film 7 P Polysilicon film for ⁺ type base electrode 8 Green film 9 Silicon intrinsic base film 10 Polysilicon 11 Silicon oxide film 12 N ⁺ type polysilicon 12 a N ⁺ Polysilicon for emitter electrode 12 b N ⁺ Polysilicon for collector electrode 13 Single Crystal emitter region 14 LOCOS silicon oxide film 15 N ⁺ type collector lead 16 N-type single crystal emitter region 17 Silicon oxide film 18 a Emitter electrode 18 b Base electrode 18 c Collector electrode 20 Photoresist 29 Additive-free single-crystal SiGe film / p-type single-crystal SiGe
Intrinsic base layer composed of a film 30 Additive-free polycrystalline SiGe film / p-type polycrystalline SiGe
Layer composed of a film and undoped polycrystalline Si film 37 P ⁺ -type polysilicon film for base electrode 38 Insulating film 39 Graft base 40 Silicon intrinsic base film 41 Silicon oxide film 42 Single crystal emitter region 100 Silicon base 101 Emitter opening 102 Opening 103 Emitter opening 104 Opening 201 Collector probe opening 301 Emitter probe opening 401 Base probe opening

Claims (4)

(57) [Claims] A first conductive type first single crystal region (3 ₁ ) electrically insulated from another region by an insulator is used as a collector, and a first single crystal region (3 ₁ ) is formed on the _first single crystal region (3 ₁ ). The third single crystal region (9) of the second conductivity type is used as an authentic base,
In a diffusion check transistor for measurement using a fourth single crystal (13) of the first conductivity type as an emitter on a single crystal region (9), a probe can be brought into contact with the _first single crystal region (3 ₁ ) A first opening (201), which is in contact with the first single crystal region, and is capable of contacting the probe with a _second single crystal region (32) electrically insulated from the first single crystal region. a second opening (301), and an upper side of the first opening, the upper and <br/> fourth single crystal region of the side surface of the second opening (13) and a second opening Inside the connecting groove, the first conductive type first polycrystalline silicon (12-
b, 12a) , based on the measurement results of the electrical characteristics by directly probing the measurement probe contact electrodes of the first and second openings, and a first polycrystal of the first conductivity type. A fourth single crystal region of the first conductivity type (13) formed on the surface of the third single crystal region of the second conductivity type by diffusion of impurities of the first conductivity type from silicon. Characterized in that the indentation of the emitter is adjusted to a predetermined amount. 2. A third opening (401) for a base probe which is buried in the first conductivity type single crystal region (3 ₁ ) by a first conductivity type first polycrystalline silicon (12). 3. The diffusion check transistor for measurement according to claim 1, further comprising: 3. The method according to claim 1, wherein the third single crystal region of the second conductivity type has a boron-free SiGe alloy layer and a boron-doped SiGe alloy layer.
The diffusion check transistor for measurement according to claim 1, comprising a multilayer film of a SiGe alloy layer and a Si layer to which boron is not added . 4. Polycrystalline silicon (12a, 12b, 12) burying said first, second and third single crystal regions
The diffusion check transistor for measurement according to any one of claims 1 to 3, wherein are formed simultaneously.